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Электронный компонент: ADG442BN

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ADG441
ADG444
D4
S4
D3
S3
D2
S2
D1
S1
IN1
IN2
IN3
IN4
ADG442
D4
S4
D3
S3
D2
S2
D1
S1
IN1
IN2
IN3
IN4
SWITCHES SHOWN FOR A LOGIC "1" INPUT
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
LC
2
MOS Quad SPST Switches
ADG441/ADG442/ADG444
FEATURES
44 V Supply Maximum Ratings
V
SS
to V
DD
Analog Signal Range
Low On Resistance (< 70
)
Low
R
ON
(9
max)
Low R
ON
Match (3
max)
Low Power Dissipation
Fast Switching Times
t
ON
< 110 ns
t
OFF
< 60 ns
Low Leakage Currents ( 3 nA max)
Low Charge Injection (6 pC max)
Break-Before-Make Switching Action
Latch-Up Proof
Plug-In Upgrade for
DG201A/ADG201A, DG202A/ADG202A,
DG211/ADG211A
Plug in Replacement for DG441/DG442/DG444
APPLICATIONS
Audio and Video Switching
Automatic Test Equipment
Precision Data Acquisition
Battery Powered Systems
Sample Hold Systems
Communication Systems
FUNCTIONAL BLOCK DIAGRAMS
GENERAL DESCRIPTION
The ADG441, ADG442 and ADG444 are monolithic CMOS
devices comprising four independently selectable switches. They
are designed on an enhanced LC
2
MOS process that provides
low power dissipation yet gives high switching speed and low on
resistance.
The on resistance profile is very flat over the full analog input
range ensuring good linearity and low distortion when switching
audio signals. High switching speed also makes the parts suit-
able for video signal switching. CMOS construction ensures
ultralow power dissipation making the parts ideally suited for
portable and battery powered instruments.
The ADG441, ADG442 and ADG444 contain four indepen-
dent SPST switches. Each switch of the ADG441 and ADG444
turns on when a logic low is applied to the appropriate control
input. The ADG442 switches are turned on with a logic high on
the appropriate control input. The ADG441 and ADG444
switches differ in that the ADG444 requires a 5 V logic power
supply which is applied to the V
L
pin. The ADG441 and
ADG442 do not have a V
L
pin, the logic power supply being
generated internally by an on-chip voltage generator.
Each switch conducts equally well in both directions when ON
and has an input signal range that extends to the power sup-
plies. In the OFF condition, signal levels up to the supplies are
blocked. All switches exhibit break-before-make switching action
for use in multiplexer applications. Inherent in the design is low
charge injection for minimum transients when switching the
digital inputs.
PRODUCT HIGHLIGHTS
1. Extended Signal Range
The ADG441/ADG442/ADG444 are fabricated on an en-
hanced LC
2
MOS, trench-isolated process, giving an in-
creased signal range that extends to the supply rails.
2. Low Power Dissipation
3. Low R
ON
4. Trench Isolation Guards Against Latch Up
A dielectric trench separates the P and N channel transistors
thereby preventing latch up even under severe overvoltage
conditions.
5. Break-Before-Make Switching
This prevents channel shorting when the switches are config-
ured as a multiplexer.
6. Single Supply Operation
For applications where the analog signal is unipolar, the
ADG441/ADG442/ADG444 can be operated from a single
rail power supply. The parts are fully specified with a single
+12 V power supply.
REV. 0
2
B Version
T Version
40
C to
55
C to
Parameter
+25
C
+85
C
+25
C
+125
C
Units
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
V
SS
to V
DD
V
SS
to V
DD
V
R
ON
40
40
typ
V
D
=
8.5 V, I
S
= 10 mA
70
85
70
85
max
V
DD
= +13.5 V, V
SS
= 13.5 V
R
ON
4
4
typ
8.5 V
V
D
+8.5 V
9
9
max
R
ON
Match
1
1
typ
V
D
= 0 V, I
S
= 10 mA
3
3
max
LEAKAGE CURRENTS
V
DD
= +16.5 V, V
SS
= 16.5 V
Source OFF Leakage I
S
(OFF)
0.01
0.01
nA typ
V
D
=
15.5 V, V
S
= 15.5 V;
0.5
3
0.5
20
nA max
Test Circuit 2
Drain OFF Leakage I
D
(OFF)
0.01
0.01
nA typ
V
D
=
15.5 V, V
S
= 15.5 V;
0.5
3
0.5
20
nA max
Test Circuit 2
Channel ON Leakage I
D
, I
S
(ON)
0.08
0.08
nA typ
V
S
= V
D
=
15.5 V;
0.5
3
0.5
40
nA max
Test Circuit 3
DIGITAL INPUTS
Input High Voltage, V
INH
2.4
2.4
V min
Input Low Voltage, V
INL
0.8
0.8
V max
Input Current
I
INL
or I
INH
0.00001
0.00001
A typ
V
IN
= V
INL
or V
INH
0.5
0.5
A max
DYNAMIC CHARACTERISTICS
2
t
ON
85
85
ns typ
R
L
= 1 k
, C
L
= 35 pF;
110
170
110
170
ns max
V
S
=
10 V; Test Circuit 4
t
OFF
45
45
ns typ
R
L
= 1 k
, C
L
= 35 pF;
60
80
60
80
ns max
V
S
=
10 V; Test Circuit 4
t
OPEN
30
30
ns typ
R
L
= 1 k
, C
L
= 35 pF;
Charge Injection
1
1
pC typ
V
S
= 0 V, R
S
= 0
, C
L
= 1 nF;
6
6
pC max
V
DD
= +15 V, V
SS
= 15 V;
Test Circuit 5
OFF Isolation
60
60
dB typ
R
L
= 50
, C
L
= 5 pF;
f = 1 MHz; Test Circuit 6
Channel-to-Channel Crosstalk
100
100
dB typ
R
L
= 50
, C
L
= 5 pF;
f = 1 MHz; Test Circuit 7
C
S
(OFF)
4
4
pF typ
f = 1 MHz
C
D
(OFF)
4
4
pF typ
f = 1 MHz
C
D
, C
S
(ON)
16
16
pF typ
f = 1 MHz
POWER REQUIREMENTS
V
DD
= +16.5 V, V
SS
= 16.5 V
I
DD
Digital Inputs = 0 V or 5 V
ADG441/ADG442
80
80
A max
ADG444
0.001
0.001
A typ
1
2.5
1
2.5
A max
I
SS
0.0001
0.0001
A typ
1
2.5
1
2.5
A max
I
L
(ADG444 Only)
0.001
0.001
A typ
V
L
= +5.5 V
1
2.5
1
2.5
A max
NOTES
1
Temperature ranges are as follows: B Versions: 40
C to +85
C; T Versions: 55
C to +125
C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
ADG441/ADG442/ADG444SPECIFICATIONS
1
Dual Supply
(V
DD
= +15 V
10%, V
SS
= 15 V
10%, V
L
= +5 V
10% (ADG444), GND = 0 V, unless otherwise noted)
ORDERING GUIDE
Model
1
Temperature Range
Package Option
2
ADG441BN
40
C to +85
C
N-16
ADG441BR
40
C to +85
C
R-16A
ADG441TQ
55
C to +125
C
Q-16
ADG442BN
40
C to +85
C
N-16
ADG442BR
40
C to +85
C
R-16A
ADG444BN
40
C to +85
C
N-16
ADG444BR
40
C to +85
C
R-16A
N
OTES
1
To order MIL-STD-883, Class B processed parts, add /883B to T grade part
numbers.
2
N = Plastic DIP, R = 0.15" Small Outline IC (SOIC), Q = Cerdip.
REV. 0
3
ADG441/ADG442/ADG444
Table I. Truth Table
ADG441/ADG444
ADG442
Switch
IN
IN
Condition
0
1
ON
1
0
OFF
B Version
T Version
40
C to
55
C to
Parameter
+25
C
+85
C
+25
C
+125
C
Units
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 to V
DD
0 to V
DD
V
R
ON
70
70
typ
V
D
= +3 V, +8 V, I
S
= 10 mA;
110
130
110
130
max
V
DD
= +10.8 V
R
ON
4
4
typ
+3 V
V
D
+8 V
9
9
max
R
ON
Match
1
1
typ
V
D
= 6 V, I
S
= 10 mA
3
3
max
LEAKAGE CURRENT
V
DD
= +13.2 V
Source OFF Leakage I
S
(OFF)
0.01
0.01
nA typ
V
D
= 12.2 V/1 V, V
S
= 1 V/12.2 V;
0.5
3
0.5
20
nA max
Test Circuit 2
Drain OFF Leakage I
D
(OFF)
0.01
0.01
nA typ
V
D
= 12.2 V/1 V, V
S
= 1 V/12.2 V;
0.5
3
0.5
20
nA max
Test Circuit 2
Channel ON Leakage I
D
, I
S
(ON)
0.08
0.08
nA typ
V
S
= V
D
= 12.2 V/1 V;
0.5
3
0.5
40
nA max
Test Circuit 3
DIGITAL INPUTS
Input High Voltage, V
INH
2.4
2.4
V min
Input Low Voltage, V
INL
0.8
0.8
V max
Input Current
I
INL
or I
INH
0.00001
0.00001
A typ
V
IN
= V
INL
or V
INH
0.5
0.5
A max
DYNAMIC CHARACTERISTICS
2
t
ON
105
105
ns typ
R
L
= 1 k
, C
L
= 35 pF;
150
220
150
220
ns max
V
S
= +8 V; Test Circuit 4
t
OFF
40
40
ns typ
R
L
= 1 k
, C
L
= 35 pF;
60
100
60
100
ns max
V
S
= +8 V; Test Circuit 4
t
OPEN
50
50
ns typ
R
L
= 1 k
, C
L
= 35 pF;
Charge Injection
2
2
pC typ
V
S
= 6 V, R
S
= 0
, C
L
= 1 nF;
6
6
pC max
V
DD
= +12 V, V
SS
= 0 V;
Test Circuit 5
OFF Isolation
60
60
dB typ
R
L
= 50
, C
L
= 5 pF, f = 1 MHz;
Test Circuit 6
Channel-to-Channel Crosstalk
100
100
dB typ
R
L
= 50
, C
L
= 5 pF, f = 1 MHz;
Test Circuit 7
C
S
(OFF)
7
7
pF typ
f = 1 MHz
C
D
(OFF)
10
10
pF typ
f = 1 MHz
C
D
, C
S
(ON)
16
16
pF typ
f = 1 MHz
POWER REQUIREMENTS
V
DD
= +13.2 V
I
DD
Digital Inputs = 0 V or 5 V
ADG441/ADG442
80
80
A max
ADG444
0.001
0.001
A typ
1
2.5
1
2.5
A max
I
L
(ADG444 Only)
0.001
0.001
A typ
V
L
= +5.5 V
1
2.5
1
2.5
A max
NOTES
1
Temperature ranges are as follows: B Versions: 40
C to +85
C; T Versions: 55
C to +125
C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
Single Supply
(V
DD
= +12 V
10%, V
SS
= 0 V, V
L
= +5 V
10% (ADG444), GND = 0 V, unless otherwise noted)
ADG441/ADG442/ADG444
REV. 0
4
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25
C unless otherwise noted)
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +25 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to 25 V
V
L
to GND . . . . . . . . . . . . . . . . . . . . . . 0.3 V to V
DD
+ 0.3 V
Analog, Digital Inputs
2
. . . . . . . . . . . . V
SS
2 V to V
DD
+ 2 V
or 30 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle Max)
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . . 40
C to +85
C
Extended (T Version) . . . . . . . . . . . . . . . . 55
C to +125
C
Storage Temperature Range . . . . . . . . . . . . . 65
C to +150
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150
C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 900 mW
JA
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 76
C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . +300
C
Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW
JA
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 177
C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . +260
C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 600 mW
JA
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 77
C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220
C
NOTES
1
Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability. Only
one absolute maximum rating may be applied at any one time.
2
Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
ADG441/ADG442 PIN CONFIGURATION (DIP/SOIC)
NC = NO CONNECT
IN1
D1
IN2
D2
GND
S4
D4
NC
S3
D3
S1
V
SS
S2
V
DD
IN4
IN3
1
2
16
15
5
6
7
12
11
10
3
4
14
13
8
9
TOP VIEW
(Not to Scale)
ADG441
ADG442
ADG444 PIN CONFIGURATION (DIP/SOIC)
TERMINOLOGY
V
DD
Most Positive Power Supply Potential.
V
SS
Most Negative Power Supply Potential in dual
supplies. In single supply applications, it may be
connected to ground.
V
L
Logic Power Supply (+5 V).
GND
Ground (0 V) Reference.
S
Source Terminal. May be an input or output.
D
Drain Terminal. May be an input or output.
IN
Logic Control Input.
R
ON
Ohmic resistance between D and S.
R
ON
Match
Difference between the R
ON
of any two channels.
I
S
(OFF)
Source leakage current with the switch "OFF."
I
D
(OFF)
Drain leakage current with the switch "OFF."
I
D
, I
S
(ON)
Channel leakage current with the switch "ON."
V
D
(V
S
)
Analog voltage on terminals D, S.
C
S
(OFF)
"OFF" Switch Source Capacitance.
C
D
(OFF)
"OFF" Switch Drain Capacitance.
C
D
, C
S
(ON)
"ON" Switch Capacitance.
t
ON
Delay between applying the digital control
input and the output switching on.
t
OFF
Delay between applying the digital control
input and the output switching off.
t
OPEN
Break-Before-Make Delay when switches are
configured as a multiplexer.
Crosstalk
A measure of unwanted signal which is coupled
through from one channel to another as a result
of parasitic capacitance.
Off Isolation
A measure of unwanted signal coupling through
an "OFF" switch.
Charge
A measure of the glitch impulse transferred from
Injection
the digital input to the analog output during
switching.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
IN1
D1
IN2
D2
GND
S4
D4
V
L
S3
D3
S1
V
SS
S2
V
DD
IN4
IN3
1
2
16
15
5
6
7
12
11
10
3
4
14
13
8
9
TOP VIEW
(Not to Scale)
ADG444
ADG441/ADG442/ADG444
REV. 0
5
TRENCH ISOLATION
In the ADG441, ADG442 and ADG444, an insulating oxide
layer (trench) is placed between the NMOS and the PMOS
transistors of each CMOS switch. Parasitic junctions, which oc-
cur between the transistors in junction isolated switches, are
eliminated, the result being a completely latch-up proof switch.
In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode becomes forward biased. A silicon-controlled rectifier
(SCR) type circuit is formed by the two transistors causing a sig-
nificant amplification of the current which, in turn, leads to
latch up. With trench isolation, this diode is removed, the result
being a latch-up proof switch.
Trench isolation also leads to lower leakage currents. The
ADG441, ADG442 and ADG444 have a leakage current
of 0.5 nA as compared with a leakage current of several
nanoamperes in non-trench isolated switches. Leakage current is
an important parameter in sample-and-hold circuits, this current
being responsible for the discharge of the holding capacitor with
time causing droop. The ADG441/ADG442/ADG444's low
leakage current, along with its fast switching speeds, make it
suitable for fast and accurate sample-and-hold circuits.
Typical Performance Characteristics
NMOS
PMOS
P-WELL
N-WELL
BURIED OXIDE LAYER
SUBSTRATE (BACK GATE)
TRENCH
LOCOS
Figure 1. Trench Isolation
170
10
15
90
50
3
0
130
9
R
ON
V
D
(V
S)
Volts
6
12
T
A
= +25
C
150
110
70
30
V
DD
= +5V
V
SS
= 0V
V
DD
= +10V
V
SS
= 0V
V
DD
= +12V
V
SS
= 0V
V
DD
= +15V
V
SS
= 0V
100
20
15
60
40
10
15
80
10
0
R
ON
V
D
(V
S)
Volts
5
5
T
A
= +25
C
V
DD
= +5V
V
SS
= 5V
V
DD
= +12V
V
SS
= 12V
V
DD
= +15V
V
SS
= 15V
V
DD
= +10V
V
SS
= 10V
Figure 3. R
ON
as a Function of V
D
(V
S
): Single Supply
Figure 2. R
ON
as a Function of V
D
(V
S
): Dual Supply
ADG441/ADG442/ADG444
REV. 0
6
100
20
15
15
80
40
10
60
5
10
0
5
+125
C
+25
C
+85
C
V
DD
= +15V
V
SS
= 15V
R
ON
V
D
(V
S
) Volts
Figure 4. R
ON
as a Function of V
D
(V
S
) for Different
Temperatures
0.02
0.02
15
0.01
10
15
0.00
0.01
10
5
0
5
V
S
, V
D
Volts
LEAKAGE CURRENT nA
V
DD
= +15V
V
SS
= 15V
T
A
= +25
C
I
S
(OFF)
I
D
(OFF)
I
D
(ON)
Figure 5. Leakage Currents as a Function of V
S
(V
D
)
120
50
10M
60
1k
90
110
1M
100k
10k
FREQUENCY Hz
dB
100
70
80
V
DD
= +15V
V
SS
= 15V
CROSSTALK
OFF ISOLATION
Figure 6. Crosstalk and Off Isolation vs. Frequency
120
20
0
12
80
40
2
60
8
10
6
4
V
D
(V
S
) Volts
R
ON
+25
C
100
V
DD
= +12V
V
SS
= 0V
+85
C
+125
C
Figure 7. R
ON
as a Function of V
D
(V
S
) for Different
Temperatures
0.010
0.010
12
0.005
2
0
0.000
0.005
10
8
6
4
V
S
, V
D
Volts
LEAKAGE CURRENT nA
V
DD
= +12V
V
SS
= 0V
T
A
= +25
C
I
D
(ON)
I
S
(OFF)
I
D
(OFF)
Figure 8. Leakage Currents as a Function of V
S
(V
D
)
20
20
15
10
6
15
9
6
0
9
V
S
Volts
Q pC
10
0
12
3
3
12
C
L
= 1nF
V
DD
= +15V
V
SS
= 15V
V
DD
= +12V
V
SS
= 0V
Figure 9. Charge Injection vs. Source Voltage
ADG441/ADG442/ADG444
REV. 0
7
120
40
20
80
60
12
10
100
16
t
ns
SUPPLY VOLTAGE
Volts
14
18
V
IN
= +8V
t
ON
t
OFF
Figure 10. Switching Time vs. Bipolar Supply
160
20
20
40
10
8
100
140
18
16
14
12
SUPPLY VOLTAGE Volts
t
ns
120
60
80
V
IN
= +8V
t
ON
t
OFF
Figure 11. Switching Time vs. Single Supply
Test Circuits
V1
I
DS
S
D
V
S
R
ON
= V
1
/I
DS
Test Circuit 1. On Resistance
Test Circuit 3. On Leakage
Test Circuit 2. Off Leakage
S
D
V
S
A
A
V
D
I
D
(OFF)
I
S
(OFF)
S
D
V
S
A
V
D
I
D
(ON)
S
D
V
S
IN
GND
V
SS
0.1
F
15V
R
L
1k
C
L
35pF
V
OUT
0.1
F
0.1
F
V
DD
V
L
+15V
+5V
t
OFF
90%
90%
50%
50%
50%
50%
3V
ADG442
ADG441/ADG444
V
IN
V
IN
V
OUT
3V
t
ON
Test Circuit 4. Switching Times
ADG441/ADG442/ADG444
REV. 0
8
PRINTED IN U.S.A.
C1890184/94
S
D
V
S
IN
GND
V
SS
15V
C
L
1nF
V
OUT
V
DD
V
L
+15V
+5V
R
S
3V
V
IN
V
OUT
V
OUT
Q
INJ
= C
L
V
OUT
Test Circuit 5. Charge Injection
S
D
V
S
IN
GND
V
SS
0.1
F
15V
R
L
50
V
OUT
0.1
F
0.1
F
V
DD
V
L
+15V
+5V
V
IN
Test Circuit 6. Off Isolation
S
D
V
S
GND
V
SS
0.1
F
15V
0.1
F
0.1
F
V
DD
V
L
+15V
+5V
V
IN1
S
V
IN2
NC
50
V
OUT
R
L
50
CHANNEL-TO-CHANNEL CROSSTALK = 20
LOG
V
S
/V
OUT
Test Circuit 7. Channel-to-Channel Crosstalk
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic DIP (N-16)
0.011
(0.28)
0.18
(4.57)
MAX
0.3 (7.62)
PIN 1
1
8
9
16
0.25
(6.35)
0.31
(7.87)
0.87 (22.1) MAX
0.125
(3.18)
MIN
0.035
(0.89)
0.18 (4.57)
SEATING
PLANE
0.018 (0.46)
0.033 (0.84)
0.1 (2.54)
BSC
Small Outline IC (R-16A)
8
9
16
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
1
0.0688 (1.75)
0.0532 (1.35)
0.3937 (10.00)
0.3859 (9.80)
0.0500 (1.27)
BSC
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0
8
0.0099 (0.25)
0.0075 (0.19)
45
0.0196 (0.50)
0.0099 (0.25)
0.0500 (1.27)
0.0160 (0.41)
Cerdip (Q-16)
0.015 (0.381)
0.008 (0.204)
0.320 (8.13)
0.290 (7.37)
PIN 1
0.310 (7.87)
0.220 (5.59)
1
8
9
16
0.840 (21.34) MAX
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
0.200
(5.08)
MAX
PLANE
SEATING
0.022 (0.558)
0.014 (0.356)
0.100 (2.54)
BSC
0.070 (1.78)
0.30 (0.76)
ADG441/ADG442/ADG444
REV. 0
9
ORDERING GUIDE
Model
1
Temperature Range
Package Option
2
ADG441BN
40
C to +85
C
N-16
ADG441BR
40
C to +85
C
R-16A
ADG441TQ
55
C to +125
C
Q-16
ADG442BN
40
C to +85
C
N-16
ADG442BR
40
C to +85
C
R-16A
ADG444BN
40
C to +85
C
N-16
ADG444BR
40
C to +85
C
R-16A
NOTES
1
To order MIL-STD-883, Class B processed parts, add /883B to T grade part
numbers.
2
N = Plastic DIP, R = 0.15" Small Outline IC (SOIC), Q = Cerdip. For outline
information see Package Information section.
FOR CATALOG