2. ON channel turns off while fault exists.
3. Low R
ON.
4. Fast Switching Times.
5. Break-Before-Make Switching.
Switches are guaranteed break-before-make so that input
signals are protected against momentary shorting.
6. Trench Isolation Eliminates Latch-up.
A dielectric trench separates the p and n-channel MOSFETs
thereby preventing latch-up.
ORDERING GUIDE
Model
1
Temperature Range
Package Option
2
ADG508FBN
40
C to +85
C
N-16
ADG508FBRN
40
C to +85
C
R-16N
ADG508FBRW
40
C to +85
C
R-16W
ADG508FTQ
55
C to +125
C
Q-16
ADG509FBN
40
C to +85
C
N-16
ADG509FBRN
40
C to +85
C
R-16N
ADG509FBRW
40
C to +85
C
R-16W
ADG509FTQ
55
C to +125
C
Q-16
ADG528FBN
40
C to +85
C
N-18
ADG528FBP
40
C to +85
C
P-20A
ADG528FTQ
55
C to +125
C
Q-18
NOTES
1
To order MIL-STD-883, Class B processed parts, add /883B to T grade part
numbers.
2
N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip;
RN = 0.15" Small Outline IC (SOIC), RW = 0.3" Small Outline IC (SOIC).
FUNCTIONAL BLOCK DIAGRAMS
S1
S8
A0
D
ADG508F/ADG528F
A1 A2 EN
1 OF 8
DECODER
ADG528F
ONLY
WR
RS
S1A
A0
DA
ADG509F
A1
S4A
S1B
S4B
DB
EN
1 OF 4
DECODER
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
ADG508F/ADG509F/ADG528F*
4/8 Channel Fault-Protected
Analog Multiplexers
*Patent Pending.
GENERAL DESCRIPTION
The ADG508F, ADG509F and ADG528F are CMOS analog
multiplexers, the ADG508F and ADG528F comprising eight
single channels and the ADG509F comprising four differential
channels. These multiplexers provide fault protection. Using a
series n-channel, p-channel, n-channel MOSFET structure,
both device and signal source protection is provided in the event
of an overvoltage or power loss. The multiplexer can withstand
continuous overvoltage inputs from 40 V to +55 V. During
fault conditions, the multiplexer input (or output) appears as an
open circuit and only a few nanoamperes of leakage current will
flow. This protects not only the multiplexer and the circuitry
driven by the multiplexer, but also protects the sensors or signal
sources that drive the multiplexer.
The ADG508F and ADG528F switch one of eight inputs to a
common output as determined by the 3-bit binary address lines
A0, A1 and A2. The ADG509F switches one of four differential
inputs to a common differential output as determined by the 2-
bit binary address lines A0 and A1. The ADG528F has on-chip
address and control latches that facilitate microprocessor inter-
facing. An EN input on each device is used to enable or disable
the device. When disabled, all channels are switched OFF.
PRODUCT HIGHLIGHTS
1. Fault Protection.
The ADG508F/ADG509F/ADG528F can withstand con-
tinuous voltage inputs from 40 V to +55 V. When a fault
occurs due to the power supplies being turned off, all the
channels are turned off and only a leakage current of a few
nanoamperes flows.
FEATURES
Low On Resistance (300 typ)
Fast Switching Times
t
ON
250 ns max
t
OFF
250 ns max
Low Power Dissipation (3.3 mW max)
Fault and Overvoltage Protection (40 V to +55 V)
All Switches OFF with Power Supply OFF
Analog Output of ON Channel Clamped Within Power
Supplies If an Overvoltage Occurs
Latch-Up Proof Construction
Break Before Make Construction
TTL and CMOS Compatible Inputs
APPLICATIONS
Existing Multiplexer Applications (Both Fault-Protected
and Nonfault-Protected)
New Designs Requiring Multiplexer Functions
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1998
REV. C
2
(V
DD
= +15 V 10%, V
SS
= 15 V 10%, GND = 0 V, unless otherwise noted)
Dual Supply
B Version
T Version
40 C to
55 C to
Parameter
+25 C
+85 C
+25 C
+125 C
Units
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
V
SS
+ 3
V
SS
+ 3
V min
V
DD
1.5
V
DD
1.5
V max
R
ON
300
350
300
400
typ
10 V < V
S
< +10 V, I
S
= 1 mA;
V
DD
= +15 V
10%, V
SS
= 15 V
10%
400
450
max
10 V < V
S
< +10 V, I
S
= 1 mA;
V
DD
= +15 V
5%, V
SS
= 15 V
5%
R
ON
Drift
0.6
0.6
%/
C typ V
S
= 0 V, I
S
= 1 mA
R
ON
Match
5
5
% max
V
S
= 0 V, I
S
= 1 mA
LEAKAGE CURRENTS
Source OFF Leakage I
S
(OFF)
0.02
0.02
nA typ
V
D
=
10 V, V
S
= 10 V;
1
50
1
50
nA max
Test Circuit 2
Drain OFF Leakage I
D
(OFF)
0.04
0.04
nA typ
V
D
=
10 V, V
S
= 10 V;
ADG508F/ADG528F
1
60
1
200
nA max
Test Circuit 3
ADG509F
1
30
1
100
nA max
Channel ON Leakage I
D
, I
S
(ON)
0.04
0.04
nA typ
V
S
= V
D
=
10 V;
ADG508F/ADG528F
1
60
1
200
nA max
Test Circuit 4
ADG509F
1
30
1
100
nA max
FAULT
Output Leakage Current
0.02
0.02
nA typ
V
S
=
33 V, V
D
= 0 V, Test Circuit 3
(With Overvoltage)
2
2
2
A max
Input Leakage Current
0.005
0.005
A typ
V
S
=
25 V, V
D
= 10 V, Test Circuit 5
(With Overvoltage)
2
2
A max
Input Leakage Current
0.001
0.001
A typ
V
S
=
25 V, V
D
= V
EN
= A0, A1, A2 = 0 V
(With Power Supplies OFF)
2
2
A max
Test Circuit 6
DIGITAL INPUTS
Input High Voltage, V
INH
2.4
2.4
V min
Input Low Voltage, V
INL
0.8
0.8
V max
Input Current
I
INL
or I
INH
1
1
A max
V
IN
= 0 or V
DD
C
IN
, Digital Input Capacitance
5
5
pF typ
DYNAMIC CHARACTERISTICS
2
t
TRANSITION
200
200
ns typ
R
L
= 1 M
, C
L
= 35 pF;
300
400
300
400
ns max
V
S1
=
10 V, V
S8
= 10 V; Test Circuit 7
t
OPEN
50
50
ns typ
R
L
= 1 k
, C
L
= 35 pF;
25
10
25
10
ns min
V
S
= +5 V; Test Circuit 8
t
ON
(EN, WR)
200
200
ns typ
R
L
= 1 k
, C
L
= 35 pF;
250
400
250
400
ns max
V
S
= +5 V; Test Circuit 9
t
OFF
(EN, RS)
200
200
ns typ
R
L
= 1 k
, C
L
= 35 pF;
250
400
250
400
ns max
V
S
= +5 V; Test Circuit 9
t
SETT
, Settling Time
0.1%
1
1
s typ
R
L
= 1 k
, C
L
= 35 pF;
0.01%
2.5
2.5
s typ
V
S
= +5 V
ADG528F Only
t
W
, Write Pulsewidth
100
120
100
200
ns min
t
S
, Address, Enable Setup Time
100
100
ns min
t
H
, Address, Enable Hold Time
10
10
ns min
t
RS
, Reset Pulsewidth
100
100
ns min
Charge Injection
4
4
pC typ
V
S
= 0 V, R
S
= 0
, C
L
= 1 nF; Test Circuit 12
OFF Isolation
68
68
dB typ
R
L
= 1 k
, C
L
= 15 pF, f = 100 kHz;
50
50
dB min
V
S
= 7 V rms; Test Circuit 13
C
S
(OFF)
5
5
pF typ
C
D
(OFF)
ADG508F/ADG528F
50
50
pF typ
ADG509F
25
25
pF typ
POWER REQUIREMENTS
I
DD
0.1
0.2
0.1
0.2
mA max
V
IN
= 0 V or 5 V
I
SS
0.1
0.1
0.1
0.1
mA max
NOTES
1
Temperature ranges are as follows: B Version: 40
C to +85
C; T Version: 55
C to +125
C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
ADG508F/ADG509F/ADG528FSPECIFICATIONS
1
ADG508F/ADG509F/ADG528F
REV. C
3
Table I. ADG508F Truth Table
A2
A1
A0
EN
ON SWITCH
X
X
X
0
NONE
0
0
0
1
1
0
0
1
1
2
0
1
0
1
3
0
1
1
1
4
1
0
0
1
5
1
0
1
1
6
1
1
0
1
7
1
1
1
1
8
X = Don't Care
Table II. ADG509F Truth Table
A1
A0
EN
ON SWITCH PAIR
X
X
0
NONE
0
0
1
1
0
1
1
2
1
0
1
3
1
1
1
4
X = Don't Care
Table III. ADG528F Truth Table
ON
A2
A1
A0
EN
WR
RS
SWITCH
X
X
X
X
g
1
Retains Previous Switch Condition
X
X
X
X
X
0
NONE (Address and Enable Latches Cleared)
X
X
X
0
0
1
NONE
0
0
0
1
0
1
1
0
0
1
1
0
1
2
0
1
0
1
0
1
3
0
1
1
1
0
1
4
1
0
0
1
0
1
5
1
0
1
1
0
1
6
1
1
0
1
0
1
7
1
1
1
1
0
1
8
X = Don't Care
TIMING DIAGRAMS (ADG528F)
t
W
50%
50%
t
S
t
H
0.8V
2V
3V
WR
0V
3V
0V
A0, A1, A2
EN
Figure 1.
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive; there-
fore, while WR is held low, the latches are transparent and the
switches respond to the address and enable inputs. This input
data is latched on the rising edge of WR.
t
RS
50%
50%
0.8V
O
3V
RS
0V
V
O
SWITCH
OUTPUT
t
OFF
(
RS
)
0V
Figure 2.
Figure 2 shows the Reset Pulsewidth, t
RS
, and the Reset Turn-
off Time, t
OFF
(RS).
Note: All digital input signals rise and fall times are measured
from 10% to 90% of 3 V. t
R
= t
F
= 20 ns.
REV. C
4
ADG508F/ADG509F/ADG528F
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25
C unless otherwise noted)
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44 V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +25 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to 25 V
V
EN
, V
A
Digital Input . . . . . . . 0.3 V to V
DD
+ 2 V or 20 mA,
Whichever Occurs First
V
S
, Analog Input Overvoltage with Power ON . . . . . V
SS
25 V
to V
DD
+ 40 V
V
S
, Analog Input Overvoltage with Power OFF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 V to +55 V
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 20 mA
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle max) . . . . . . . . . . . 40 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . 40
C to +85
C
Extended (T Version) . . . . . . . . . . . . . . . . 55
C to +125
C
Storage Temperature Range . . . . . . . . . . . . . 65
C to +150
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150
C
Cerdip Package
JA
, Thermal Impedance
16-Lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
C/W
18-Lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +300
C
Plastic Package
JA
, Thermal Impedance
16-Lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
C
18-Lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
C
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260
C
SOIC Package
JA
, Thermal Impedance
Narrow Body . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
C/W
Wide Body . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220
C
PLCC Package
JA
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 90
C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220
C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
ADG508F/ADG509F PIN CONFIGURATIONS
DIP/SOIC DIP/SOIC
A0
EN
A1
A2
S2
S3
S4
S5
S6
S7
S1
GND
V
DD
D
S8
1
2
16
15
5
6
7
12
11
10
3
4
14
13
8
9
TOP VIEW
(Not to Scale)
ADG508F
V
SS
A0
EN
A1
GND
S2A
S3A
S4A
S2B
S3B
S4B
V
SS
S1A
V
DD
S1B
DA
DB
1
2
16
15
5
6
7
12
11
10
3
4
14
13
8
9
TOP VIEW
(Not to Scale)
ADG509F
ADG528F PIN CONFIGURATIONS
DIP PLCC
WR
A0
RS
A1
S1
S2
S3
S5
S6
EN
V
SS
A2
S4
S7
D
S8
V
DD
GND
1
2
18
17
5
6
7
14
13
12
3
4
16
15
8
11
9
10
TOP VIEW
(Not to Scale)
ADG528F
EN
V
SS
S3
S1
S2
A0
WR
A1
NC
RS
19
3
1
2
20
4
5
8
6
7
12 13
9
11
10
18
17
14
16
15
TOP VIEW
(Not to Scale)
ADG528F
A2
GND
S6
V
DD
S5
S4
D
S7
S8
NC
NC = NO CONNECT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ADG508F/ADG509F/ADG528F
REV. C
5
TERMINOLOGY
V
DD
Most positive power supply potential.
V
SS
Most negative power supply potential.
GND
Ground (0 V) reference.
R
ON
Ohmic resistance between D and S.
R
ON
Drift
Change in R
ON
when temperature changes
by one degree Celsius.
R
ON
Match
Difference between the R
ON
of any two
channels.
I
S
(OFF)
Source leakage current when the switch is
off.
I
D
(OFF)
Drain leakage current when the switch is off.
I
D
, I
S
(ON)
Channel leakage current when the switch is
on.
V
D
(V
S
)
Analog voltage on terminals D, S.
C
S
(OFF)
Channel input capacitance for "OFF"
condition.
C
D
(OFF)
Channel output capacitance for "OFF"
condition.
C
D
, C
S
(ON)
"ON" switch capacitance.
C
IN
Digital input capacitance.
t
ON
(EN)
Delay time between the 50% and 90% points
of the digital input and switch "ON"
condition.
t
OFF
(EN)
Delay time between the 50% and 90% points
of the digital input and switch "OFF"
condition.
t
TRANSITION
Delay time between the 50% and 90% points
of the digital inputs and the switch "ON"
condition when switching from one address
state to another.
t
OPEN
"OFF" time measured between 80% points of
both switches when switching from one
address state to another.
V
INL
Maximum input voltage for Logic "0".
V
INH
Minimum input voltage for Logic "1".
I
INL
(I
INH
)
Input current of the digital input.
Off Isolation
A measure of unwanted signal coupling
through an "OFF" channel.
Charge Injection
A measure of the glitch impulse transferred
from the digital input to the analog output
during switching.
I
DD
Positive supply current.
I
SS
Negative supply current.
Typical Performance Graphs
2000
1000
0
15
5
15
5
0
10
10
500
1750
1500
1250
750
250
V
D
(V
S
) Volts
R
ON
T
A
= +25 C
V
DD
= +5V
V
SS
= 5V
V
DD
= +10V
V
SS
= 10V
V
DD
= +15V
V
SS
= 15V
Figure 3. On Resistance as a Function of V
D
(V
S
)
1m
1
1p
50
30
50
10
20
20
40
1n
30
40
100
10
10n
100n
10p
100p
10
0
V
IN
INPUT VOLTAGE Volts
I
S
INPUT LEAKAGE A
V
DD
= 0V
V
SS
= 0V
V
D
= 0V
60
OPERATING RANGE
Figure 4. Input Leakage Current as a Function of V
S
(Power Supplies OFF) During Overvoltage Conditions
1m
1
1p
50
30
50
10
20
20
40
1n
30
40
100
10
10n
100n
10p
100p
10
0
V
IN
INPUT VOLTAGE Volts
I
D
INPUT LEAKAGE A
V
DD
= +15V
V
SS
= 15V
V
D
= 0V
60
OPERATING RANGE
Figure 5. Output Leakage Current as a Function of V
S
(Power Supplies ON) During Overvoltage Conditions
REV. C
6
ADG508F/ADG509F/ADG528F
2000
1000
0
15
5
15
5
0
10
10
500
1750
1500
1250
750
250
V
D
(V
S
) Volts
R
ON
+25 C
V
DD
= +15V
V
SS
= 15V
+125 C
+85 C
Figure 6. On Resistance as a Function of V
D
(V
S
) for
Different Temperatures
1m
1
1p
50
30
50
10
20
20
40
1n
30
40
100
10
10n
100n
10p
100p
10
0
V
IN
INPUT VOLTAGE Volts
I
S
INPUT LEAKAGE A
V
DD
= +15V
V
SS
= 15V
V
D
= 0V
60
OPERATING RANGE
Figure 7. Input Leakage Current as a Function of V
S
(Power Supplies ON) During Overvoltage Conditions
0.3
0.2
0.2
14
6
14
2
2
6
10
0.1
10
0.0
0.1
V
S
, V
D
Volts
LEAKAGE CURRENTS nA
I
S
(OFF)
I
D
(OFF)
I
D
(ON)
V
DD
= +15V
V
SS
= 15V
T
A
= +25 C
Figure 8. Leakage Currents as a Function of V
D
(V
S
)
100
10
0.01
25
45
125
65
55
75
35
1
115
0.1
TEMPERATURE C
LEAKAGE CURRENTS nA
I
S
(OFF)
I
D
(OFF)
I
D
(ON)
V
DD
= +15V
V
SS
= 15V
V
D
= +10V
V
S
= 10V
85
95
105
Figure 9. Leakage Currents as a Function of Temperature
260
240
100
10
15
12
13
11
120
14
t
ON
(EN)
V
IN
= +2V
220
200
180
160
140
t
ns
V
SUPPLY
Volts
t
OFF
(EN)
t
TRANSITION
Figure 10. Switching Time vs. Power Supply
280
240
100
25
125
65
85
45
120
105
t
ON
(EN)
220
200
180
160
140
t
ns
TEMPERATURE C
t
OFF
(EN)
t
TRANSITION
260
V
DD
= +15V
V
SS
= 15V
V
IN
= +5V
Figure 11. Switching Time vs. Temperature
ADG508F/ADG509F/ADG528F
REV. C
7
THEORY OF OPERATION
The ADG508F/ADG509F/ADG528F multiplexers are capable
of withstanding overvoltages from 40 V to +55 V, irrespective
of whether the power supplies are present or not. Each channel
of the multiplexer consists of an n-channel MOSFET, a p-
channel MOSFET and an n-channel MOSFET, connected in
series. When the analog input exceeds the power supplies, one
of the MOSFETs will switch off, limiting the current to sub-
microamp levels, thereby preventing the overvoltage from dam-
aging any circuitry following the multiplexer. Figure 12 illustrates
the channel architecture that enables these multiplexers to with-
stand continuous overvoltages.
When an analog input of V
SS
+ 3 V to V
DD
1.5 V is applied to
the ADG508F/ADG509F/ADG528F, the multiplexer behaves
as a standard multiplexer, with specifications similar to a stan-
dard multiplexer, for example, the on-resistance is 400
maxi-
mum. However, when an overvoltage is applied to the device,
one of the three MOSFETs will turn off.
Figures 12 to 15 show the conditions of the three MOSFETs for
the various overvoltage situations. When the analog input ap-
plied to an ON channel approaches the positive power supply
line, the n-channel MOSFET turns OFF since the voltage on
the analog input exceeds the difference between V
DD
and the
Q1
Q2
Q3
+55V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
OFF
V
DD
V
SS
Figure 12. +55 V Overvoltage Input to the ON Channel
Q1
Q2
Q3
40V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
ON
V
DD
V
SS
p-CHANNEL
MOSFET IS
OFF
Figure 13. 40 V Overvoltage on an OFF Channel with
Multiplexer Power ON
n-channel threshold voltage (V
TN
). When a voltage more nega-
tive than V
SS
is applied to the multiplexer, the p-channel
MOSFET will turn off since the analog input is more negative
than the difference between V
SS
and the p-channel threshold
voltage (V
TP
). Since V
TN
is nominally 1.5 V and V
TP
is typically
3 V, the analog input range to the multiplexer is limited to
12 V to +13.5 V when a
15 V power supply is used.
When the power supplies are present but the channel is off,
again either the p-channel MOSFET or one of the n-channel
MOSFETs will turn off when an overvoltage occurs.
Finally, when the power supplies are off, the gate of each
MOSFET will be at ground. A negative overvoltage switches
on the first n-channel MOSFET but the bias produced by the
overvoltage causes the p-channel MOSFET to remain turned
off. With a positive overvoltage, the first MOSFET in the
series will remain off since the gate to source voltage applied to
this MOSFET is negative.
During fault conditions, the leakage current into and out of the
ADG508F/ADG509F/ADG528F is limited to a few microamps.
This protects the multiplexer and succeeding circuitry from over
stresses as well as protecting the signal sources which drive the
multiplexer. Also, the other channels of the multiplexer will be
undisturbed by the overvoltage and will continue to operate
normally.
Q1
Q2
Q3
+55V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
OFF
Figure 14. +55 V Overvoltage with Power OFF
Q1
Q2
Q3
40V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
ON
p-CHANNEL
MOSFET IS
OFF
Figure 15. 40 V Overvoltage with Power OFF
REV. C
8
ADG508F/ADG509F/ADG528F
Test Circuits
I
DS
S
R
ON
= V
1
/I
DS
V1
V
S
D
Test Circuit 1. On Resistance
V
S
I
S
(OFF)
V
D
S1
S2
S8
V
SS
V
DD
V
SS
V
DD
+0.8V
D
EN
A
Test Circuit 2. I
S
(OFF)
V
D
S1
S2
S8
V
S
V
SS
V
DD
I
D
(OFF)
V
SS
V
DD
+0.8V
D
EN
A
Test Circuit 3. I
D
(OFF)
I
D
(ON)
V
D
S1
S8
V
S
V
SS
V
DD
V
SS
V
DD
+2.4V
D
EN
A
S2
Test Circuit 4. I
D
(ON)
V
D
S1
S2
S8
V
S
V
SS
V
DD
V
SS
V
DD
+0.8V
D
EN
A
Test Circuit 5. Input Leakage Current
(with Overvoltage)
A2
V
S
0V
0V
V
SS
V
DD
D
0V
A
* SIMILAR CONNECTION FOR ADG508F/ADG509F
A1
A0
EN
RS
GND
WR
ADG528F
*
S1
S8
Test Circuit 6. Input Leakage Current
(with Power Supplies OFF)
3V
50%
V
OUT
t
TRANSITION
90%
90%
t
TRANSITION
ADDRESS
DRIVE (V
IN
)
50%
A2
V
OUT
V
SS
V
DD
D
V
S1
* SIMILAR CONNECTION FOR ADG508F/ADG509F
A1
A0
EN
RS
GND
WR
ADG528F
*
S1
S8
S2S7
V
IN
+2.4V
50
V
S8
R
L
1M
C
L
35pF
V
SS
V
DD
Test Circuit 7. Switching Time of Multiplexer, t
TRANSITION
ADG508F/ADG509F/ADG528F
REV. C
9
A2
V
OUT
V
SS
V
DD
D
V
S
* SIMILAR CONNECTION FOR ADG508F/ADG509F
A1
A0
EN
RS
GND
WR
ADG528F
*
S1
S8
S2S7
V
IN
+2.4V
50
R
L
1k
C
L
35pF
V
SS
V
DD
ADDRESS
DRIVE (V
IN
)
3V
V
OUT
t
OPEN
80%
80%
Test Circuit 8. Break-Before-Make Delay, t
OPEN
3V
50%
OUTPUT
0.9V
O
50%
t
ON
(EN)
0.9V
O
0V
V
O
0V
t
OFF
(EN)
ENABLE
DRIVE (V
IN
)
A2
V
OUT
V
SS
V
DD
D
V
S
* SIMILAR CONNECTION FOR ADG508F/ADG509F
A1
A0
RS
GND
WR
ADG528F
*
S1
S2S8
V
IN
50
R
L
1k
C
L
35pF
V
SS
V
DD
+2.4V
EN
Test Circuit 9. Enable Delay, t
ON
(EN), t
OFF
(EN)
3V
OUTPUT
WR
0.2V
O
50%
t
ON
(
WR
)
0V
V
O
0V
A2
V
OUT
V
SS
V
DD
D
V
S
A1
A0
EN
RS
GND
ADG528F
S1
S2S8
+2.4V
R
L
1k
C
L
35pF
V
SS
V
DD
WR
V
WR
V
RS
Test Circuit 10. Write Turn-On Time, t
ON
(WR)
REV. C
10
ADG508F/ADG509F/ADG528F
3V
50%
RS
SWITCH
OUTPUT
0.8V
O
50%
t
RS
t
OFF
(
RS
)
0V
0V
V
O
A2
V
OUT
V
SS
V
DD
D
V
S
A1
A0
EN
RS
GND
WR
ADG528F
S1
S2S8
V
IN
+2.4V
R
L
1k
C
L
35pF
V
SS
V
DD
Test Circuit 11. Reset Turn-Off Time, t
OFF
(RS)
V
OUT
3V
V
OUT
LOGIC
INPUT (V
IN
)
Q
INJ
= C
L
x V
OUT
0V
A2
V
OUT
V
SS
V
DD
D
* SIMILAR CONNECTION FOR ADG508F/ADG509F
A1
A0
EN
RS
GND
WR
ADG528F
*
V
IN
+2.4V
C
L
1nF
V
SS
V
DD
S
R
S
V
S
Test Circuit 12. Charge Injection
A2
V
OUT
V
SS
V
DD
D
* SIMILAR CONNECTION FOR ADG508F/ADG509F
A1
A0
EN
RS
GND
WR
ADG528F
*
+2.4V
R
L
1k
V
SS
V
DD
S1
V
IN
S8
Test Circuit 13. OFF Isolation
ADG508F/ADG509F/ADG528F
REV. C
11
16-Lead Plastic (N-16)
16
1
8
9
0.840 (21.34)
0.745 (18.92)
0.280 (7.11)
0.240 (6.10)
PIN 1
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.160 (4.06)
0.115 (2.93)
0.325 (8.26)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
16-Lead SOIC (R-16N)
(Narrow Body)
16
9
8
1
0.3937 (10.00)
0.3859 (9.80)
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0688 (1.75)
0.0532 (1.35)
0.0500
(1.27)
BSC
0.0099 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
0
0.0196 (0.50)
0.0099 (0.25)
x 45
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Cerdip (Q-16)
16
1
8
9
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13) MIN
0.080 (2.03) MAX
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.200 (5.08)
MAX
0.840 (21.34) MAX
0.150
(3.81)
MIN
0.070 (1.78)
0.030 (0.76)
0.200 (5.08)
0.125 (3.18)
0.100
(2.54)
BSC
0.060 (1.52)
0.015 (0.38)
15
0
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
16-Lead SOIC (R-16W)
(Wide Body)
16
9
8
1
0.4133 (10.50)
0.3977 (10.00)
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC
0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
8
0
0.0291 (0.74)
0.0098 (0.25)
x 45
REV. C
12
ADG508F/ADG509F/ADG528F
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C1979c08/98
PRINTED IN U.S.A.
18-Lead Plastic (N-18)
18
1
9
10
0.925 (23.49)
0.845 (21.47)
0.280 (7.11)
0.240 (6.10)
PIN 1
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.160 (4.06)
0.115 (2.93)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
18-Lead Cerdip (Q-18)
18
1
9
10
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13) MIN
0.098 (2.49) MAX
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.200 (5.08)
MAX
0.960 (24.38) MAX
0.150
(3.81)
MIN
0.070 (1.78)
0.030 (0.76)
0.200 (5.08)
0.125 (3.18)
0.100
(2.54)
BSC
0.060 (1.52)
0.015 (0.38)
15
0
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
20-Lead PLCC (P-20A)
3
PIN 1
IDENTIFIER
4
19
18
8
9
14
13
TOP VIEW
(PINS DOWN)
0.395 (10.02)
0.385 (9.78)
SQ
0.356 (9.04)
0.350 (8.89)
SQ
0.048 (1.21)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
0.020
(0.50)
R
0.050
(1.27)
BSC
0.021 (0.53)
0.013 (0.33) 0.330 (8.38)
0.290 (7.37)
0.032 (0.81)
0.026 (0.66)
0.180 (4.57)
0.165 (4.19)
0.040 (1.01)
0.025 (0.64)
0.056 (1.42)
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
0.110 (2.79)
0.085 (2.16)
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