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ADG728/ADG729
a
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
CMOS, Low-Voltage, 2-Wire
Serially-Controlled, Matrix Switches
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2000
FUNCTIONAL BLOCK DIAGRAMS
S1
S8
SDA
D
SCL
ADG728
S1A
DA
S4A
S1B
S4B
DB
ADG729
RESET
INPUT SHIFT
REGISTER
INPUT SHIFT
REGISTER
A0
A1
SDA SCL
A0
A1
I
2
C is a trademark of Philips Corporation.
FEATURES
2-Wire Serial Interface
2.7 V to 5.5 V Single Supply
2.5
On Resistance
0.75 On-Resistance Flatness
100 pA Leakage Currents
Single 8-to-1 Matrix Switch ADG728
Dual 4-to-1 Matrix Switch ADG729
Power-On Reset
Small 16-Lead TSSOP Package
APPLICATIONS
Data Acquisition Systems
Communication Systems
Relay Replacement
Audio and Video Switching
Automatic Test Equipment
GENERAL DESCRIPTION
The ADG728 and ADG729 are CMOS analog matrix switches
with a serially controlled 2-wire interface. The ADG728 is an
8-channel matrix switch, while the ADG729 is a dual 4-channel
matrix switch. On resistance is closely matched between switches
and very flat over the full signal range. These parts can operate
equally well as either multiplexers, demultiplexers or switch
arrays and the input signal range extends to the supplies.
The ADG728 and ADG729 utilize a 2-wire serial interface that
is compatible with the I
2
CTM interface standard. Both have two
external address pins (A0 and A1). This allows the 2 LSBs of
the 7-bit slave address to be set by the user. Four of each of the
devices can be connected to the one bus. The ADG728 also has
a
RESET pin that should be tied high if not in use.
Each channel is controlled by one bit of an 8-bit word. This
means that these devices may be used in a number of different
configurations; all, any, or none of the channels may be on at
any one time.
On power-up of the device, all switches will be in the OFF con-
dition and the internal shift register will contain all zeros.
All channels exhibit break-before-make switching action pre-
venting momentary shorting when switching channels.
The ADG728 and ADG729 are available in 16-lead TSSOP
packages.
PRODUCT HIGHLIGHTS
1. 2-Wire Serial Interface.
2. Single Supply Operation. The ADG728 and ADG729 are
fully specified and guaranteed with 3 V and 5 V supply rails.
3. Low On Resistance 2.5
typical.
4. Any configuration of switches may be on at any one time.
5. Guaranteed Break-Before-Make Switching Action.
6. Small 16-Lead TSSOP Package.
2
REV. 0
ADG728/ADG729SPECIFICATIONS
1
(V
DD
= 5 V 10%, GND = 0 V, unless otherwise noted.)
B Version
40 C
Parameter
25 C
to +85 C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to V
DD
V
On Resistance (R
ON
)
2.5
typ
V
S
= 0 V to V
DD
, I
S
= 10 mA;
4.5
5
max
Test Circuit 1
On-Resistance Match Between
0.4
typ
V
S
= 0 V to V
DD
, I
S
= 10 mA
Channels (
R
ON
)
0.8
max
On-Resistance Flatness (R
FLAT(ON)
)
0.75
typ
V
S
= 0 V to V
DD
, I
S
= 10 mA
1.2
max
LEAKAGE CURRENTS
V
DD
= 5.5 V
Source OFF Leakage I
S
(OFF)
0.01
nA typ
V
D
= 4.5 V/1 V, V
S
= 1 V/4.5 V, Test Circuit 2
0.1
0.3
nA max
Drain OFF Leakage I
D
(OFF)
0.01
nA typ
V
D
= 4.5 V/1 V, V
D
= 1 V/4.5 V, Test Circuit 3
0.1
1
nA max
Channel ON Leakage I
D
, I
S
(ON)
0.01
nA typ
V
D
= V
S
= 4.5 V/1 V, Test Circuit 4
0.1
1
nA max
LOGIC INPUTS (A0, A1)
2
Input High Voltage, V
INH
2.4
V min
Input Low Voltage, V
INL
0.8
V max
Input Current
I
INL
or I
INH
0.005
A typ
0.1
A max
C
IN
, Input Capacitance
6
pF typ
LOGIC INPUTS (SCL, SDA)
2
Input High Voltage, V
INH
0.7 V
DD
V min
V
DD
+ 0.3
V max
Input Low Voltage, V
INL
0.3
V min
0.3 V
DD
V max
I
IN
, Input Leakage Current
0.005
A typ
V
IN
= 0 V to V
DD
1.0
A max
V
HYST
, Input Hysteresis
0.05 V
DD
V min
C
IN
, Input Capacitance
6
pF typ
LOGIC OUTPUT (SDA)
2
V
OL
, Output Low Voltage
0.4
V max
I
SINK
= 3 mA
0.6
V max
I
SINK
= 6 mA
DYNAMIC CHARACTERISTICS
2
t
ON
95
ns typ
R
L
= 300
, C
L
= 35 pF, Test Circuit 5;
140
ns max
V
S1
= 3 V
t
OFF
85
ns typ
V
S1
= 3 V, R
L
= 300
, C
L
= 35 pF;
130
ns max
Test Circuit 5
Break-Before-Make Time Delay, t
D
8
ns typ
R
L
= 300
, C
L
= 35 pF;
1
ns min
V
S1
= V
S2
= 3 V, Test Circuit 5
Charge Injection
3
pC typ
V
S
= 2.5 V, R
S
= 0
, C
L
= 1 nF;
Test Circuit 6
Off Isolation
55
dB typ
R
L
= 50
, C
L
= 5 pF, f = 10 MHz;
75
dB typ
R
L
= 50
, C
L
= 5 pF, f = 1 MHz;
Test Circuit 8
Channel-to-Channel Crosstalk
55
dB typ
R
L
= 50
, C
L
= 5 pF, f = 10 MHz;
75
dB typ
R
L
= 50
, C
L
= 5 pF, f = 1 MHz;
Test Circuit 7
3 dB Bandwidth
ADG728
65
MHz typ
R
L
= 50
, C
L
= 5 pF, Test Circuit 8
ADG729
100
MHz typ
C
S
(OFF)
13
pF typ
C
D
(OFF)
ADG728
85
pF typ
ADG729
42
pF typ
C
D
, C
S
(ON)
ADG728
96
pF typ
ADG729
48
pF typ
POWER REQUIREMENTS
V
DD
= 5.5 V
I
DD
10
A typ
Digital Inputs = 0 V or 5.5 V
20
A max
N
OTES
1
Temperature range is as follows: B Version: 40
C to +85C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
3
REV. 0
ADG728/ADG729
(V
DD
= 3 V 10%, GND = 0 V, unless otherwise noted.)
SPECIFICATIONS
1
B Version
40 C
Parameter
25 C
to +85 C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to V
DD
V
On Resistance (R
ON
)
6
typ
V
S
= 0 V to V
DD
, I
S
= 10 mA;
11
12
max
Test Circuit 1
On-Resistance Match Between
0.4
typ
V
S
= 0 V to V
DD
, I
S
= 10 mA
Channels (
R
ON
)
1.2
max
On-Resistance Flatness (R
FLAT(ON)
)
3.5
typ
V
S
= 0 V to V
DD
, I
S
= 10 mA
LEAKAGE CURRENTS
V
DD
= 3.3 V
Source OFF Leakage I
S
(OFF)
0.01
nA typ
V
S
= 3 V/1 V, V
D
= 1 V/3 V, Test Circuit 2
0.1
0.3
nA max
Drain OFF Leakage I
D
(OFF)
0.01
nA typ
V
D
= 3 V/1 V, V
D
= 1 V/3 V, Test Circuit 3
0.1
1
nA max
Channel ON Leakage I
D
, I
S
(ON)
0.01
nA typ
V
D
= V
S
= 3 V/1 V, Test Circuit 4
0.1
1
nA max
LOGIC INPUTS (A0, A1)
2
Input High Voltage, V
INH
2.0
V min
Input Low Voltage, V
INL
0.4
V max
Input Current
I
INL
or I
INH
0.005
A typ
0.1
A max
C
IN
, Input Capacitance
3
pF typ
LOGIC INPUTS (SCL, SDA)
2
Input High Voltage, V
INH
0.7 V
DD
V min
V
DD
+ 0.3
V max
Input Low Voltage, V
INL
0.3
V min
0.3 V
DD
V max
I
IN
, Input Leakage Current
0.005
A typ
V
IN
= 0 V to V
DD
1.0
A max
V
HYST
, Input Hysteresis
0.05 V
DD
V min
C
IN
, Input Capacitance
3
pF typ
LOGIC OUTPUT (SDA)
2
V
OL
, Output Low Voltage
0.4
V max
I
SINK
= 3 mA
0.6
V max
I
SINK
= 6 mA
DYNAMIC CHARACTERISTICS
2
t
ON
130
ns typ
R
L
= 300
, C
L
= 35 pF, Test Circuit 5;
200
ns max
V
S1
= 2 V
t
OFF
115
ns typ
R
L
= 300
, C
L
= 35 pF;
180
ns max
V
S
= 2 V, Test Circuit 5
Break-Before-Make Time Delay, t
D
8
ns typ
R
L
= 300
, C
L
= 35 pF;
1
ns min
V
S1
= V
S8
= 2 V, Test Circuit 5
Charge Injection
3
pC typ
V
S
= 1.5 V, R
S
= 0
, C
L
= 1 nF;
Test Circuit 6
Off Isolation
55
dB typ
R
L
= 50
, C
L
= 5 pF, f = 10 MHz;
75
dB typ
R
L
= 50
, C
L
= 5 pF, f = 1 MHz;
Test Circuit 8
Crosstalk
55
dB typ
R
L
= 50
, C
L
= 5 pF, f = 10 MHz;
75
dB typ
R
L
= 50
, C
L
= 5 pF, f = 1 MHz;
Test Circuit 7
3 dB Bandwidth
ADG728
65
MHz typ
R
L
= 50
, C
L
= 5 pF, Test Circuit 8
ADG729
100
MHz typ
C
S
(OFF)
13
pF typ
C
D
(OFF)
ADG728
85
pF typ
ADG729
42
pF typ
C
D
, C
S
(ON)
ADG728
96
pF typ
ADG729
48
pF typ
POWER REQUIREMENTS
V
DD
= 3.3 V
I
DD
10
A typ
Digital Inputs = 0 V or 3.3 V
20
A max
NOTES
1
Temperature ranges are as follows: B Versions: 40
C to +85C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
4
REV. 0
ADG728/ADG729
TIMING CHARACTERISTICS
1
Parameter
Limit at T
MIN
, T
MAX
Unit
Conditions/Comments
f
SCL
400
kHz max
SCL Clock Frequency
t
1
2.5
ms min
SCL Cycle Time
t
2
0.6
ms min
t
HIGH
, SCL High Time
t
3
1.3
ms min
t
LOW
, SCL Low Time
t
4
0.6
ms min
t
HD, STA
, Start/Repeated Start Condition Hold Time
t
5
100
ns min
t
SU, DAT
, Data Setup Time
t
6
2
0.9
ms max
t
HD, DAT
, Data Hold Time
0
ms min
t
7
0.6
ms min
t
SU, STA
, Setup Time for Repeated Start
t
8
0.6
ms min
t
SU, STO
, Stop Condition Setup Time
t
9
1.3
ms min
t
BUF
, Bus Free Time Between a STOP Condition and
a Start Condition
t
10
300
ns max
t
R
, Rise Time of Both SCL and SDA when Receiving
20 + 0.1C
b
3
ns min
t
11
250
ns max
t
F
, Fall Time of SDA when Receiving
300
ns max
t
F
, Fall Time of SDA when Transmitting
20 + 0.1C
b
3
ns min
C
b
400
pF max
Capacitive Load for Each Bus Line
t
SP
4
50
ns max
Pulsewidth of Spike Suppressed
NOTES
1
See Figure 1.
2
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH
min of the SCL signal) in order to bridge the undefined region of
the falling edge of SCL.
3
C
b
is the total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 V
DD
and 0.7 V
DD
.
4
Input filtering on both the SCL and SDA inputs suppress noise spikes which are less than 50 ns.
Specifications subject to change without notice.
t
3
t
2
t
1
t
4
t
8
t
6
t
5
t
9
t
7
t
4
t
11
t
10
SDA
SCL
START
CONDITION
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
Figure 1. 2-Wire Serial Interface Timing Diagram
(V
DD
= 2.7 V to 5.5 V. All specifications 40 C to +85 C, unless otherwise noted.)
ADG728/ADG729
5
REV. 0
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADG728BRU
40
C to +85C
Thin Shrink Small Outline Package (TSSOP)
RU-16
ADG729BRU
40
C to +85C
Thin Shrink Small Outline Package (TSSOP)
RU-16
PIN FUNCTION DESCRIPTIONS
ADG728
ADG729
Mnemonic
Function
1
1
SCL
Serial Clock Line. This is used in conjunction with the SDA line to clock data into
the 8-bit input shift register. Clock rates of up to 400 kbit/s can be accommodated
with this 2-wire serial interface.
2
RESET
Active low control input that clears the input register and turns all switches to the
OFF condition.
3
3
SDA
Serial Data Line. This is used in conjunction with the SCL line to clock data into
the 8-bit input shift register during the write cycle and used to read back 1 byte of
data during the read cycle. It is a bidirectional open-drain data line which should be
pulled to the supply with an external pull-up resistor.
4, 5, 6, 7
4, 5, 6, 7
Sxx
Source. May be an input or output.
8
8, 9
Dx
Drain. May be an input or output.
9, 10, 11, 12
10, 11, 12, 13
Sxx
Source. May be an input or output.
13
14
V
DD
Power Supply Input. These parts can be operated from a supply of 2.7 V to 5.5 V.
14
15
GND
Ground Reference.
15
2
A1
Address Input. Sets the second least significant bit of the 7-bit slave address.
16
16
A0
Address Input. Sets the least significant bit of the 7-bit slave address.
ADG729
SCL
S2A
S3A
S4A
S1A
DA
1
2
16
15
5
6
7
12
11
10
3
4
14
13
8
9
TOP VIEW
(Not to Scale)
A1
GND
V
DD
SDA
ADG729
A0
S2B
S3B
S4B
S1B
DB
ADG728
SCL
RESET
S2
S3
S4
S1
D
1
2
16
15
5
6
7
12
11
10
3
4
14
13
8
9
TOP VIEW
(Not to Scale)
A1
S5
S6
S7
GND
V
DD
S8
SDA
ADG728
A0
PIN CONFIGURATIONS
6
REV. 0
ADG728/ADG729
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25
C unless otherwise noted.)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V
Analog, Digital Inputs
2
. . . . . . . . . . 0.3 V to V
DD
+ 0.3 V or
30 mA, Whichever Occurs First
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Continuous Current, Each S . . . . . . . . . . . . . . . . . . . . . 30 mA
Continuous Current D, ADG729 . . . . . . . . . . . . . . . . . 80 mA
Continuous Current D, ADG728 . . . . . . . . . . . . . . . . 120 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . 40
C to +85C
Storage Temperature Range . . . . . . . . . . . . 65
C to +150C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150
C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG728/ADG729 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
TSSOP Package
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . 150.4
C/W
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 27.6
C/W
Lead Temperature, Soldering (10 seconds) . . . . . . . . . . 300
C
IR Reflow, Peak Temperature . . . . . . . . . . . . . . . . . . . . 220
C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
TERMINOLOGY
C
D
, C
S
(ON)
"ON" Switch Capacitance. Measured with refer-
ence to ground.
C
IN
Digital Input Capacitance.
t
ON
Delay time between the 50% and 90% points
of the STOP condition and the switch "ON"
condition.
t
OFF
Delay time between the 50% and 90% points
of the STOP condition and the switch "OFF"
condition.
t
D
"OFF" time measured between the 80% points of
both switches when switching from one switch to
another.
Charge
A measure of the glitch impulse transferred from
Injection
the digital input to the analog output during
switching.
Off Isolation
A measure of unwanted signal coupling through
an "OFF" switch.
Crosstalk
A measure of unwanted signal which is coupled
through from one channel to another as a result
of parasitic capacitance.
Bandwidth
The frequency at which the output is attenuated
by 3 dBs.
On Response The frequency response of the "ON" switch.
Insertion
The loss due to the ON resistance of the switch.
Loss
WARNING!
ESD SENSITIVE DEVICE
V
DD
Most Positive Power Supply Potential.
I
DD
Positive Supply Current.
GND
Ground (0 V) Reference.
S
Source Terminal. May be an input or output.
D
Drain Terminal. May be an input or output.
V
D
(V
S
)
Analog Voltage on Terminals D, S.
R
ON
Ohmic Resistance between D and S.
R
ON
On Resistance Match Between any Two Chan-
nels, i.e., R
ON
max R
ON
min.
R
FLAT(ON)
Flatness is defined as the difference between the
maximum and minimum value of on resistance
as measured over the specified analog signal range.
I
S
(OFF)
Source Leakage Current with the Switch "OFF."
I
D
(OFF)
Drain Leakage Current with the Switch "OFF."
I
D
, I
S
(ON)
Channel Leakage Current with the Switch "ON."
V
INL
Maximum Input Voltage for Logic "0."
V
INH
Minimum Input Voltage for Logic "1."
I
INL
(I
INH
)
Input Current of the Digital Input.
C
S
(OFF)
"OFF" Switch Source Capacitance. Measured
with reference to ground.
C
D
(OFF)
"OFF" Switch Drain Capacitance. Measured
with reference to ground.
T
A
= 25 C
V
SS
= 0V
V
DD
= 4.5V
V
DD
= 5.5V
V
DD
= 3.3V
V
DD
= 2.7V
V
D
OR V
S
DRAIN OR SOURCE VOLTAGE V
ON RESISTANCE
0
0
1
2
3
4
5
6
7
8
1
2
3
4
5
Figure 2. On Resistance as a Function
of V
D
(V
S
) for Single Supply
CURRENT
nA
0.12
0
0.08
0.04
0.00
0.04
0.08
0.12
1
2
3
4
5
V
DD
= 5V
V
SS
= 0V
T
A
= 25 C
I
D
(ON)
I
S
(OFF)
I
D
(OFF)
V
D
(V
S
)
Volts
Figure 5. Leakage Currents as a Func-
tion of V
D
(V
S
)
CURRENT
nA
0.05
15
0.05
0.15
0.20
0.30
0.35
25
TEMPERATURE
C
0.25
0.10
0.00
35
45
55
65
75
85
V
DD
= 3V
V
SS
= 0V
I
D
(OFF)
I
D
(ON)
I
S
(OFF)
Figure 8. Leakage Currents as a Func-
tion of Temperature
Typical Performance CharacteristicsADG728/ADG729
7
REV. 0
V
D
OR V
S
DRAIN OR SOURCE VOLTAGE V
ON RESISTANCE
0
0
1
2
3
4
5
6
7
8
1
2
3
4
5
40 C
+25 C
V
DD
= 5V
V
SS
= 0V
+85 C
Figure 3. On Resistance as a Function
of V
D
(V
S
) for Different Temperatures,
Single Supply
CURRENT
nA
0.12
0
0.08
0.04
0.00
0.04
0.08
0.12
3.0
V
D
(V
S
)
Volts
2.5
2.0
1.5
1.0
0.5
V
DD
= 3V
V
SS
= 0V
T
A
= 25 C
I
D
(ON)
I
D
(OFF)
I
S
(OFF)
Figure 6. Leakage Currents as a Func-
tion of V
D
(V
S
)
CURRENT
A
1
10k
10
1m
FREQUENCY Hz
100
100k
1M
V
DD
= 3V
V
DD
= 5V
T
A
= 25 C
Figure 9. Input Current vs. Switch-
ing Frequency
V
D
OR V
S
DRAIN OR SOURCE VOLTAGE V
ON RESISTANCE
0
0
1
2
3
4
5
6
7
8
3.0
2.5
2.0
1.5
1.0
0.5
+25 C
40 C
+85 C
V
DD
= 3V
V
SS
= 0V
Figure 4. On Resistance as a Function
of V
D
(V
S
) for Different Temperatures,
Single Supply
CURRENT
nA
0.05
15
0.05
0.15
0.20
0.30
0.35
25
TEMPERATURE
C
0.25
0.10
0.00
35
45
55
65
75
85
V
DD
= 5V
V
SS
= 0V
I
D
(ON)
I
D
(OFF)
I
S
(OFF)
Figure 7. Leakage Currents as a
Function of Temperature
VOLTAGE Volts
Q
INJ
pC
40
0
30
20
10
0
10
20
1
2
3
4
5
T
A
= 25 C
V
DD
= 3V
V
SS
= 0V
V
DD
= 5V
V
SS
= 0V
Figure 10. Charge Injection vs. Source
Voltage
8
REV. 0
ADG728/ADG729
TEMPERATURE C
TIME
ns
0
40
40
60
100
120
140
160
20
0
20
40
80
60
80
20
T
ON
,
V
DD
= 3V
T
OFF
,
V
DD
= 3V
T
ON
,
V
DD
= 5V
T
OFF
,
V
DD
= 5V
Figure 11. T
ON
/T
OFF
Times vs.
Temperature
FREQUENCY Hz
0
30k
ATTENUATION
dB
5
100k
1M
10M
100M
10
15
20
V
DD
= 5V
T
A
= 25 C
ADG728
ADG729
Figure 14. On Response vs.
Frequency
FREQUENCY Hz
0
30k
ATTENUATION
dB
20
40
60
80
100
120
100k
1M
10M
100M
V
DD
= 5V
T
A
= 25 C
Figure 12. Off Isolation vs. Frequency
FREQUENCY Hz
0
30k
ATTENUATION
dB
20
40
60
80
100
120
100k
1M
10M
100M
V
DD
= 5V
T
A
= 25 C
Figure 13. Crosstalk vs. Frequency
ADG728/ADG729
9
REV. 0
GENERAL DESCRIPTION
The ADG728 and ADG729 are serially controlled, 8-channel
and dual 4-channel matrix switches respectively. While provid-
ing the normal multiplexing and demultiplexing functions, these
devices also provide the user with more flexibility as to where
their signal may be routed. Each bit of the serial word corre-
sponds to one switch of the device. A Logic 1 in the particular
bit position turns on the switch, while a Logic 0 turns the switch
off. Because each switch is independently controlled by an indi-
vidual bit, this provides the option of having any, all, or none of
the switches ON. This feature may be particularly useful in the
demultiplexing application where the user may wish to direct
one signal from the drain to a number of outputs (sources). Care
must be taken, however, in the multiplexing situation where a
number of inputs may be shorted together (separated only by
the small on resistance of the switch).
When changing the switch conditions, a new 8-bit word is writ-
ten to the input shift register. Some of the bits may be the same
as the previous write cycle, as the user may not wish to change
the state of some switches. In order to minimize glitches on the
output of these switches, the part cleverly compares the state of
switches from the previous write cycle. If the switch is already
in the ON condition, and is required to stay ON, there will be
minimal glitches on the output of the switch.
POWER-ON RESET
On power-up of the device, all switches will be in the OFF con-
dition and the internal shift register is filled with zeros and will
remain so until a valid write takes place.
SERIAL INTERFACE
2-Wire Serial Bus
The ADG728/ADG729 are controlled via an I
2
C compatible
serial bus. These parts are connected to this bus as a slave device
(no clock is generated by the multiplexer).
The ADG728/ADG729 have different 7-bit slave addresses.
The five MSBs of the ADG728 are 10011, while the MSBs of
the ADG729 are 10001 and the two LSBs are determined by
the state of the A0 and A1 pins.
The 2-wire serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition which is when a high-to-low transition on the SDA
line occurs while SCL is high. The following byte is the
address byte, which consists of the 7-bit slave address fol-
lowed by a R/
W bit (this bit determines whether data will be
read from or written to the slave device).
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the Acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from its
serial register. If the R/W bit is high, the master will read
from the slave device. However, if the R/
W bit is low, the
master will write to the slave device.
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of
SCL.
3. When all data bits have been read or written, a STOP condition
is established by the master. A STOP condition is defined as
a low-to-high transition on the SDA line while SCL is high.
In Write mode, the master will pull the SDA line high during
the 10th clock pulse to establish a STOP condition. In Read
mode, the master will issue a No Acknowledge for the ninth
clock pulse (i.e., the SDA line remains high). The master will
then bring the SDA line low before the tenth clock pulse and
then high during the tenth clock pulse to establish a STOP
condition.
See Figures 18 to 21 below for a graphical explanation of the
serial interface.
A repeated write function gives the user flexibility to update the
matrix switch a number of times after addressing the part only
once. During the write cycle, each data byte will update the con-
figuration of the switches. For example, after the matrix switch
has acknowledged its address byte, and receives one data byte,
the switches will update after the data byte, if another data byte
is written to the matrix switch while it is still the addressed slave
device, this data byte will also cause an switch configuration
update. Repeat read of the matrix switch is also allowed.
INPUT SHIFT REGISTER
The input shift register is eight bits wide. Figure 15 illustrates
the contents of the input shift register. Data is loaded into the
device as an 8-bit word under the control of a serial clock input,
SCL. The timing diagram for this operation is shown in Figure 1.
The 8-bit word consists of eight data bits each controlling one
switch. MSB (Bit 7) is loaded first.
S8
S7
S6
S5
S4
S3
S2
S1
DB0 (LSB)
DB7 (MSB)
DATA BITS
Figure 15. ADG728/ADG729 Input Shift Register Contents
10
REV. 0
ADG728/ADG729
WRITE OPERATION
When writing to the ADG728/ADG729, the user must begin
with an address byte and R/
W bit, after which the switch will
acknowledge that it is prepared to receive data by pulling SDA
low. This address byte is followed by the 8-bit word. The write
operations for each matrix switch are shown in the figures below.
SCL
SDA
S8
S7
S6
S5
S4
S3
S2
S1
0
0
1
1
A0
R/
W
STOP
COND
BY
MASTER
ACK
BY
ADG728
START
COND
BY
MASTER
ADDRESS BYTE
DATA BYTE
ACK
BY
ADG728
A1
1
Figure 16. ADG728 Write Sequence
SCL
SDA
S8
S7
S6
S5
S4
S3
S2
S1
0
0
1
A0
R/
W
STOP
COND
BY
MASTER
ACK
BY
ADG729
START
COND
BY
MASTER
ADDRESS BYTE
DATA BYTE
ACK
BY
ADG729
A1
1
0
Figure 17. ADG729 Write Sequence
READ OPERATION
When reading data back from the ADG728/ADG729, the user
must begin with an address byte and R/
W bit, after which the
matrix switch will acknowledge that it is prepared to transmit data
by pulling SDA low. The readback operation is a single byte
that consists of the eight data bits in the input register. The read
operations for each part are shown in Figures 18 and 19.
SCL
SDA
S8
S7
S6
S5
S4
S3
S2
S1
0
0
1
A0
R/
W
STOP
COND
BY
MASTER
ACK
BY
ADG728
START
COND
BY
MASTER
ADDRESS BYTE
DATA BYTE
NO ACK
BY
MASTER
A1
1
1
Figure 18. ADG728 Readback Sequence
SCL
SDA
S8
S7
S6
S5
S4
S3
S2
S1
0
0
1
A0
R/
W
STOP
COND
BY
MASTER
ACK
BY
ADG729
START
COND
BY
MASTER
ADDRESS BYTE
DATA BYTE
NO ACK
BY
MASTER
A1
1
0
Figure 19. ADG729 Readback Sequence
ADG728/ADG729
11
REV. 0
TEST CIRCUITS
I
DS
S
V
S
D
V
1
R
ON
= V
1
/I
DS
Test Circuit 1. On Resistance
I
S
(OFF)
S1
S2
S8
D
A
GND
V
DD
V
DD
V
D
V
S
Test Circuit 2. I
D
(OFF)
S1
S2
S8
D
GND
V
DD
V
DD
V
S
A
I
D
(OFF)
V
D
Test Circuit 3. I
S
(OFF)
S1
S8
D
GND
V
DD
V
DD
V
S
A
I
D
(ON)
V
D
Test Circuit 4. I
D
(ON)
GND
V
DD
V
DD
50%
t
OFF
90%
90%
50%
V
S1
80%
80%
V
S1
= V
S8
V
OUT
V
OUT
t
ON
t
OPEN
SCL
V
OUT
D
V
S1
ADG728*
S1
S8
S2 THRU S7
R
L
300
C
L
35pF
V
S8
* SIMILAR CONNECTION FOR ADG729
Test Circuit 5. Switching Times and Break-Before-Make Times
MULTIPLE DEVICES ON ONE BUS
Figure 20 shows four ADG728s devices on the same serial bus.
Each has a different slave address since the state of their A0 and
A1 pins is different. This allows each Matrix Switch to be writ-
ten to or read from independently. Because the ADG729 has a
different address to the ADG728, it would be possible for four
of each of these devices to be connected to the same bus.
ADG728
A1
A0
SDA
SCL
ADG728
A1
A0
SDA
SCL
ADG728
A1
A0
SDA
SCL
ADG728
A1
A0
SDA
SCL
SCL
SDA
+5V
V
DD
MASTER
R
P
R
P
V
DD
V
DD
Figure 20. Multiple ADG728s on the Same Bus
ADG728/ADG729
12
REV. 0
PRIN
TED IN U
.S.A.
C38332.54/0
0 (rev
. 0) 0
1
0
0
2
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead TSSOP
(RU-16)
16
9
8
1
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
0.201 (5.10)
0.193 (4.90)
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
0.0433 (1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8
0
SDA
V
DD
ADG728*
1nF
INPUT LOGIC
SWITCH OFF
SWITCH ON
V
OUT
C
L
V
S
R
S
V
OUT
Q
INJ
= C
L
x V
OUT
D
* SIMILAR CONNECTION FOR ADG729
S
V
DD
SCL
GND
Test Circuit 6. Charge Injection
GND
ADG728*
50
S1
S2
S8
* SIMILAR CONNECTION FOR ADG729
CHANNEL-TO-CHANNEL CROSSTALK = 20LOG
10
(V
OUT
/V
S
)
V
OUT
V
DD
R
L
V
DD
50
V
S
D
Test Circuit 7. Channel-to-Channel Crosstalk
GND
ADG728*
50
S1
S8
V
OUT
V
DD
R
L
V
DD
V
S
D
*SIMILAR CONNECTION FOR ADG729
OFF ISOLATION = 20LOG
10
(V
OUT
/V
S
)
V
OUT
WITHOUT SWITCH
INSERTION LOSS = 20LOG
10
V
OUT
WITH SWITCH
S1 IS SWITCHED OFF FOR OFF ISOLATION MEASURE-
MENTS AND ON FOR BANDWIDTH MEASUREMENTS
Test Circuit 8. Off Isolation and Bandwidth
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