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REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
ADG733/ADG734
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2001
CMOS, 2.5 Low Voltage,
Triple/Quad SPDT Switches
FEATURES
1.8 V to 5.5 V Single Supply
3 V Dual Supply
2.5 On Resistance
0.5 On Resistance Flatness
100 pA Leakage Currents
19 ns Switching Times
Triple SPDT: ADG733
Quad SPDT: ADG734
Small TSSOP and QSOP Packages
Low Power Consumption
TTL/CMOS-Compatible Inputs
APPLICATIONS
Data Acquisition Systems
Communication Systems
Relay Replacement
Audio and Video Switching
Battery-Powered Systems
GENERAL DESCRIPTION
The ADG733 and ADG734 are low voltage, CMOS devices
comprising three independently selectable SPDT (single pole,
double throw) switches and four independently selectable SPDT
switches respectively.
Low power consumption and operating supply range of 1.8 V to
5.5 V and dual
3 V make the ADG733 and ADG734 ideal for
battery powered, portable instruments. All channels exhibit
break-before-make switching action preventing momentary
shorting when switching channels. An
EN input on the ADG733
is used to enable or disable the device. When disabled, all chan-
nels are switched OFF.
These 21 multiplexers/SPDT switches are designed on an
enhanced submicron process that provides low power dissipation
yet gives high switching speed, very low on resistance, high signal
bandwidths and low leakage currents. On resistance is in the region
of a few ohms, is closely matched between switches and very flat
over the full signal range. These parts can operate equally well
in either direction and have an input signal range which extends
to the supplies.
The ADG733 is available in small TSSOP and QSOP packages,
while the ADG734 is available in a small TSSOP package.
PRODUCT HIGHLIGHTS
1. Single/Dual Supply Operation. The ADG733 and ADG734 are
fully specified and guaranteed with 3 V and 5 V single supply
rails and
3 V dual supply rails.
2. Low On Resistance (2.5
typical).
3. Low Power Consumption (<0.01
W).
4. Guaranteed Break-Before-Make Switching Action.
FUNCTIONAL BLOCK DIAGRAMS
S1B
D1
S1A
A0
S2A
D2
S2B
S3B
D3
S3A
A1
ADG733
SWITCHES SHOWN FOR A "1" INPUT LOGIC
S1A
D1
S1B
IN1
IN2
S2B
D2
S2A
S3A
D3
S3B
IN3
IN4
S4B
D2
S4A
ADG734
EN
A2
LOGIC
REV. 0
2
ADG733/ADG734SPECIFICATIONS
1
B Version
40 C
Parameter
25 C
to +85 C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to V
DD
V
On Resistance (R
ON
)
2.5
typ
V
S
= 0 V to V
DD
, I
DS
= 10 mA;
4.5
5.0
max
Test Circuit 1
On-Resistance Match between
0.1
typ
V
S
= 0 V to V
DD
, I
DS
= 10 mA
Channels (
R
ON
)
0.4
max
On-Resistance Flatness (R
FLAT(ON)
)
0.5
typ
V
S
= 0 V to V
DD
, I
DS
= 10 mA
1.2
max
LEAKAGE CURRENTS
V
DD
= 5.5 V
Source OFF Leakage I
S
(OFF)
0.01
nA typ
V
D
= 4.5 V/1 V, V
S
= 1 V/4.5 V;
0.1
0.3
nA max
Test Circuit 2
Channel ON Leakage I
D
, I
S
(ON)
0.01
nA typ
V
D
= V
S
= 1 V, or 4.5 V;
0.1
0.5
nA max
Test Circuit 3
DIGITAL INPUTS
Input High Voltage, V
INH
2.4
V min
Input Low Voltage, V
INL
0.8
V max
Input Current
I
INL
or I
INH
0.005
A typ
V
IN
= V
INL
or V
INH
0.1
A max
C
IN
, Digital Input Capacitance
4
pF typ
DYNAMIC CHARACTERISTICS
2
t
ON
19
ns typ
R
L
= 300
, C
L
= 35 pF;
34
ns max
V
S
= 3 V, Test Circuit 4
t
OFF
7
ns typ
R
L
= 300
, C
L
= 35 pF;
12
ns max
V
S
= 3 V, Test Circuit 4
ADG733
t
ON
(
EN)
20
ns typ
R
L
= 300
, C
L
= 35 pF;
40
ns max
V
S
= 3 V, Test Circuit 5
t
OFF
(
EN)
7
ns typ
R
L
= 300
, C
L
= 35 pF;
12
ns max
V
S
= 3 V, Test Circuit 5
Break-Before-Make Time Delay, t
D
13
ns typ
R
L
= 300
, C
L
= 35 pF;
1
ns min
V
S
= 3 V, Test Circuit 6
Charge Injection
3
pC typ
V
S
= 2 V, R
S
= 0
, C
L
= 1 nF;
Test Circuit 7
Off Isolation
62
dB typ
R
L
= 50
, C
L
= 5 pF, f = 10 MHz;
82
dB typ
R
L
= 50
, C
L
= 5 pF, f = 1 MHz;
Test Circuit 8
Channel-to-Channel Crosstalk
62
dB typ
R
L
= 50
, C
L
= 5 pF, f = 10 MHz;
82
dB typ
R
L
= 50
, C
L
= 5 pF, f = 1 MHz;
Test Circuit 9
3 dB Bandwidth
200
MHz typ
R
L
= 50
, C
L
= 5 pF, Test Circuit 8
C
S
(OFF)
11
pF typ
C
D
, C
S
(ON)
34
pF typ
POWER REQUIREMENTS
V
DD
= 5.5 V
I
DD
0.001
A typ
Digital Inputs = 0 V or 5.5 V
1.0
A max
NOTES
1
Temperature range is as follows: B Version: 40
C to +85C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
(V
DD
= 5 V
10%, V
SS
= 0 V, GND = 0 V, unless otherwise noted.)
REV. 0
3
ADG733/ADG734
B Version
40 C
Parameter
25 C
to +85 C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to V
DD
V
On Resistance (R
ON
)
6
typ
V
S
= 0 V to V
DD
, I
DS
= 10 mA;
11
12
max
Test Circuit 1
On-Resistance Match between
0.1
typ
V
S
= 0 V to V
DD
, I
DS
= 10 mA
Channels (
R
ON
)
0.4
max
On-Resistance Flatness (R
FLAT(ON)
)
3
typ
V
S
= 0 V to V
DD
, I
DS
= 10 mA
LEAKAGE CURRENTS
V
DD
= 3.3 V
Source OFF Leakage I
S
(OFF)
0.01
nA typ
V
S
= 3 V/1 V, V
D
= 1 V/3 V;
0.1
0.3
nA max
Test Circuit 2
Channel ON Leakage I
D
, I
S
(ON)
0.01
nA typ
V
S
= V
D
= 1 V or 3 V;
0.1
0.5
nA max
Test Circuit 3
DIGITAL INPUTS
Input High Voltage, V
INH
2.0
V min
Input Low Voltage, V
INL
0.4
V max
Input Current
I
INL
or I
INH
0.005
A typ
V
IN
= V
INL
or V
INH
0.1
A max
C
IN
, Digital Input Capacitance
4
pF typ
DYNAMIC CHARACTERISTICS
2
t
ON
28
ns typ
R
L
= 300
, C
L
= 35 pF;
55
ns max
V
S
= 2 V, Test Circuit 4
t
OFF
9
ns typ
R
L
= 300
, C
L
= 35 pF;
16
ns max
V
S
= 2 V, Test Circuit 4
ADG733
t
ON
(
EN)
29
ns typ
R
L
= 300
, C
L
= 35 pF;
60
ns max
V
S
= 2 V, Test Circuit 5
t
OFF
(
EN)
9
ns typ
R
L
= 300
, C
L
= 35 pF;
16
ns max
V
S
= 2 V, Test Circuit 5
Break-Before-Make Time Delay, t
D
22
ns typ
R
L
= 300
, C
L
= 35 pF;
1
ns min
V
S
= 2 V, Test Circuit 6
Charge Injection
3
pC typ
V
S
= 1 V, R
S
= 0
, C
L
= 1 nF;
Test Circuit 7
Off Isolation
62
dB typ
R
L
= 50
, C
L
= 5 pF, f = 10 MHz;
82
dB typ
R
L
= 50
, C
L
= 5 pF, f = 1 MHz;
Test Circuit 8
Channel-to-Channel Crosstalk
62
dB typ
R
L
= 50
, C
L
= 5 pF, f = 10 MHz;
82
dB typ
R
L
= 50
, C
L
= 5 pF, f = 1 MHz;
Test Circuit 9
3 dB Bandwidth
200
MHz typ
R
L
= 50
, C
L
= 5 pF, Test Circuit 8
C
S
(OFF)
11
pF typ
C
D
, C
S
(ON)
34
pF typ
POWER REQUIREMENTS
V
DD
= 3.3 V
I
DD
0.001
A typ
Digital Inputs = 0 V or 3.3 V
1.0
A max
NOTES
1
Temperature ranges are as follows: B Version: 40
C to +85C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
(V
DD
= 3 V 10%, V
SS
= 0 V, GND = 0 V, unless otherwise noted.)
SPECIFICATIONS
1
REV. 0
4
ADG733/ADG734SPECIFICATIONS
1
DUAL SUPPLY
B Version
40 C
Parameter
25 C
to +85 C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
V
SS
to V
DD
V
On Resistance (R
ON
)
2.5
typ
V
S
= V
SS
to V
DD
, I
DS
= 10 mA;
4.5
5.0
max
Test Circuit 1
On-Resistance Match between
0.1
typ
V
S
= V
SS
to V
DD
, I
DS
= 10 mA
Channels (
R
ON
)
0.4
max
On-Resistance Flatness (R
FLAT(ON)
)
0.5
typ
V
S
= V
SS
to V
DD
, I
DS
= 10 mA
1.2
max
LEAKAGE CURRENTS
V
DD
= +3.3 V, V
SS
= 3.3 V
Source OFF Leakage I
S
(OFF)
0.01
nA typ
V
S
= +2.25 V/1.25 V, V
D
= 1.25 V/+2.25 V;
0.1
0.3
nA max
Test Circuit 2
Channel ON Leakage I
D
, I
S
(ON)
0.01
nA typ
V
S
= V
D
= +2.25 V/1.25 V, Test Circuit 3
0.1
0.5
nA max
DIGITAL INPUTS
Input High Voltage, V
INH
2.0
V min
Input Low Voltage, V
INL
0.4
V max
Input Current
I
INL
or I
INH
0.005
A typ
V
IN
= V
INL
or V
INH
0.1
A max
C
IN
, Digital Input Capacitance
4
pF typ
DYNAMIC CHARACTERISTICS
2
t
ON
21
ns typ
R
L
= 300
, C
L
= 35 pF;
35
ns max
V
S
= 1.5 V, Test Circuit 4
t
OFF
10
ns typ
R
L
= 300
, C
L
= 35 pF;
16
ns max
V
S
= 1.5 V, Test Circuit 4
ADG733
t
ON
(
EN)
21
ns typ
R
L
= 300
, C
L
= 35 pF;
40
ns max
V
S
= 1.5 V, Test Circuit 5
t
OFF
(
EN)
10
ns typ
R
L
= 300
, C
L
= 35 pF;
16
ns max
V
S
= 1.5 V, Test Circuit 5
Break-Before-Make Time Delay, t
D
13
ns typ
R
L
= 300
, C
L
= 35 pF;
1
ns min
V
S
= 1.5 V, Test Circuit 6
Charge Injection
5
pC typ
V
S
= 0 V, R
S
= 0
, C
L
= 1 nF;
Test Circuit 7
Off Isolation
62
dB typ
R
L
= 50
, C
L
= 5 pF, f = 10 MHz;
82
dB typ
R
L
= 50
, C
L
= 5 pF, f = 1 MHz;
Test Circuit 8
Channel-to-Channel Crosstalk
62
dB typ
R
L
= 50
, C
L
= 5 pF, f = 10 MHz;
82
dB typ
R
L
= 50
, C
L
= 5 pF, f = 1 MHz;
Test Circuit 9
3 dB Bandwidth
200
MHz typ
R
L
= 50
, C
L
= 5 pF, Test Circuit 8
C
S
(OFF)
11
pF typ
C
D
, C
S
(ON)
34
pF typ
POWER REQUIREMENTS
V
DD
= 3.3 V
I
DD
0.001
A typ
Digital Inputs = 0 V or 3.3 V
1.0
A max
I
SS
0.001
A typ
V
SS
= 3.3 V
1.0
A max
Digital Inputs = 0 V or 3.3 V
NOTES
1
Temperature range is as follows: B Version: 40
C to +85C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
(V
DD
= +3 V 10%, V
SS
= 3 V 10%, GND = 0 V, unless otherwise noted.)
REV. 0
ADG733/ADG734
5
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25
C unless otherwise noted)
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to 3.5 V
Analog Inputs
2
. . . . . . . . . . . . . . V
SS
0.3 V to V
DD
+ 0.3 V or
30 mA, Whichever Occurs First
Digital Inputs
2
. . . . . . . . . . . . . . . . . 0.3 V to V
DD
+ 0.3 V or
30 mA, Whichever Occurs First
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . . 40
C to +85C
Storage Temperature Range . . . . . . . . . . . . 65
C to +150C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG733/ADG734 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150
C
16-Lead TSSOP,
JA
Thermal Impedance . . . . . . . 150.4
C/W
20-Lead TSSOP,
JA
Thermal Impedance . . . . . . . . 143
C/W
16-Lead QSOP,
JA
Thermal Impedance . . . . . . . 149.97
C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300
C
IR Reflow, Peak Temperature . . . . . . . . . . . . . . . . . . . . 220
C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADG733BRU
40
C to +85C
Thin Shrink Small Outline Package (TSSOP)
RU-16
ADG733BRQ
40
C to +85C
Quarter Size Outline Package (QSOP)
RQ-16
ADG734BRU
40
C to +85C
Thin Shrink Small Outline Package (TSSOP)
RU-20
PIN CONFIGURATIONS
TSSOP/QSOP
TSSOP
10
9
13
12
11
15
14
16
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
ADG733
S2B
S1B
D1
D2
V
DD
S2A
S3B
D3
A1
A0
S1A
S3A
EN
V
SS
GND
A2
14
13
12
11
17
16
15
19
18
20
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
ADG734
NC = NO CONNECT
IN1
S4B
D4
S4A
IN4
S1A
D1
S1B
S3B
NC
V
DD
V
SS
GND
S2B
D2
S2A
IN2
IN3
S3A
D3
REV. 0
ADG733/ADG734
6
Table I. ADG733 Truth Table
A2
A1
A0
EN
ON Switch
X
X
X
1
None
0
0
0
0
D1-S1A, D2-S2A, D3-S3A
0
0
1
0
D1-S1B, D2-S2A, D3-S3A
0
1
0
0
D1-S1A, D2-S2B, D3-S3A
0
1
1
0
D1-S1B, D2-S2B, D3-S3A
1
0
0
0
D1-S1A, D2-S2A, D3-S3B
1
0
1
0
D1-S1B, D2-S2A, D3-S3B
1
1
0
0
D1-S1A, D2-S2B, D3-S3B
1
1
1
0
D1-S1B, D2-S2B, D3-S3B
X = Don't Care.
Table II. ADG734 Truth Table
Logic
Switch A
Switch B
0
OFF
ON
1
ON
OFF
V
DD
Most Positive Power Supply Potential.
V
SS
Most Negative Power Supply in a Dual Supply
Application. In single supply applications, this
should be tied to ground close to the device.
I
DD
Positive Supply Current.
I
SS
Negative Supply Current.
GND
Ground (0 V) Reference.
S
Source Terminal. May be an input or output.
D
Drain Terminal. May be an input or output.
IN
Logic Control Input.
V
D
(V
S
)
Analog Voltage on Terminals D, S
R
ON
Ohmic Resistance between D and S.
R
ON
On Resistance Match between Any Two
Channels, i.e., R
ON
max R
ON
min
R
FLAT(ON)
Flatness is defined as the difference between the
maximum and minimum value of on-resistance
as measured over the specified analog signal range.
I
S
(OFF)
Source Leakage Current with the Switch
"OFF."
I
D
, I
S
(ON)
Channel Leakage Current with the Switch
"ON."
V
INL
Maximum Input Voltage for Logic "0."
V
INH
Minimum Input Voltage for Logic "1."
I
INL
(I
INH
)
Input Current of the Digital Input.
C
S
(OFF)
"OFF" Switch Source Capacitance.
Measured with reference to ground.
C
D
, C
S
(ON)
"ON" Switch Capacitance. Measured
with reference to ground.
C
IN
Digital Input Capacitance.
t
ON
Delay time measured between the 50% and
90% points of the digital inputs and the
switch "ON" condition.
t
OFF
Delay time measured between the 50% and
90% points of the digital input and the switch
"OFF" condition.
t
ON
(
EN)
Delay time between the 50% and 90% points
of the
EN digital input and the switch "ON"
condition.
t
OFF
(
EN)
Delay time between the 50% and 90% points
of the
EN digital input and the switch "OFF"
condition.
t
OPEN
"OFF" time measured between the 80%
points of both switches when switching from
one address state to another.
Charge
A measure of the glitch impulse transferred
Injection
from the digital input to the analog output
during switching.
Off Isolation
A measure of unwanted signal coupling
through an "OFF" switch.
Crosstalk
A measure of unwanted signal that is coupled
through from one channel to
another as a result of parasitic capacitance.
Bandwidth
The frequency at which the output is
attenuated by 3 dBs.
On Response
The Frequency Response of the "ON" Switch.
Insertion Loss The loss due to the ON resistance of the switch.
TERMINOLOGY
REV. 0
7
Typical Performance CharacteristicsADG733/ADG734
V
D
, V
S
, DRAIN OR SOURCE VOLTAGE V
8
0
1
2
3
4
7
6
5
4
3
2
1
0
ON RESISTANCE
T
A
= 25 C
V
SS
= 0V
V
DD
= 4.5V
V
DD
= 5.5V
V
DD
= 3.3V
V
DD
= 2.7V
5
TPC 1. On Resistance as a Function of
V
D
(V
S
) for Single Supply
V
D
OR V
S
DRAIN OR SOURCE VOLTAGE V
0
0.5
7
6
5
4
3
2
1
0
ON RESISTANCE
1.0
1.5
2.0
2.5
3.0
8
+25 C
40 C
+85 C
V
DD
= 3V
V
SS
= 0V
TPC 4. On Resistance as a Function of
V
D
(V
S
) for Different Temperatures,
Single Supply
V
S
(V
D
) V
0.10
0
0.5
CURRENT
nA
V
DD
= 3V
V
SS
= GND
T
A
= 25 C
I
S
, I
D
(ON)
I
S
(OFF)
0.08
0.06
0.04
0.02
0
0.02
0.04
0.06
0.08
0.10
1.0
1.5
2.0
2.5
3.0
TPC 7. Leakage Currents as a
Function of V
D
(V
S
)
V
D
, OR V
S
/DRAIN OR SOURCE VOLTAGE V
8
3
2
1
0
2
7
6
5
4
3
2
1
0
ON RESISTANCE
T
A
= 25 C
V
DD
= +2.7V
V
SS
= 2.7V
3
V
DD
= +3.0V
V
SS
= 3.0V
V
DD
= +3.3V
V
SS
= 3.3V
1
TPC 2. On Resistance as a Function of
V
D
(V
S
) for Dual Supply
V
D
, OR V
S
DRAIN OR SOURCE VOLTAGE V
8
3
2
1
0
2
7
6
5
4
3
2
1
0
ON RESISTANCE
V
DD
= +3.0V
V
SS
= 3.0V
3
40 C
1
+85 C
+25 C
TPC 5. On Resistance as a Function of
V
D
(V
S
) for Different Temperatures,
Dual Supply
V
S
(V
D
) V
0.15
3
2
CURRENT
nA
V
DD
= +3V
V
SS
= 3V
T
A
= 25 C
I
S
, I
D
(ON)
I
S
(OFF)
0.10
0.05
0
0.05
0.10
0.15
1
0
1
2
3
TPC 8. Leakage Currents as a
Function of V
D
(V
S
)
V
D
, OR V
S
DRAIN OR SOURCE VOLTAGE V
8
0
2
7
6
5
4
3
2
1
0
ON RESISTANCE
V
DD
= 5V
V
SS
= 0V
3
40 C
1
+85 C
+25 C
4
5
TPC 3. On Resistance as a Function of
V
D
(V
S
) for Different Temperatures,
Single Supply
V
S
(V
D
) V
0.1
0
1
2
3
5
CURRENT
nA
V
DD
= 5V
V
SS
= GND
T
A
= 25 C
4
I
S
, I
D
(ON)
I
S
(OFF)
0.05
0
0.05
0.1
0.15
TPC 6. Leakage Currents as a
Function of V
D
(V
S
)
TEMPERATURE C
0.25
5
CURRENT
nA
V
DD
= +3V
V
SS
= 3V
V
D
= +2.25V/1.25V
V
S
= 1.25V/+2.25V
V
DD
= 5V
V
SS
= GND
V
D
= 4.5V/1.0V
V
S
= 1.0V/4.5V
I
S
, I
D
(ON)
I
S
(OFF)
0.20
0.15
0.10
0.05
0
0.05
20
35
50
65
80
0.10
TPC 9. Leakage Currents as a
Function of Temperature
REV. 0
ADG733/ADG734
8
TEMPERATURE C
0.25
5
CURRENT
nA
V
DD
= 3V
V
SS
= GND
V
D
= 2.7V/1V
V
S
= 1V/2.7V
I
S
, I
D
(ON)
I
S
(OFF)
0.20
0.15
0.10
0.05
0
0.05
20
35
50
65
80
0.10
TPC 10. Leakage Currents as a
Function of Temperature
V
SS
= 3V
V
DD
= GND
V
SS
= +3V
V
DD
= 3V
V
DD
= 5V
V
SS
= GND
T
A
= 25 C
FREQUENCY kHz
10m
0.1
CURRENT
A
1m
100
10
1
100n
10n
1
10
100
1000
10000
TPC 13. Input Current, I
DD
vs.
Switching Frequency
VOLTAGE V
3
2
20
10
0
10
Q
INJ
pC
1
0
1
2
3
30
TA = 25 C
V
DD
= 5V
V
SS
= GND
V
DD
= +3V
V
SS
= 3V
V
DD
= 3V
V
SS
= GND
4
5
TPC 16. Charge Injection vs. Source
Voltage
TEMPERATURE C
40
20
TIME
ns
35
30
25
20
15
10
0
20
40
60
80
0
V
SS
= GND
t
ON
, V
DD
= 3V
t
OFF
, V
DD
= 3V
t
ON
, V
DD
= 5V
t
OFF
, V
DD
= 5V
5
TPC 11. t
ON
/t
OFF
Times vs.
Temperature
FREQUENCY kHz
0
30k
ATTENUATION
dB
20
40
60
80
100
120
100k
1M
10M
100M
V
DD
= 5V
T
A
= 25 C
TPC 14. Off Isolation vs. Frequency
FREQUENCY
H
Z
0
10M
10k
4
2
100k
1M
100M
6
ON
RESPONSE
dB
V
DD
= 5V
T
A
= 25 C
TPC 12. On Response vs. Frequency
FREQUENCY kHz
0
30k
ATTENUATION
dB
20
40
60
80
100
120
100k
1M
10M
100M
V
DD
= 5V
T
A
= 25 C
TPC 15. Crosstalk vs. Frequency
REV. 0
ADG733/ADG734
9
I
DS
V1
S
D
V
S
R
ON
= V1/I
DS
Test Circuit 1. On Resistance
Test Circuits
V
D
I
S
(OFF)
S
D
V
S
A
Test Circuit 2. I
S
(OFF)
I
D
(ON)
S
D
A
V
D
NC
Test Circuit 3. I
D
(ON)
S1A
D1
VS1B
IN/
EN
GND
R
L
300
C
L
35pF
V
OUT
V
DD
V
DD
0.1 F
S1B
VS1A
V
SS
V
SS
0.1 F
t
ON
90%
90%
50%
50%
ADDRESS
DRIVE
V
OUT
VS1B
VS1A
t
OFF
Test Circuit 4. Switching Times, t
ON
, t
OFF
3V
50%
OUTPUT
50%
t
ON
(
EN)
0.9V
0
0V
0V
ENABLE
DRIVE (V
IN
)
0.9V
0
V
O
t
OFF
(
EN)
A2
V
O
D1
V
S
A1
A0
EN
GND
ADG733
S1A
S1B
V
IN
50
R
L
300
C
L
35pF
V
DD
V
SS
V
SS
V
DD
0.1 F
Test Circuit 5. Enable Delay, t
ON
(
EN), t
OFF
(
EN)
V
OUT
D1
V
S
GND
ADG733/
ADG734
SA
SB
V
IN
50
ADDRESS*
*A0, A1, A2 FOR ADG733, IN1-4 FOR ADG734
V
SS
0.1 F
V
SS
V
DD
V
DD
0.1 F
R
L
300
C
L
35pF
ADDRESS
3V
V
OUT
t
OPEN
80%
80%
0V
V
S
Test Circuit 6. Break-Before-Make Delay, t
OPEN
REV. 0
ADG733/ADG734
10
* IN14 FOR ADG734
GND
V
DD
ADG733/
ADG734
V
OUT
C
L
1nF
V
S
R
S
D
S
V
DD
V
SS
V
SS
V
IN
EN*
V
OUT
3V
V
OUT
LOGIC
INPUT (V
IN
)
Q
INJ
= C
L
V
OUT
0V
Test Circuit 7. Charge Injection
SWITCH OPEN FOR OFF ISOLATION MEASUREMENTS
SWITCH CLOSED FOR BANDWIDTH MEASUREMENTS
OFF ISOLATION = 20LOG
10
(V
OUT
/V
S
)
INSERTION LOSS = 20LOG
10
(
V
OUT
WITH SWITCH
V
OUT
WITHOUT SWITCH
)
S
D
0.1 F
V
DD
IN/
EN
V
S
GND
R
L
50
V
OUT
V
DD
V
SS
0.1 F
V
SS
Test Circuit 8. OFF Isolation and Bandwidth
S
D
0.1 F
V
DD
V
S
GND
50
NC
D
S
R
L
50
CHANNEL-TO-CHANNEL
CROSSTALK
20 LOG
|
V
S
/V
OUT
|
V
DD
V
OUT
0.1 F
V
SS
NC = NO CONNECT
V
SS
Test Circuit 9. Channel-to-Channel Crosstalk
REV. 0
ADG733/ADG734
11
16-Lead TSSOP
(RU-16)
16
9
8
1
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
0.201 (5.10)
0.193 (4.90)
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
0.0433 (1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8
0
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead TSSOP
(RU-20)
20
11
10
1
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
0.260 (6.60)
0.252 (6.40)
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
0.0433 (1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8
0
16-Lead QSOP
(RQ-16)
16
9
8
1
0.197 (5.00)
0.189 (4.80)
0.244 (6.20)
0.228 (5.79)
PIN 1
0.157 (3.99)
0.150 (3.81)
SEATING
PLANE
0.010 (0.25)
0.004 (0.10)
0.012 (0.30)
0.008 (0.20)
0.025
(0.64)
BSC
0.059 (1.50)
MAX
0.069 (1.75)
0.053 (1.35)
0.010 (0.20)
0.007 (0.18)
0.050 (1.27)
0.016 (0.41)
8
0
C016022.51/01 (rev. 0)
PRINTED IN U.S.A.
Document Outline
- Specifications
- Pinout
- Package Drawings
- Ordering Guide
- Features
- Applications
- Product Description
- Absolute Maximum Ratings
- Functional Block Diagram
- Typical Characteristics
- CAUTION
- PRODUCT HIGHLIGHTS
- TSSOP/QSOP TSSOP
- TERMINOLOGY
- DIAGRAMS
- Test Circuit 1. On Resistance
- Test Circuit 2. IS (OFF)
- Test Circuit 3. ID (ON)
- Test Circuit 4. Switching Times, tON, tOFF
- Test Circuit 5. Enable Delay, tON (EN ), tOFF (EN
- Test Circuit 6. Break-Before-Make Delay, tOPEN
- Test Circuit 7. Charge Injection
- Test Circuit 8. OFF Isolation and Bandwidth
- Test Circuit 9. Channel-to-Channel Crosstalk
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