www.docs.chipfind.ru
High Speed, Half-Duplex iCoupler
Isolated RS-485 Transceiver
ADM2486
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2005 Analog Devices, Inc. All rights reserved.
FEATURES
Half-duplex, isolated RS-485 transceiver
PROFIBUS-compliant
ANSI EIA/TIA 485-A and ISO 8482: 1987(E) compliant
20 Mbps data rate
5 V or 3 V operation (V
DD1
)
High common-mode transient immunity: >25 kV/s
Isolated DE status output
Receiver open-circuit, fail-safe design
Thermal shutdown protection
50 nodes on bus
Safety and regulatory approvals
UL recognition--2500 V
rms
for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity
DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01
DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000
V
IORM
= 560 V peak
Operating temperature range: -40C to +85C
Wide body, 16-lead SOIC package
APPLICATIONS
Isolated RS-485/RS-422 interfaces
PROFIBUS networks
Industrial field networks
Multipoint data transmission systems
GENERAL DESCRIPTION
The ADM2486 differential bus transceiver is an integrated,
galvanically isolated component designed for bidirectional
data communication on multipoint bus transmission lines. It
is designed for balanced transmission lines and complies with
ANSI EIA/TIA-485-A and ISO 8482: 1987(E).
FUNCTIONAL BLOCK DIAGRAM
RTS
V
DD1
DE
GND
1
A
B
V
DD2
GND
2
GALV
ANIC IS
OLATION
LOGIC SIDE
TxD
RxD
BUS
S
I
DE
04604-001
RE
PV
ADM2486
Figure 1.
The device employs Analog Devices' iCoupler technology to
combine a 3-channel isolator, a three-state differential line
driver, and a differential input receiver into a single package.
The logic side of the device is powered with either a 5 V or a
3 V supply, and the bus side uses an isolated 5 V supply.
The ADM2486 driver has an active-high enable feature. The
driver differential outputs and the receiver differential inputs
are connected internally to form a differential input/output port
that imposes minimal loading on the bus when the driver is
disabled or when V
DD1
or V
DD2
= 0 V. Also provided is an active-
high receiver disable feature that causes the receive output to
enter a high impedance state.
The device has current-limiting and thermal shutdown features
to protect against output short circuits and situations where bus
contention might cause excessive power dissipation. The part is
fully specified over the industrial temperature range and is
available in a 16-lead, wide body SOIC package.
ADM2486
Rev. C | Page 2 of 20
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
ADM2486 Characteristics ............................................................... 7
Package Characteristics ............................................................... 7
Regulatory Information............................................................... 7
Insulation and Safety-Related Specifications............................ 7
VDE 0884 Insulation Characteristics ........................................ 8
Pin Configuration and Function Descriptions............................. 9
Test Circuits..................................................................................... 10
Switching Characteristics .............................................................. 11
Typical Performance Characteristics ........................................... 12
Circuit Description......................................................................... 14
Electrical Isolation...................................................................... 14
Truth Tables................................................................................. 14
Power-Up/Power-Down Thresholds ....................................... 14
Thermal Shutdown .................................................................... 15
Receiver Fail-Safe Inputs ........................................................... 15
Magnetic Field Immunity.......................................................... 15
Applications Information .............................................................. 16
Power_Valid Input ..................................................................... 16
Isolated Power Supply Circuit .................................................. 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
3/05--Rev. B to Rev. C
Change to Package Characteristics................................................. 7
Changes to Figure 12, Figure 14, and Figure 15 ......................... 11
Change to Power_Valid Input Section......................................... 16
1/05--Rev. A to Rev. B
Added PROFIBUS logo ................................................................... 1
11/04--Rev. 0 to Rev. A
Changes to Figure 1.......................................................................... 1
Changes to Figure 6........................................................................ 10
Added Figure 22 through Figure 25............................................. 13
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 18
ADM2486
Rev. C | Page 3 of 20
SPECIFICATIONS
2.7 V V
DD1
5.5 V, 4.75 V V
DD2
5.25 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter Min
Typ
Max
Unit
Test
Conditions/Comments
DRIVER
Differential Outputs
Differential Output Voltage, V
OD
5
V
R = , see Figure 3
2.1
5
V
R = 50 (RS-422), see Figure 3
2.1
5
V
R = 27 (RS-485), see Figure 3
2.1
5
V
V
TST
= -7 V to 12 V, V
DD1
4.7,
see Figure 4
|V
OD
| for Complementary Output States
0.2
V
R = 27 or 50 , see Figure 3
Common-Mode Output Voltage, V
OC
3
V
R = 27 or 50 , see Figure 3
|V
OC
| for Complementary Output States
0.2
V
R = 27 or 50 , see Figure 3
Output Short-Circuit Current, V
OUT
= High
60
200
mA
-7 V V
OUT
+12 V
Output Short-Circuit Current, V
OUT
= Low
60
200
mA
-7 V V
OUT
+12 V
Bus Enable Output
Output High Voltage
V
DD2
- 0.1
V
I
ODE
= 20 A
V
DD2
- 0.3
V
DD2
- 0.1
V
I
ODE
= 1.6 mA
V
DD2
- 0.4
V
DD2
- 0.2
V
I
ODE
= 4 mA
Output Low Voltage
0.1
V
I
ODE
= -20 A
0.1
0.3
V
I
ODE
= -1.6 mA
0.2
0.4
V
I
ODE
= -4 mA
Logic Inputs
Input High Voltage
0.7 V
DD1
V TxD, RTS, RE, PV
Input Low Voltage
0.25 V
DD1
V
TxD, RTS, RE, PV
CMOS Logic Input Current (TxD, RTS, RE, PV)
-10 0.01 10 A
TxD, RTS, RE, PV = V
DD1
or 0 V
RECEIVER
Differential Inputs
Differential Input Threshold Voltage, V
TH
-200
200
mV
-7 V V
CM
+12V
Input Hysteresis
70
mV
-7 V V
CM
+12V
Input Resistance (A, B)
20
30
k
-7 V V
CM
+12V
Input Current (A, B)
0.6
mA
V
IN
= +12 V
-0.35
mA
V
IN
= -7 V
RxD Logic Output
Output High Voltage
V
DD1
- 0.1
V
I
OUT
= 20 A, V
A
- V
B
= 0.2 V
V
DD1
- 0.4
V
DD1
- 0.2
V
I
OUT
= 4 mA, V
A
- V
B
= 0.2 V
Output Low Voltage
0.1
V
I
OUT
= -20 A, V
A
- V
B
= -0.2 V
0.2
0.4
V
I
OUT
= -4 mA, V
A
- V
B
= -0.2 V
Output Short-Circuit Current
7
85
mA
V
OUT
= GND or V
CC
Three-State Output Leakage Current
1
A
0.4 V V
OUT
2.4 V
ADM2486
Rev. C | Page 4 of 20
Parameter Min
Typ
Max
Unit
Test
Conditions/Comments
POWER SUPPLY CURRENT
Logic Side
1.3
mA
RTS = 0 V, V
DD1
= 5.5 V
2.9
mA
2 Mbps, V
DD1
= 5.5 V, see Figure 5
10.2
mA
20 Mbps, V
DD1
= 5.5 V, see Figure 5
0.8
mA
RTS = 0 V, V
DD1
= 3 V
1.1
mA
2 Mbps, V
DD1
= 3 V, see Figure 5
4.3
mA
20 Mbps, V
DD1
= 3 V, see Figure 5
Bus Side
3.0
mA
RTS = 0 V
53.4
mA
2 Mbps, RTS = V
DD1
, see Figure 5
86.7
mA
20 Mbps, RTS = V
DD1
, see Figure 5
COMMON-MODE TRANSIENT IMMUNITY
1
25
kV/s
V
CM
= 1 kV,
transient magnitude = 800 V
HIGH FREQUENCY, COMMON-MODE NOISE
IMMUNITY
100
mV
V
HF
= +5 V, -2 V < V
TEST2
< 7 V,
1 MHz < f
TEST
< 50 MHz, see Figure 6
1
Common-mode transient immunity is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation.
V
CM
is the common-mode potential difference between the logic and bus sides. The transient magnitude is the range over which the common-mode is slewed. The
common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
ADM2486
Rev. C | Page 5 of 20
TIMING SPECIFICATIONS
2.7 V V
DD1
5.5 V, 4.75 V V
DD2
5.25 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter Min
Typ
Max
Unit
Test
Conditions/Comments
DRIVER
Maximum Data Rate
20
Mbps
Propagation Delay, t
PLH
, t
PHL
25
45
55
ns
R
LDIFF
= 54 , C
L1
= C
L2
= 100 pF, see Figure 7
RTS-to-DE Propagation Delay
20
35
55
ns
See Figure 8
Pulse Width Distortion, t
PWD
5
ns
R
LDIFF
= 54 , C
L1
= C
L2
= 100 pF, see Figure 7 and
Figure 12
Switching Skew, t
SKEW
2
5
ns
R
LDIFF
= 54 , C
L1
= C
L2
= 100 pF, see Figure 7 and
Figure 12
Rise/Fall Time, t
R
, t
F
5
15
ns
R
LDIFF
= 54 , C
L1
= C
L2
= 100 pF, see Figure 7 and
Figure 12
Enable Time
43
53
ns
See Figure 9 and Figure 14
Disable Time
43
55
ns
See Figure 9 and Figure 14
Enable Skew, |t
AZH
- t
BZL
|, |t
AZL
- t
BZH
|
1
3
ns
See Figure 9 and Figure 14
Disable Skew, |t
AHZ
- t
BLZ
|, |t
ALZ
- t
BHZ
|
2
5
ns
See Figure 9 and Figure 14
RECEIVER
Propagation Delay, t
PLH
, t
PHL
25
45
55
ns
C
L
= 15 pF, see Figure 10 and Figure 13
Differential Skew, t
SKEW
5
ns
C
L
= 15 pF, see Figure 10 and Figure 13
Enable Time
3
13
ns
R
L
= 1 k, C
L
= 15 pF, see Figure 11 and Figure 15
Disable Time
3
13
ns
R
L
= 1 k, C
L
= 15 pF, see Figure 11 and Figure 15
POWER_VALID
INPUT
Enable Time
1
2
s
Disable Time
3
5
s
ADM2486
Rev. C | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
T
A
= 25C, unless otherwise noted. All voltages are relative to
their respective ground.
Table 3.
Parameter
Rating
V
DD1
-0.5 V to +7 V
V
DD2
-0.5 V to +6 V
Digital Input Voltage (RTS, RE, TxD)
-0.5 V to V
DD1
+ 0.5 V
Digital Output Voltage
RxD
-0.5 V to V
DD1
+ 0.5 V
DE
-0.5 V to V
DD2
+ 0.5 V
Driver Output/Receiver Input Voltage
-9 V to +14 V
Operating Temperature Range
-40C to +85C
Storage Temperature Range
-55C to +150C
Average Output Current per Pin
-35 mA to +35 mA
JA
Thermal Impedance
73C/W
Lead Temperature
Soldering (10 sec)
260C
Vapor Phase (60 sec)
215C
Infrared (15 sec)
220C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degrada-
tion or loss of functionality.
ADM2486
Rev. C | Page 7 of 20
ADM2486 CHARACTERISTICS
PACKAGE CHARACTERISTICS
Table 4.
Parameter Symbol
Min
Typ
Max
Unit
Test
Conditions
Resistance (Input-Output)
1
R
I-O
10
12
Capacitance (Input-Output)
1
C
I-O
3
pF
f = 1 MHz
Input Capacitance
2
C
I
4
pF
Input IC Junction-to-Case Thermal Resistance
JCI
33
C/W
Output IC Junction-to-Case Thermal Resistance
JCO
28
C/W
Thermocouple located at
center of package underside
1
Device considered a 2-terminal device: Pins 1, 2, 3, 4, 5, 6, 7, and 8 shorted together, and Pins 9, 10, 11, 12, 13, 14, 15, and 16 shorted together.
2
Input capacitance is from any input data pin to ground
REGULATORY INFORMATION
The ADM2486 has been approved by the following organizations:
Table 5.
Organization Approval
Type
Notes
UL
Recognized under 1577 component recognition program.
File E214100
In accordance with UL1577, each ADM2486
is proof tested by applying an insulation
test voltage 3000 V rms for 1 sec (current
leakage detection limit = 5 A).
CSA
Approved under CSA Component Acceptance Notice #5A. File 205078.
VDE
Certified according to DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01
Complies with DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01,
DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000
File 2471900-4880-0001
In accordance with VDE 0884, each ADM2486
is proof tested by applying an insulation
test voltage 1050 V
PEAK
for 1 sec
(partial discharge detection limit = 5 pC).
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter Symbol
Value
Unit
Conditions
Rated Dielectric Insulation Voltage
2500
V rms
1-minute duration.
Minimum External Air Gap (Clearance)
L(I01)
7.45 min
mm
Measured from input terminals to output
terminals, shortest distance through air.
Minimum External Tracking (Creepage)
L(I02)
8.1 min
mm
Measured from input terminals to output
terminals, shortest distance along body.
Minimum Internal Gap (Internal Clearance)
0.017 min
mm
Insulation distance through insulation.
Tracking Resistance (Comparative Tracking Index)
CTI
>175
V
DIN IEC 112/VDE 0303 Part 1.
Isolation
Group
IIIa Material
Group (DIN VDE 0110, 1/89, Table 1).
ADM2486
Rev. C | Page 8 of 20
VDE 0884 INSULATION CHARACTERISTICS
This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data must be ensured by
means of protective circuits.
An asterisk (*) on the physical package denotes VDE 0884 approval for 560 V peak working voltage.
Table 7.
Description Symbol
Characteristic
Unit
Installation Classification per DIN VDE 0110 for Rated Mains Voltage
150 V rms
I to IV
300 V rms
I to III
400 V rms
I to II
Climatic Classification
40/85/21
Pollution Degree (DIN VDE 0110, Table 1)
2
Maximum Working Insulation Voltage
V
IORM
560 V
PEAK
Input-to-Output Test Voltage, Method b1
V
PR
1050
V
PEAK
V
IORM
1.875 = V
PR
, 100% Production Tested, t
m
= 1 sec, Partial Discharge < 5 pC
Input-to-Output Test Voltage, Method a
(After Environmental Tests, Subgroup 1)
V
IORM
1.6 = V
PR
, t
m
= 60 sec, Partial Discharge < 5 pC
896
V
PEAK
(After Input and/or Safety Test, Subgroup 2/3)
V
IORM
1.2 = V
PR
, t
m
= 60 sec, Partial Discharge < 5 pC
V
PR
672 V
PEAK
Highest Allowable Overvoltage
(Transient Overvoltage, t
TR
= 10 sec)
V
TR
4000
V
PEAK
Safety-Limiting Values (Mximum Value Allowed in the Event of a Failure. See
Figure 21.)
Case Temperature
T
S
150
C
Input Current
I
S
,
INPUT
265
mA
Output Current
I
S
,
OUTPUT
335
mA
Insulation Resistance at Ts, V
IO
= 500 V
R
S
>10
9
ADM2486
Rev. C | Page 9 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADM2486
TOP VIEW
(Not to Scale)
V
DD1 1
GND
1
1 2
RxD
3
RE
4
V
DD2
GND
2
1
NC
B
16
15
14
13
04604-003
5
6
4
12
11
5
7
8
10
9
RTS
TxD
PV
GND
1
1
A
NC
DE
GND
2
1
NC = NO CONNECT
1
PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED.
EITHER OR BOTH MAY BE USED FOR GND1.
PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED.
EITHER OR BOTH MAY BE USED FOR GND2.
Figure 2. Pin Configuration
Table 8.
Pin No.
Mnemonic
Function
1 V
DD1
Power Supply (Logic Side).
2, 8
GND
1
Ground (Logic Side).
3 RD
Receiver Output Data. This output is high when (A B) > 200 mV, and low when (A B) < 200 mV.
The output is three-stated when the receiver is disabled, that is, when RE is driven high.
4
RE
Receiver Enable Input. This is an active-low input. Driving this input low enables the receiver, and driving
it high disables the receiver.
5
RTS
Request to Send Input. Driving this input high enables the driver, and driving it low disables the driver.
6
TxD
Transmit Data Input. Data to be transmitted by the driver is applied to this input.
7
PV
Power_Valid. Used during power-up and power-down. See the Applications Information section.
9, 15
GND
2
Ground (Bus Side).
10 DE Driver Enable Status Output. This output signals the driver enable or disable status to other devices on
the bus. DE is high when the driver is enabled and low when the driver is disabled.
11, 14
NC
No Connect.
12 A Noninverting Driver Output/Receiver Input. When the driver is disabled, or when V
DD1
or V
DD2
is powered
down, Pin A is put into a high impedance state to avoid overloading the bus.
13 B Inverting Driver Output/Receiver Input. When the driver is disabled, or when V
DD1
or V
DD2
is powered
down, Pin B is put into a high impedance state to avoid overloading the bus.
16 V
DD2
Power Supply (Bus Side).
ADM2486
Rev. C | Page 10 of 20
TEST CIRCUITS
04604-005
V
OC
R
R
V
OD
Figure 3. Driver Voltage Measurement
04604-006
60
V
OD3
375
375
V
TEST
Figure 4. Driver Voltage Measurement
V
DD1
DE
150
GND
1
A
B
V
DD2
GND
2
GALV
ANIC IS
OLATION
04604-004
V
DD2
195
110
195
GND
2
RTS
TxD
RxD
RE
Figure 5. Supply-Current Measurement Test Circuit
V
DD1
DE
GND
1
A
B
V
DD2
GND
2
GA
LVA
N
I
C
ISOLA
TION
04604-
010
50
110nF
50
V
TEST2
RTS
TxD
RxD
GND
2
2.2k
100nF
100nF
V
CM(HF)
470nF
22k
F
TEST
,
V
HF
RECEIVE
ENABLE
195
110
195
V
DD2
GND
2
Figure 6. High Frequency Common-Mode Noise Test Circuit
04604-007
C
L2
C
L1
R
LDIFF
A
B
Figure 7. Driver Propagation Delay
V
DD1
DE
GND
1
A
B
V
DD2
GND
2
GALV
ANIC IS
OLATION
04604-008
RTS
TxD
RxD
RE
150
50pF
Figure 8. RTS-to-DE Propagation Delay
04604-009
V
CC
S2
V
OUT
110
50pF
S1
B
A
TxD
RTS
Figure 9. Driver Enable/Disable
04604-012
C
L
V
OUT
RE
A
B
Figure 10. Receiver Propagation Delay
04604-013
V
CC
S2
V
OUT
R
L
C
L
+1.5V
1.5V
S1
RE
RE IN
Figure 11. Receiver Enable/Disable
ADM2486
Rev. C | Page 11 of 20
SWITCHING CHARACTERISTICS
04604-011
t
PAHL
t
PBHL
t
PALH
t
PBLH
V
DD1
0V
VO
B
A
V
OH
A, B
V
OL
0.5V
DD1
0.5V
DD1
t
SKEW
t
F
t
R
10% POINT
10% POINT
90% POINT
90% POINT
1/2VO
t
SKEW
t
PWD
= |t
PALH
t
PAHL
|, |t
PBLH
t
PBHL
|
Figure 12. Driver Propagation Delay, Rise/Fall Timing
04604-019
A B
RxD
0V
0V
1.5V
1.5V
t
PLH
t
SKEW
= |t
PLH
t
PHL
|
t
PHL
V
OH
V
OL
Figure 13. Receiver Propagation Delay
04604-021
t
LZ
t
ZL
t
HZ
t
ZH
V
OH
0.5V
V
OH
+ 0.5V
A, B
A, B
RTS
0.7V
DD1
0.3V
DD1
0.5V
DD1
0.5V
DD1
2.3V
2.3V
V
OL
V
OH
0V
Figure 14. Driver Enable/Disable Timing
04604-020
0.7V
DD1
0.3V
DD1
0.5V
DD1
0.5V
DD1
V
OH
V
OL
O/P LOW
O/P HIGH
t
LZ
t
ZL
t
HZ
t
ZH
V
OH
0.5V
V
OL
+ 0.5V
1.5V
1.5V
RxD
RxD
RE
0V
Figure 15. Receiver Enable/Disable Timing
ADM2486
Rev. C | Page 12 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
40
25
85
TEMPERATURE (
C)
S
U
P
P
L
Y
CURRE
NT (mA)
04604-029
I
DD1
_RCVR_ENABLE @ 5.5V
I
DD2
_DE_ENABLE @ 5.5V
Figure 16. Unloaded Supply Current vs. Temperature
10
15
20
25
30
35
40
45
50
40
25
85
TEMPERATURE (
C)
TIME (ns)
RECEIVER
t
PHL
RECEIVER
t
PLH
0
5
04604-026
Figure 17. Driver Propagation Delay vs. Temperature
DRIVER
t
AHL
DRIVER
t
BLH
DRIVER
t
BHL
10
15
20
25
30
35
40
45
50
40
25
85
TEMPERATURE (
C)
TIME (ns)
0
5
DRIVER
t
ALH
04604-027
Figure 18. Receiver Propagation Delay vs. Temperature
04604-025
CH1 2.00V
CH2 2.00V
CH3 2.00V
CH4 2.00V
M20.0ns
A CH2 3.12V
1
2
4
T
6.00000ns
Figure 19. Driver/Receiver Propagation Delay, Low to High
(R
LDiff
= 54 , C
L1
= C
L2
= 100 pF)
04604-028
CH1 5.00V
CH2 2.00V
CH3 2.00V
CH4 2.00V
M20.0ns
A CH1 2.60V
1
3
4
T
444.400ns
Figure 20. Driver/Receiver Propagation Delay, High to Low
(R
LDiff
= 54 , C
L1
= C
L2
= 100 pF)
CASE TEMPERATURE (
C)
S
A
FE
TY
-LIMITING CURRE
NT (mA)
0
0
350
300
250
200
150
100
50
50
100
150
200
SIDE 1
SIDE 2
04604-018
Figure 21. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per VDE 0884
ADM2486
Rev. C | Page 13 of 20
OUTP
UT CURRE
NT (mA)
30
25
20
15
10
5
0
04604-031
OUTPUT VOLTAGE (V)
3.04
3.30
3.56
3.82
4.07
4.31
4.55
4.79
5.00
Figure 22. Output Current vs. Receiver Output High Voltage
OUTP
UT CURRE
NT (mA)
5
10
15
20
25
30
35
04604-032
OUTPUT VOLTAGE (V)
0
0.23
0.46 0.69
0.93
1.17 1.42
1.67
1.93
0
2.20
Figure 23. Output Current vs. Receiver Output Low Voltage
OUTPUT VOLTAGE (V)
4.66
4.68
4.70
4.72
4.74
4.76
4.78
04604-033
TEMPERATURE (
C)
40
25
10
5
20
35
50
65
80
Figure 24. Receiver Output High Voltage vs. Temperature I = -4 mA
OUTPUT VOLTAGE (V)
0.20
0.22
0.24
0.26
0.28
0.30
0.32
04604-034
TEMPERATURE (
C)
40
25
10
5
20
35
50
65
80
Figure 25. Receiver Output Low Voltage vs. Temperature I = 4 mA
ADM2486
Rev. C | Page 14 of 20
CIRCUIT DESCRIPTION
ELECTRICAL ISOLATION
In the ADM2486, electrical isolation is implemented on the
logic side of the interface. Therefore, the part has two main
sections: a digital isolation section and a transceiver section
(see Figure 26). Driver input and request-to-send signals,
applied to the TxD and RTS pins, respectively, and referenced to
logic ground (GND
1
), are coupled across an isolation barrier to
appear at the transceiver section referenced to isolated ground
(GND
2
). Similarly, the receiver output, referenced to isolated
ground in the transceiver section, is coupled across the isolation
barrier to appear at the RxD pin referenced to logic ground.
iCoupler Technology
The digital signals are transmitted across the isolation barrier
using iCoupler technology. This technique uses chip-scale
transformer windings to couple the digital signals magnetically
from one side of the barrier to the other. Digital inputs are
encoded into waveforms that are capable of exciting the
primary transformer winding. At the secondary winding, the
induced waveforms are then decoded into the binary value that
was originally transmitted.
04604-
022
ISOLATION
BARRIER
V
DD2
V
DD1
A
B
DE
GND
2
GND
1
TxD
RTS
RxD
RE
ENCODE
DECODE
DECODE
DECODE
ENCODE
ENCODE
D
R
TRANSCEIVER
DIGITAL ISOLATION
Figure 26. ADM2486 Digital Isolation and Transceiver Sections
TRUTH TABLES
The truth tables in this section use these abbreviations:
Letter Description
H High
level
I Indeterminate
L Low
level
X Irrelevant
Z
High impedance (off)
NC
Disconnected
Table 9. Transmitting
Supply Status
Inputs Output
V
DD1
V
DD2
RTS
TxD
A
B
DE
On On
H H H L H
On On
H L
L H H
On On
L X
Z Z L
On Off
X X
Z Z L
Off On
X X
Z Z L
Off Off
X X
Z Z L
Table 10. Receiving
Supply Status
Inputs Output
V
DD1
V
DD2
A - B (V)
RE
RxD
On
On
>0.2
L or NC
H
On
On
<-0.2
L or NC
L
On
On
-0.2 < A - B < 0.2
L or NC
I
On
On
Inputs open
L or NC
H
On On X
H
Z
On
Off
X
L or NC
H
Off
On
X
L or NC
H
Off
Off
X
L or NC
L
POWER-UP/POWER-DOWN THRESHOLDS
The power-up/power-down characteristics of the ADM2486 are
in accordance with the supply thresholds shown in Table 11.
Upon power-up, the ADM2486 output signals (A, B, RxD, and
DE) reach their correct state once both supplies have exceeded
their thresholds. Upon power-down, the ADM2486 output
signals retain their correct state until at least one of the supplies
drops below its power-down threshold. When the V
DD1
power-
down threshold is crossed, the ADM2486 output signals reach
their unpowered states within 4 s.
Table 11. Power-Up/Power-Down Thresholds
Supply Transition
Threshold
(V)
V
DD1
Power-up
2.0
V
DD1
Power-down 1.0
V
DD2
Power-up
3.3
V
DD2
Power-down 2.4
ADM2486
Rev. C | Page 15 of 20
THERMAL SHUTDOWN
The ADM2486 contains thermal shutdown circuitry that
protects the part from excessive power dissipation during fault
conditions. Shorting the driver outputs to a low impedance
source can result in high driver currents. The thermal sensing
circuitry detects the increase in die temperature under this
condition and disables the driver outputs. This circuitry is
designed to disable the driver outputs when a die temperature
of 150C is reached. As the device cools, the drivers are re-enabled
at a temperature of 140C.
RECEIVER FAIL-SAFE INPUTS
The receiver input includes a fail-safe feature that guarantees a
logic high RxD output when the A and B inputs are floating or
open-circuited.
MAGNETIC FIELD IMMUNITY
Because iCouplers use a coreless technology, no magnetic
components are present, and the problem of magnetic
saturation of the core material does not exist. Therefore,
iCouplers have essentially infinite dc field immunity. The
analysis below defines the conditions under which this may
occur. The ADM2486's 3 V operating condition is examined
because it represents the most susceptible mode of operation.
The limitation on the iCoupler's ac magnetic field immunity is
set by the condition in which the induced error voltage in the
receiving coil (the bottom coil in this case) is made sufficiently
large, either to falsely set or reset the decoder. The voltage
induced across the bottom coil is given by
-
=
2
n
r
dt
d
V
;
N
n
,
.
.
.
,
2
,
1
=
where, if the pulses at the transformer output are greater than
1.0 V in amplitude:
= magnetic flux density (gauss)
N = number of turns in receiving coil
r
n
= radius of nth turn in receiving coil (cm)
The decoder has a sensing threshold of about 0.5 V; therefore,
there is a 0.5 V margin in which induced voltages can be
tolerated.
Given the geometry of the receiving coil and an imposed
requirement that the induced voltage is, at most, 50% of the
0.5 V margin at the decoder, a maximum allowable magnetic
field is calculated, as shown in Figure 27.
04604-016
MAGNETIC FIELD FREQUENCY (Hz)
1k
10k
100k
100M
1M
10M
100.000
10.000
1.000
0.100
0.010
0.001
MAX
I
MUM ALLO
WABLE
MAG
N
E
T
IC
FLU
X D
E
N
S
ITY (
k
GA
U
SS)
Figure 27. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kGauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurs during a transmitted pulse and
is the worst-case polarity, it reduces the received pulse from
>1.0 V to 0.75 V. This is well above the 0.5 V sensing threshold
of the decoder.
Figure 28 shows the magnetic flux density values in terms of
more familiar quantities such as maximum allowable current
flow at given distances away from the ADM2486 transformers.
04604-017
MAGNETIC FIELD FREQUENCY (Hz)
1k
10k
100k
100M
1M
10M
DISTANCE = 1m
DISTANCE = 100mm
DISTANCE = 5mm
1000.00
100.00
0.10
1.00
10.00
0.01
MAX
I
MUM ALLOWABLE
CURRE
NT (k
A)
Figure 28. Maximum Allowable Current for
Various Current-to-ADM2486 Spacings
At combinations of strong magnetic field and high frequency,
any loops formed by printed circuit board traces could induce
sufficiently large error voltages to trigger the thresholds of
succeeding circuitry. Care should be taken in the layout of
such traces to avoid this possibility.
ADM2486
Rev. C | Page 16 of 20
APPLICATIONS INFORMATION
POWER_VALID INPUT
To avoid chatter on the A and B outputs caused by slow power-
up and power-down transients on V
DD1
(>100 s/V), the device
features a power_valid (PV) digital input. This pin should be
driven low until V
DD1
exceeds 2.0 V. When V
DD1
is greater than
2.0 V, this pin should be driven high. Conversely, upon power-
down, PV should be driven low before V
DD1
reaches 2.0 V.
If the PV pin is driven with an open-drain output, the
recommended value for the pull-up resistor is a 10 k resistor,
bypassed with a 100 pF capacitor to GND
1
(see Figure 30).
The power_valid input can be driven, for example, by the
output of a system reset circuit such as the ADM809Z, which
has a threshold voltage of 2.32 V.
ADM809Z
ADM2486
V
DD1
PV
GND
1
V
DD1
RESET
RESET
V
DD1
t
POR
2.32V
2.0V
2.32V
2.0V
04604-023
Figure 29. Driving PV with ADM809Z
ADM809Z
ADM2486
V
DD1
PV
GND
1
V
DD1
RESET
RESET
V
DD1
t
POR
2.32V
2.0V
2.32V
2.0V
04604-030
100pF
10k
Figure 30. Driving PV with an Open-Drain Output
ADM2486
Rev. C | Page 17 of 20
ISOLATED POWER SUPPLY CIRCUIT
The ADM2486 requires isolated power capable of 5 V at 100 mA
to be supplied between the V
DD2
and GND
2
pins. If no suitable
integrated power supply is available, a discrete circuit, such as
the one in Figure 31, can be used. A center-tapped transformer
provides electrical isolation. The primary winding is excited
with a pair of square waveforms that are 180 out of phase with
each other. A pair of Schottky diodes and a smoothing capacitor
are used to create a rectified signal from the secondary winding.
The ADP667 linear voltage regulator provides a regulated
power supply to the ADM2486's bus-side circuitry.
To create the pair of square waves, a D-type flip-flop with
complementary Q/Q outputs is used. The flip-flop can be
connected so that output Q follows the clock input signal. If no
local clock signal is available, a simple digital oscillator can be
implemented with a hex-inverting Schmitt trigger and a resistor
and capacitor. In this case, values of 3.9 k and 1 nF generate a
364 kHz square wave. A pair of discrete NMOS transistors,
switched by the Q/Q flip-flop outputs, conduct current through
the center tap of the primary transformer, winding in an
alternating fashion.
04604-024
ISOLATION
BARRIER
V
CC
78253
SD103C
SD103C
22
F
BS107A
BS107A
10
F
5V
OUT
IN
SET GND SHDN
V
CC
V
DD1
V
DD2
GND
1
GND
2
CLK
Q
Q
D
PR
CLR
74HC74A
100nF
V
CC
V
CC
100nF
74HC14A
3.9k
1nF
ADP667
ADM2486
Figure 31. Isolated Power Supply Circuit
ADM2486
Rev. C | Page 18 of 20
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-013AA
SEATING
PLANE
0.30 (0.0118)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
2.65 (0.1043)
2.35 (0.0925)
1.27 (0.0500)
BSC
16
9
8
1
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
10.50 (0.4134)
10.10 (0.3976)
8
0
0.75 (0.0295)
0.25 (0.0098)
45
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COPLANARITY
0.10
Figure 32. 16-Lead Standard Small Outline Package [SOIC]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
Data Rate (Mbps)
Temperature Range
Package Description
Quantity
Package Option
ADM2486BRW
20
-40C to +85C
16-Lead, Wide Body SOIC
47
RW-16
ADM2486BRW-REEL
20
-40C to +85C
16-Lead, Wide Body SOIC
1,000
RW-16
ADM2486BRWZ
1
20
-40C to +85C
16-Lead, Wide Body SOIC
47
RW-16
ADM2486BRWZ-REEL
1
20
-40C to +85C
16-Lead, Wide Body SOIC
1,000
RW-16
1
Z = Pb-free part.
ADM2486
Rev. C | Page 19 of 20
NOTES
ADM2486
Rev. C | Page 20 of 20
NOTES
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D0460403/05(C)
Document Outline
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- FUNCTIONAL BLOCK DIAGRAM
-
-
-
-
-
-
-
-
-
-
-
PDF 
ZIP