Document Outline
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- FUNCTIONAL BLOCK DIAGRAM
-
-
-
-
-
-
-
-
5 V Slew-Rate Limited Half- and Full-Duplex
RS-485/RS-422 Transceivers
ADM4850ADM4857
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
FEATURES
EIA RS-485-/RS-422-compliant
Data rate options
ADM4850/ADM4854--115 kbps
ADM4851/ADM4855--500 kbps
ADM4852/ADM4856--2.5 Mbps
ADM4853/ADM4857--10 Mbps
Half- and full-duplex options
Reduced slew rates for low EMI
True fail-safe receiver inputs
5 A (maximum) supply current in shutdown mode
Up to 256 transceivers on one bus
Outputs high-z when disabled or powered off
-7 V to +12 V bus common-mode range
Thermal shutdown and short-circuit protection
Pin-compatible with MAX308x
Specified over the -40C to +85C temperature range
Available in 8-lead SOIC and LFCSP packages
APPLICATIONS
Low power RS-485 applications
EMI-sensitive systems
DTE-DCE interfaces
Industrial control
Packet switching
Local area networks
Level translators
FUNCTIONAL BLOCK DIAGRAM
04931-001
RO
R
A
B
DI
D
Z
Y
GND
V
CC
ADM4854/ADM4855/
ADM4856/ADM4857
RO
RE
R
DE
DI
D
A
B
GND
V
CC
ADM4850/ADM4851/
ADM4852/ADM4853
Figure 1.
GENERAL DESCRIPTION
The ADM4850-ADM4857 are differential line transceivers
suitable for high speed half- and full-duplex data communication
on multipoint bus transmission lines. They are designed for
balanced data transmission and comply with EIA Standards
RS-485 and RS-422. The ADM4850-ADM4853 are half-duplex
transceivers, which share differential lines and have separate
enable inputs for the driver and receiver. The full-duplex
ADM4854-ADM4857 transceivers have dedicated differential
line driver outputs and receiver inputs.
The parts have a 1/8-unit-load receiver input impedance, which
allows up to 256 transceivers on one bus. Since only one driver
should be enabled at any time, the output of a disabled or pow-
ered-down driver is three-stated to avoid overloading the bus.
The receiver inputs have a true fail-safe feature, which ensures a
logic high output level when the inputs are open or shorted.
This guarantees that the receiver outputs are in a known state
before communication begins and when communication ends.
The driver outputs are slew-rate limited to reduce EMI and data
errors caused by reflections from improperly terminated buses.
Excessive power dissipation caused by bus contention or by
output shorting is prevented with a thermal shutdown circuit.
The parts are fully specified over the commercial and industrial
temperature ranges, and are available in 8-lead SOIC and LFCSP
packages.
Table 1. Selection Table
Part No
Half-/Full-Duplex
Data Rate
ADM4850 Half
115
kbps
ADM4851 Half
500
kbps
ADM4852 Half
2.5
Mbps
ADM4853 Half
10
Mbps
ADM4854 Full
115
kbp
ADM4855 Full
500
kbps
ADM4856 Full
2.5
Mbps
ADM4857 Full
10
Mbps
ADM4850ADM4857
Rev. 0 | Page 2 of 16
TABLE OF CONTENTS
Specifications..................................................................................... 3
ADM4850/ADM4854 Timing Specifications........................... 4
ADM4851/ADM4855 Timing Specifications........................... 4
ADM4852/ADM4856 Timing Specifications........................... 5
ADM4853/ADM4857 Timing Specifications........................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Test Circuits....................................................................................... 8
Switching Characteristics ................................................................ 9
Typical Performance Characteristics ........................................... 10
Circuit Description......................................................................... 12
Slew-Rate Control ...................................................................... 12
Receiver Input Filtering ............................................................. 12
Half-/Full-Duplex Operation ................................................... 12
High Receiver Input Impedance .............................................. 13
Three-State Bus Connection..................................................... 13
Shutdown Mode ......................................................................... 13
Fail-Safe Operation .................................................................... 13
Current Limit and Thermal Shutdown ................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 15
REVISION HISTORY
10/04--Revision 0: Initial Version
ADM4850ADM4857
Rev. 0 | Page 3 of 16
SPECIFICATIONS
V = 5 V 5%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter Min
Typ
Max
Unit
Test
Conditions/Comments
DRIVER
Differential Output Voltage, V
OD
V
CC
V
R =
, Figure 4
1
2.0
5
V
R = 50 (RS-422), Figure 4
1.5
5
V
R = 27 (RS-485), Figure 4
1.5
5
V
V
TST
= -7 V to 12 V, Figure 5
|V
OD
| for Complementary Output States
0.2
V
R = 27 or 50 , Figure 4
Common-Mode Output Voltage, V
O
3
V
R = 27 or 50 , Figure 4
|V
O
| for Complementary Output States
0.2
V
R = 27 or 50 , Figure 4
Output Short-Circuit Current, V
OUT
= High
-200
+200
mA
-7 V < V
OUT
< +12 V
Output Short-Circuit Current, V
OUT
= Low
-200
+200
mA
-7 V < V
OUT
< +12 V
DRIVER INPUT LOGIC
CMOS Input Logic Threshold Low
1.4
0.8
V
CMOS Input Logic Threshold High
2.0
1.4
V
CMOS Logic Input Current (DI)
1
A
DE Input Resistance to GND
220
k
RECEIVER
Differential Input Threshold Voltage, V
TH
-200
-125
-30
mV
-7 V < V
M
< +12 V
Input Hysteresis
20
mV
-7 V < V
M
< +12 V
Input Resistance (A, B)
96
150
k
-7 V < V
M
< +12 V
Input Current (A, B)
0.125
mA
V
IN
= +12 V
-0.1
mA
V
IN
= -7 V
CMOS Logic Input Current (RE)
1
A
CMOS Output Voltage Low
0.4
V
I
OUT
= +4 mA
CMOS Output Voltage High
4.0
V
I
OUT
= -4 mA
Output Short Circuit Current
7
85
mA
V
OUT
= GND or V
CC
Three-State Output Leakage Current
2
A
0.4 V V
OUT
2.4 V
POWER
SUPPLY
CURRENT
I (115 kbps Options)
5
A
DE = 0 V, RE = V
CC
(shutdown)
36 60 A
DE = 0 V, RE = 0 V
100 160 A
DE
=
V
CC
I (500 kbps Options)
5
A
DE = 0 V, RE = V
CC
(shutdown)
80
120
A
DE = 0 V, RE = 0 V
120 200 A
DE
=
V
CC
I (2.5 Mbps Options)
5
A
DE = 0 V, RE = V
CC
(shutdown)
250 400 A
DE = 0 V, RE = 0 V
320 500 A
DE
=
V
CC
I (10 Mbps Options)
5
A
DE = 0 V, RE = V
CC
(shutdown)
250 400 A
DE = 0 V, RE = 0 V
320 500 A
DE
=
V
CC
1
Guaranteed by design.
ADM4850ADM4857
Rev. 0 | Page 4 of 16
ADM4850/ADM4854 TIMING SPECIFICATIONS
V = 5 V 5%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter Min
Typ
Max
Unit
Test
Conditions/Comments
DRIVER
Maximum Data Rate
115
kbps
Propagation Delay t
PLH
, t
PHL
600
2500
ns R
LDIFF
= 54 , C
L1
= C
L2
= 100 pF, Figure 6
Skew t
SKEW
70
ns
R
LDIFF
= 54 , C
L1
= C
L2
= 100 pF, Figure 6
Rise/Fall Time t
R
, t
F
600
2400
ns R
LDIFF
= 54 , C
L1
= C
L2
= 100 pF, Figure 6
Enable
Time
2000
ns
R
L
= 500 , C
L
= 100 pF, Figure 7, ADM4850
Disable
Time
2000
ns
R
L
= 500 , C
L
= 15 pF, Figure 7, ADM4850
Enable Time from Shutdown
4000
ns
R
L
= 500 , C
L
= 100 pF, Figure 7, ADM4850
RECEIVER
Propagation Delay t
PLH
, t
PH
400
1000
ns C
L
= 15 pF, Figure 8
Differential Skew t
SKEW
255
ns
C
L
= 15 pF, Figure 8
Enable Time
5
50
ns
R
L
= 1 k, C
L
= 15 pF, Figure 9, ADM4850
Disable
Time
20 50 ns R
L
= 1 k, C
L
= 15 pF, Figure 9, ADM4850
Enable Time from Shutdown
4000
ns
R
L
= 1 k, C
L
= 15 pF, Figure 9, ADM4850
Time to Shut Down
50
330
3000
ns
ADM4850
1
1
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ADM4851/ADM4855 TIMING SPECIFICATIONS
V = 5 V 5%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 4.
Parameter Min
Typ
Max
Unit
Test
Conditions/Comments
DRIVER
Maximum Data Rate
500
kbps
Propagation Delay t
PLH
, t
PHL
250
600 ns R
LDIFF
= 54 , C
L1
= C
L2
= 100 pF, Figure 6
Skew t
SKEW
40
ns
R
LDIFF
= 54 , C
L1
= C
L2
= 100 pF, Figure 6
Rise/Fall Time t
R
, t
F
200
600 ns R
LDIFF
= 54 , C
L1
= C
L2
= 100 pF, Figure 6
Enable Time
1000
ns
R
L
= 500 , C
L
= 100 pF, Figure 7, ADM4851
Disable Time
1000
ns
R
L
= 500 , C
L
= 15 pF, Figure 7, ADM4851
Enable Time from Shutdown
4000
ns
R
L
= 500 , C
L
= 100 pF, Figure 7, ADM4851
RECEIVER
Propagation Delay t
PLH
, t
PHL
400
1000
ns C
L
= 15 pF, Figure 8
Differential Skew t
SKEW
250
ns
C
L
= 15 pF, Figure 8
Enable Time
5
50
ns
R
L
= 1 k, C
L
= 15 pF, Figure 9, ADM4851
Disable Time
20
50
ns
R
L
=1 k, C
L
= 15 pF, Figure 9, ADM4851
Enable Time from Shutdown
4000
ns
R
L
=1 k, C
L
= 15 pF, Figure 9, ADM4851
Time to Shut Down
50
330
3000
ns
ADM4851
1
1
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ADM4850ADM4857
Rev. 0 | Page 5 of 16
ADM4852/ADM4856 TIMING SPECIFICATIONS
V = 5 V 5%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 5.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DRIVER
Maximum Data Rate
2.5
Mbps
Propagation Delay t
PLH
, t
PHL
50
180
ns R
LDIFF
= 54 , C
L1
= C
L2
= 100 pF, Figure 6
Skew t
SKEW
50
ns
R
LDIFF
= 54 , C
L1
= C
L2
= 100 pF, Figure 6
Rise/Fall Time t
R
, t
F
140
ns
R
LDIFF
= 54 , C
L1
= C
L2
= 100 pF, Figure 6
Enable
Time
180
ns
R
L
= 500 , C
L
= 100 pF, Figure 7, ADM4852
Disable
Time
180
ns
R
L
= 500 , C
L
= 15 pF, Figure 7, ADM4852
Enable Time from Shutdown
4000
ns
R
L
=500 , C
L
= 100 pF, Figure 7, ADM4852
RECEIVER
Propagation Delay t
PLH
, t
PHL
55
190
ns C
L
= 15 pF, Figure 8
Differential Skew t
SKEW
50
ns
C
L
= 15 pF, Figure 8
Enable Time
5
50
ns
R
L
= 1 k, C
L
= 15 pF, Figure 9, ADM4852
Disable Time
20
50
ns
R
L
= 1 k, C
L
= 15 pF, Figure 9, ADM4852
Enable Time from Shutdown
4000
ns
R
L
= 1 k, C
L
= 15 pF, Figure 9, ADM4852
Time to Shut Down
50
330
3000
ns
ADM4852
1
1
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ADM4853/ADM4857 TIMING SPECIFICATIONS
V = 5 V 5%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 6.
Parameter Min
Typ
Max
Unit
Test
Conditions/Comments
DRIVER
Maximum Data Rate
10
Mbps
Propagation Delay t
PLH
, t
PHL
0 30
ns R
LDIFF
= 54 , C
L1
= C
L2
= 100 pF, Figure 6
Skew t
SKEW
10
ns
R
LDIFF
= 54 , C
L1
= C
L2
= 100 pF, Figure 6
Rise/Fall Time t
R
, t
F
30
ns
R
LDIFF
= 54 , C
L1
= C
L2
= 100 pF, Figure 6
Enable
Time
35
ns
R
L
= 500 , C
L
= 100 pF, Figure 7, ADM4853
Disable
Time
35
ns
R
L
= 500 , C
L
= 15 pF, Figure 7, ADM4853
Enable Time from Shutdown
4000
ns
R
L
= 500 , C
L
= 100 pF, Figure 7, ADM4853
RECEIVER
Propagation Delay t
PLH
, t
PHL
55
190
ns C
L
= 15 pF, Figure 8
Differential Skew t
SKEW
30
ns
C
L
= 15 pF, Figure 8
Enable Time
5
50
ns
R
L
= 1 k, C
L
= 15 pF, Figure 9, ADM4853
Disable Time
20
50
ns
R
L
= 1 k, C
L
= 15 pF, Figure 9, ADM4853
Enable Time from Shutdown
4000
ns
R
L
= 1 k, C
L
= 15 pF, Figure 9, ADM4853
Time to Shut Down
50
330
3000
ns
ADM4853
1
1
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ADM4850ADM4857
Rev. 0 | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter Rating
V
CC
to GND
6 V
Digital I/O Voltage (DE, RE, DI, ROUT)
-0.3 V to V
CC
+ 0.3 V
Driver Output/Receiver Input Voltage
-9 V to +14 V
Operating Temperature Range
-40C to +85C
Storage Temperature Range
-65C to +125C
JA
Thermal Impedance
SOIC 110C/W
LFCSP 62C/W
Lead Temperature
Soldering (10 s)
300C
Vapour Phase (60 s)
215C
Infrared (15 s)
220C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADM4850ADM4857
Rev. 0 | Page 7 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RO
1
V
CC
8
DI
4
GND
5
ADM4850/
ADM4851/
ADM4852/
ADM4853
TOP VIEW
(Not to Scale)
RE
2
B
7
04931-002
DE
A
6
3
Figure 2. ADM4850ADM4853 Pin Configuration
Table 8. ADM4850ADM4853 Pin Descriptions
Pin No.
Mnemonic
Description
1 RO
Receiver Output. When enabled, if (A-B) -30 mV, then RO = high.
If (A-B) -200 mV, then RO = low.
2
RE
Receiver Output Enable.
A low level enables the receiver output, RO.
A high level places it in a high impedance state.
3 DE
Driver Output Enable. A high level enables the driver differential inputs A and B.
A low level places it in a high impedance state.
4 DI
Driver Input. When the driver is enabled, a logic low on DI forces A low and B high,
while a logic high on DI forces A high and B low.
5 GND
Ground.
6 A
Noninverting
Receiver
Input A/Driver Output A.
7
B
Inverting Receiver Input B/Driver Output B.
8 V
CC
5 V Power Supply.
V
CC
1
A
8
GND
4
Y
5
ADM4854/
ADM4855/
ADM4856/
ADM4857
TOP VIEW
(Not to Scale)
RO
2
B
7
04931-003
DI
Z
6
3
Figure 3. ADM4854ADM4857 Pin Configuration
Table 9. ADM4854ADM4857 Pin Descriptions
Pin No.
Mnemonic
Description
1
V
CC
5 V Power Supply.
2
RO
Receiver Output. When enabled, if (A-B) -30 mV, then RO = high.
If (A-B) -200 mV, then RO = low.
3
DI
Driver Input. When the driver is enabled, a logic low on DI forces Y low and Z high,
while a logic high on DI forces Y high and Z low.
4
GND
Ground.
5
Y
Driver Noninverting Output.
6
Z
Driver Inverting Output.
7
B
Receiver Inverting Input.
8
A
Receiver Noninverting Input.
ADM4850ADM4857
Rev. 0 | Page 8 of 16
TEST CIRCUITS
04931-004
V
OD
R
R
V
OC
Figure 4. Driver Voltage Measurement
04931-005
V
OD3
60
375
375
V
TST
Figure 5. Driver Voltage Measurement over Common-Mode Voltage Range
04931-006
C
L1
C
L2
R
LDIFF
A
B
Figure 6. Driver Propagation Delay
04931-007
R
L
V
CC
S2
V
OUT
DE IN
0V OR 3V
DE
S1
B
A
C
L
Figure 7. Driver Enable/Disable
04931-008
RE
B
A
C
L
V
OUT
Figure 8. Receiver Propagation Delay
RE
04931-009
R
L
V
CC
S2
V
OUT
S1
C
L
+1.5V
1.5V
RE IN
Figure 9. Receiver Enable/Disable
ADM4850ADM4857
Rev. 0 | Page 9 of 16
SWITCHING CHARACTERISTICS
04931-010
3V
0V
5V
0V
A
B
VO
t
R
t
F
t
PLH
t
PHL
90% POINT
10% POINT
90% POINT
10% POINT
t
SKEW
=
|t
PLH
t
PHL
|
1/2VO
1.5V
1.5V
Figure 10. Driver Propagation Delay, Rise/Fall Timing
04931-011
t
SKEW
=
|t
PLH
t
PHL
|
1.5V
1.5V
t
PLH
t
PHL
RO
V
OH
0V
A, B
0V
V
OL
Figure 11. Receiver Propagation Delay
04931-012
A, B
A, B
DE
3V
0V
0V
V
OH
V
OL
1.5V
t
LZ
t
ZL
1.5V
t
HZ
t
ZH
2.3V
2.3V
V
OL
+0.5V
V
OH
0.5V
Figure 12. Driver Enable/Disable Timing
04931-013
R
R
RE
3V
0V
0V
V
OH
V
OL
1.5V
t
LZ
t
ZL
1.5V
t
HZ
t
ZH
1.5V
1.5V
V
OL
+0.5V
V
OH
0.5V
O/P HIGH
O/P LOW
Figure 13. Receiver Enable/Disable Timing
ADM4850ADM4857
Rev. 0 | Page 10 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
400
0
50
100
150
200
250
300
350
50
25
0
25
50
75
100
125
04931-014
TEMPERATURE (
C)
UNLOADE
D S
U
P
P
L
Y
CURRE
NT (
A)
ADM4853: DE = V
CC
ADM4853: DE = GND
ADM4850: DE = V
CC
ADM4850: DE = GND
Figure 14. Unloaded Supply Current vs. Temperature
04931-015
50
0
5
10
15
20
25
30
35
40
45
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
RECEIVER OUTPUT LOW VOLTAGE (V)
RE
CE
IV
E
R
OUTP
UT CURRE
NT (mA)
Figure 15. Output Current vs. Receiver Output Low Voltage
04931-016
5
0
5
10
15
20
3.5
4.0
4.5
5.0
5.5
RECEIVER OUTPUT HIGH VOLTAGE (V)
RE
CE
IV
E
R
OUTP
UT CURRE
NT (mA)
Figure 16. Output Current vs. Receiver Output High Voltage
04931-017
0.40
0.15
0.20
0.25
0.30
0.35
50
25
0
25
50
75
100
125
TEMPERATURE (
C)
OUTPUT LOW VOLTAGE (V)
Figure 17. Receiver Output Low Voltage vs. Temperature
04931-018
4.6
4.0
4.1
4.2
4.3
4.4
4.5
50
25
0
25
50
75
100
125
TEMPERATURE (
C)
OUTPUT HIGH VOLTAGE (
V
)
Figure 18. Receiver Output High Voltage Temperature
04931-019
90
0
10
20
30
40
50
60
70
80
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
DIFFERENTIAL OUTPUT VOLTAGE (V)
DRIV
E
R
OUTP
UT CURRE
NT (mA)
Figure 19. Driver Output Current vs. Differential Output Voltage
ADM4850ADM4857
Rev. 0 | Page 11 of 16
04931-020
120
100
80
60
40
20
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT VOLTAGE (V)
OUTP
UT CURRE
NT (mA)
Figure 20. Output Current vs. Driver Low Voltage
04931-021
10
30
50
70
90
110
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT VOLTAGE (V)
OUTP
UT CURRE
NT (mA)
Figure 21. Output Current vs. Driver Output High Voltage
450
0
50
100
150
200
250
300
350
400
50
25
0
25
50
75
100
125
04931-022
TEMPERATURE (
C)
P
R
OP
AGATION DE
LAY
(ns
)
ADM4855
ADM4853
Figure 22. Driver Propagation Delay vs. Temperature
800
700
600
500
400
300
200
100
0
50
25
0
25
50
75
100
125
04931-023
TEMPERATURE (
C)
P
R
OP
AGATION DE
LAY
(ns
)
ADM4855
ADM4853
Figure 23. Receiver Propagation Delay vs. Temperature
04931-024
CH1 1.00V
B
W
CH2 1.00V
B
W
M 400ns
CH3
2.00V
CH3
2.00V
B
W
CH4 5.00V
3
2
4
Figure 24. Driver/Receiver Propagation Delay (ADM4855, 500 kbps)
04931-025
CH1
2.00V
B
W
CH2 1.00V
M 50.0ns CH1 480mV
CH3 1.00V
B
W
CH4 5.00V
1
2
4
Figure 25. Driver/ Receiver Propagation Delay (ADM4855, 4 Mbps)
ADM4850ADM4857
Rev. 0 | Page 12 of 16
CIRCUIT DESCRIPTION
The ADM4850ADM4857 are high speed RS-485/RS-422
transceivers offering enhanced performance over industry-
standard devices. All devices in the family contain one driver
and one receiver, but offer a choice of performance options. The
devices feature true fail-safe operation, which means that a logic
high receiver output is guaranteed when the receiver inputs are
open-circuit or short-circuit, or when they are connected to a
terminated transmission line with all drivers disabled (see the
Fail-Safe Operation section).
SLEW-RATE CONTROL
The ADM4850/ADM4854 feature a controlled slew-rate driver
that minimizes electromagnetic interference (EMI) and reduces
reflections caused by incorrectly terminated cables, allowing
error-free data transmission rates up to 115 kbps. The ADM4851/
ADM4855 offer a higher limit on driver output slew rate, allowing
data transmission rates up to 500 kbps. The driver slew rates of
the ADM4852/ADM4856 and the ADM4853/ADM4857 are not
limited, offering data transmission rates up to 2.5 Mbps and
10 Mbps, respectively.
RECEIVER INPUT FILTERING
The receivers of all the devices incorporate input hysteresis. In
addition, the receivers of the 115 kbps ADM4850/ADM485 and
the 500 kbps ADM4851/ADM4855 incorporate input filtering.
This enhances noise immunity with differential signals that have
very slow rise and fall times. However, it causes the propagation
delay to increase by 20%.
HALF-/FULL-DUPLEX OPERATION
Half-duplex operation implies that the transceiver can transmit
and receive, but it can only do one of these at any given time.
However, with full-duplex operation, the transceiver can
transmit and receive simultaneously. The ADM4850ADM4853
are half-duplex devices in which the driver and receiver share
differential bus terminals. The ADM4854ADM4857 are full-
duplex devices, which have dedicated driver output and receiver
input pins. Figure 26
and Figure 27 show typical half- and full-
duplex topologies.
04931-026
RO
RE
DE
DI
D
R
A
B
MAXIMUM NUMBER OF TRANSCEIVERS ON BUS: 256
RO
RE
DE
DI
D
R
A
B
R
D
RO RE DE DI
A
B
R
D
RO RE DE
DI
A
B
ADM4850/ADM4851/
ADM4852/ADM4853
ADM4850/ADM4851/
ADM4852/ADM4853
ADM4850/ADM4851/
ADM4852/ADM4853
ADM4850/ADM4851/
ADM4852/ADM4853
Figure 26. Typical Half-Duplex RS-485 Network Topology
04931-027
GND
RO
DI
D
R
A
B
RO
DI
D
A
B
Z
Y
R
GND
V
DD
V
DD
Z
Y
ADM4854/ADM4855/
ADM4856/ADM4857
ADM4854/ADM4855/
ADM4856/ADM4857
Figure 27. Typical Full-Duplex Point-to-Point RS-485 Network Topology
ADM4850ADM4857
Rev. 0 | Page 13 of 16
HIGH RECEIVER INPUT IMPEDANCE
The input impedance of the ADM485x receivers is 96 k,
which is 8 times higher than the standard RS-485 unit load of
12 k. This 96 k impedance, enables a standard driver to
drive 32 unit loads or be connected to 256 ADM485x receivers.
An RS-485 bus, driven by a single standard driver, can be
connected to a combination of ADM485x and standard unit
load receivers, up to an equivalent of 32 standard unit loads.
THREE-STATE BUS CONNECTION
The half-duplex parts have a driver enable (DE) pin that enables
the driver outputs when taken high, or puts the driver outputs
into a high impedance state when taken low. Similarly, the half-
duplex devices have an active-low receiver enable (RE) pin.
Taking this pin low enables the receiver, while taking it high
puts the receiver outputs into a high impedance state. This
allows several driver outputs to be connected to an RS-485 bus.
Note that only one driver should be enabled at a time, while
many receivers can be enabled.
SHUTDOWN MODE
The ADM4850ADM4853 have a low power shutdown mode,
which is enabled by taking RE high and DE low. If shutdown
mode is not used, the fact that DE is active high and RE is active
low offers a convenient way of switching the device between
transmit and receive by tying DE and RE together.
The devices are guaranteed not to enter shutdown mode if DE
and RE are driven in this way. If DE is low and RE is high for
less than 50 ns, the device does not enter shutdown mode. If DE
is low and RE is high for less than 3000 ns, the device is
guaranteed to enter shutdown mode.
FAIL-SAFE OPERATION
The ADM4850ADM4857 offer true fail-safe operation while
remaining fully compliant with the 200 mV EIA/TIA-485
standard. A logic-high receiver output is generated when the
receiver inputs are shorted together or open-circuit, or when
they are connected to a terminated transmission line with all
drivers disabled. This is done by setting the receiver threshold
between -30 mV and -200 mV. If the differential receiver input
voltage (A-B) is greater than or equal to -30 mV, RO is logic
high. If A-B is less than or equal to -200 mV, RO is logic low. In
the case of a terminated bus with all transmitters disabled, the
receiver's differential input voltage is pulled to 0 V by the
ADM485x's internal circuitry, which results in a logic high with
30 mV minimum noise margin.
CURRENT LIMIT AND THERMAL SHUTDOWN
The ADM485x incorporates two protection mechanisms to
guard the drivers against short circuits, bus contention, or other
fault conditions. The first is a current-limiting output stage,
which protects the driver against short circuits over the entire
common-mode voltage range by limiting the output current to
approximately 70 mA. Under extreme fault conditions where
the current limit is not effective, a thermal shutdown circuit
puts the driver outputs into a high impedance state if the die
temperature exceeds 150C, and does not turn them back on
until the temperature falls to 130C.
ADM4850ADM4857
Rev. 0 | Page 14 of 16
OUTLINE DIMENSIONS
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)
45
8
0
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8
5
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
Figure 28. 8-Lead Standard Small Outline Package [SOIC]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
1
EXPOSED
PAD
(BOTTOM VIEW)
0.50
BSC
0.60 MAX
PIN 1
INDICATOR
1.50
REF
0.50
0.40
0.30
0.25
MIN
0.45
2.75
BSC SQ
TOP
VIEW
12 MAX
0.80 MAX
0.65TYP
SEATING
PLANE
PIN 1
INDICATOR
0.90
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
1.90
1.75
1.60
4
1.60
1.45
1.30
3.00
BSC SQ
5
8
Figure 29. 8-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-8-2)
Dimensions shown in millimeters
ADM4850ADM4857
Rev. 0 | Page 15 of 16
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Type
Branding
ADM4850ACP-REEL
-40C to +85C
8-Lead Lead Frame Chip Scale Package
CP-8-2
M0R
ADM4850ACP-REEL7
-40C to +85C
8-Lead Lead Frame Chip Scale Package
CP-8-2
M0R
ADM4850AR
-40C to +85C
8-Lead Standard Small Outline Package
R-8
ADM4850AR-REEL
-40C to +85C
8-Lead Standard Small Outline Package
R-8
ADM4850AR-REEL7
-40C to +85C
8-Lead Standard Small Outline Package
R-8
ADM4851ACP-REEL
-40C to +85C
8-Lead Lead Frame Chip Scale Package
CP-8-2
M0S
ADM4851ACP-REEL7
-40C to +85C
8-Lead Lead Frame Chip Scale Package
CP-8-2
M0S
ADM4851AR
-40C to +85C
8-Lead Standard Small Outline Package
R-8
ADM4851AR-REEL
-40C to +85C
8-Lead Standard Small Outline Package
R-8
ADM4851AR-REEL7
-40C to +85C
8-Lead Standard Small Outline Package
R-8
ADM4852ACP-REEL
-40C to +85C
8-Lead Lead Frame Chip Scale Package
CP-8-2
M0T
ADM4852ACP-REEL7
-40C to +85C
8-Lead Lead Frame Chip Scale Package
CP-8-2
M0T
ADM4852AR
-40C to +85C
8-Lead Standard Small Outline Package
R-8
ADM4852AR-REEL
-40C to +85C
8-Lead Standard Small Outline Package
R-8
ADM4852AR-REEL7
-40C to +85C
8-Lead Standard Small Outline Package
R-8
ADM4853ACP-REEL
-40C to +85C
8-Lead Lead Frame Chip Scale Package
CP-8-2
M0U
ADM4853ACP-REEL7
-40C to +85C
8-Lead Lead Frame Chip Scale Package
CP-8-2
M0U
ADM4853AR
-40C to +85C
8-Lead Standard Small Outline Package
R-8
ADM4853AR-REEL
-40C to +85C
8-Lead Standard Small Outline Package
R-8
ADM4853AR-REEL7
-40C to +85C
8-Lead Standard Small Outline Package
R-8
ADM4854AR
-40C to +85C
8-Lead Standard Small Outline Package
R-8
ADM4855AR
-40C to +85C
8-Lead Standard Small Outline Package
R-8
ADM4855AR-REEL
-40C to +85C
8-Lead Standard Small Outline Package
R-8
ADM4855AR-REEL7
-40C to +85C
8-Lead Standard Small Outline Package
R-8
ADM4856AR
-40C to +85C
8-Lead Standard Small Outline Package
R-8
ADM4856AR-REEL
-40C to +85C
8-Lead Standard Small Outline Package
R-8
ADM4856AR-REEL7
-40C to +85C
8-Lead Standard Small Outline Package
R-8
ADM4857AR
-40C to +85C
8-Lead Standard Small Outline Package
R-8
ADM4857AR-REEL
-40C to +85C
8-Lead Standard Small Outline Package
R-8
ADM4857AR-REEL7
-40C to +85C
8-Lead Standard Small Outline Package
R-8
ADM4850ADM4857
Rev. 0 | Page 16 of 16
NOTES
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04931010/04(0)
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