FUNCTIONAL BLOCK DIAGRAMS
1.3V
V
OUT
V
BATT
V
CC
WATCHDOG
INPUT (WDI)
POWER FAIL
INPUT (PFI)
POWER FAIL
OUTPUT (PFO)
RESET
WATCHDOG
TIMER
BATT ON
OSC IN
OSC SEL
WATCHDOG
OUTPUT (WDO)
RESET
LOW LINE
LL
IN
RESET GENERATOR
TIMEBASE FOR RESET
AND WATCHDOG
WATCHDOG
TRANSITION DETECTOR
ADM696
1.3V
CE
OUT
WATCHDOG
INPUT (WDI)
POWER FAIL
INPUT (PFI)
POWER FAIL
OUTPUT (PFO)
RESET
WATCHDOG
TIMER
OSC IN
OSC SEL
WATCHDOG
OUTPUT (WDO)
RESET
LOW LINE
LL
IN
RESET GENERATOR
TIMEBASE FOR RESET
AND WATCHDOG
WATCHDOG
TRANSITION DETECTOR
ADM697
CE
IN
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Microprocessor
Supervisory Circuits
ADM696/ADM697
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
FEATURES
Superior Upgrade for MAX696/MAX697
Specified Over Temperature
Adjustable Low Line Voltage Monitor
Power OK/Reset Time Delay
Reset Assertion Down to 1 V V
CC
Watchdog Timer--100 ms, 1.6 s, or Adjustable
Low Switch On Resistance
1.5 Normal, 20 in Backup
600 nA Standby Current
Automatic Battery Backup Switching (ADM696)
Fast On-Board Gating of Chip Enable Signals (ADM697)
Voltage Monitor for Power Fail or Low Battery Warning
APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Automotive Systems
Critical P Power Monitoring
GENERAL DESCRIPTION
The ADM696/ADM697 supervisory circuits offer complete
single chip solutions for power supply monitoring and battery
control functions in microprocessor systems. These functions
include
P reset, backup-battery switchover, watchdog timer,
CMOS RAM write protection, and power failure warning.
The ADM696/ADM697 are available in 16-pin DIP and small
outline packages and provide the following functions:
1. Power-On Reset output during power-up, power-down and
brownout conditions. The RESET voltage threshold is
adjustable using an external voltage divider. The RESET
output remains operational with V
CC
as low as 1 V.
2. A Reset pulse if the optional watchdog timer has not been
toggled within specified time.
3. Separate watchdog time-out and low line status outputs.
4. Adjustable reset and watchdog timeout periods.
5. A 1.3 V threshold detector for power fail warning, low bat-
tery detection, or to monitor a power supply other than V
CC
.
6. Battery backup switching for CMOS RAM, CMOS micro-
processor or other low power logic (ADM696).
7. Write protection of CMOS RAM or EEPROM (ADM697).
The ADM696/ADM697 is fabricated using an advanced epitaxial
CMOS process combining low power consumption (5 mW),
extremely fast Chip Enable gating (5 ns) and high reliability.
RESET
assertion is guaranteed with V
CC
as low as 1 V. In
addition, the power switching circuitry is designed for minimal
voltage drop thereby permitting increased output current drive
of up to 100 mA without the need for an external pass transistor.
ADM696/ADM697SPECIFICATIONS
P
arameter
Min
Typ
Max
Units
Test Conditions/Comments
V
CC
Operating Voltage Range
3.0
5.5
V
V
BATT
Operating Voltage Range
2.0
V
CC
0 3
V
BATTERY BACKUP SWITCHING (ADM696)
V
OUT
Output Voltage
V
CC
0.05
V
CC
0.025
V
I
OUT
= 1 mA
V
CC
0.5
V
CC
0.25
V
I
OUT
100 mA
V
OUT
in Battery Backup Mode
V
BATT
0.05
V
BATT
0.02
V
I
OUT
= 250
A, V
CC
< V
BATT
0.2 V
Supply Current (Excludes I
OUT
)
1
1.95
mA
I
OUT
= 100 mA
Supply Current in Battery Backup Mode
0.6
1
A
V
CC
= 0 V, V
BATT
= 2.8 V
Battery Standby Current
5.5 V > V
CC
> V
BATT
+ 0.2 V
(+ = Discharge, = Charge)
0.1
+0.02
A
T
A
= +25
C
1
+0.02
A
Battery Switchover Threshold
70
mV
Power-Up
V
CC
V
BATT
50
mV
Power-Down
Battery Switchover Hysteresis
20
mV
BATT ON Output Voltage
0.4
V
I
SINK
= 1.6 mA
BATT ON Output Short Circuit Current
7
mA
BATT ON = V
OUT
= 2.4 V Sink Current
0.5
1
25
A
BATT ON = V
OUT
, V
CC
= 0 V, Source Current
RESET AND WATCHDOG TIMER
Low Line Threshold (LL
IN
)
1.25
1.3
1.35
V
V
CC
= +5 V, +3 V
Reset Timeout Delay
35
50
70
ms
OSC SEL = HIGH, V
CC
= 5 V, T
A
= +25
C
Watchdog Timeout Period, Internal Oscillator
1.0
1.6
2.25
s
Long Period, V
CC
= 5 V, T
A
= +25
C
70
100
140
ms
Short Period, V
CC
= 5 V, T
A
= +25
C
Watchdog Timeout Period, External Clock
4032
4097
Cycles
Long Period
960
1025
Cycles
Short Period
Minimum WDI Input Pulse Width
50
ns
V
IL
= 0.4, V
IH
= 3.5 V, V
CC
= 5 V
RESET
Output Voltage @ V
CC
= +1 V
4
200
mV
I
SINK
= 10
A, V
CC
= 1 V
RESET, RESET Output Voltage
0.4
V
I
SINK
= 400
A, V
CC
= 2 V, V
BATT
= 0 V
0.4
V
I
SINK
= 1.6 mA, 3 V < V
CC
< 5.5 V
3.5
V
I
SOURCE
= 1
A, V
CC
= 5 V
LOW LINE
, WDO Output Voltage
0.4
V
I
SINK
= 1.6 mA,
3.5
V
I
SOURCE
= 1
A, V
CC
= 5 V
Output Short Circuit Source Current
1
3
25
A
WDI Input Threshold
V
CC
= 5 V
1
Logic Low
0.8
V
Logic High
3.5
V
WDI Input Current
20
50
A
WD1 = V
OUT
, (V
CC
) T
A
= +25
C
50
15
A
WD1 = 0 V, T
A
= +25
C
POWER FAIL DETECTOR
PFI Input Threshold
1.2
1.3
1.4
V
V
CC
= +3 V, +5 V
PFILL
IN
Threshold Difference
50
15
+50
mV
V
CC
= +3 V, +5 V
PFI Input Current
25
0.01
+25
nA
LL
IN
Input Current
50
0.01
+50
nA
PFO
Output Voltage
0.4
V
I
SINK
= 1.6 mA
3.5
V
I
SOURCE
= 1
A, V
CC
= 5 V
PFO
Short Circuit Source Current
1
3
25
A
PFI = Low, PFO = 0 V
CHIP ENABLE GATING (ADM697)
CE
IN
Threshold
0.8
V
V
IL
3.0
V
V
IH
, V
CC
= 5 V
CE
IN
Pullup Current
3
A
CE
OUT
Output Voltage
0.4
V
I
SINK
= 1.6 mA
V
CC
0.5
V
I
SOURCE
= 800
A
CE
Propagation Delay
5
25
ns
OSCILLATOR
OSC IN Input Current
2
A
OSC SEL Input Pullup Current
5
A
OSC IN Frequency Range
0
250
kHz
OSC SEL = 0 V
OSC IN Frequency with Ext. Capacitor
4
kHz
OSC SEL = 0 V, C
OSC
= 47 pF
NOTE
1
WDI is a three-level input which is internally biased to 38% of V
CC
and has an input impedance of approximately 125 k
.
Specifications subject to change without notice.
REV. 0
2
(V
CC
= Full Operating Range, V
BATT
= +2.8 V, T
A
= T
MIN
to T
MAX
unless otherwise noted.)
ADM696/ADM697
REV. 0
3
ORDERING GUIDE
Model
Temperature Range
Package Option
ADM696AN
40
C to +85
C
N-16
ADM696AR
40
C to +85
C
R-16
ADM696AQ
40
C to +85
C
Q-16
ADM696SQ
55
C to +125
C
Q-16
ADM697AN
40
C to +85
C
N-16
ADM697AR
40
C to +85
C
R-16
ADM697AQ
40
C to +85
C
Q-16
ADM697SQ
55
C to +125
C
Q-16
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25
C unless otherwise noted)
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +6 V
V
BATT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +6 V
All Other Inputs . . . . . . . . . . . . . . . . . . 0.3 V to V
OUT
+ 0.5 V
Input Current
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
V
BATT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . . 600 mW
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135
C/W
Power Dissipation, Q-16 DIP . . . . . . . . . . . . . . . . . . . 600 mW
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 100
C/W
Power Dissipation, R-16 SOIC . . . . . . . . . . . . . . . . . . 600 mW
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110
C/W
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . . 40
C to +85
C
Extended (S Version) . . . . . . . . . . . . . . . . . 55
C to +125
C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300
C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220
C
Storage Temperature Range . . . . . . . . . . . . . 65
C to +150
C
*Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum ratings for extended periods of time may affect device reliability.
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADM696/ADM697 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TOP VIEW
(Not to Scale)
ADM696
GND
V
BATT
V
OUT
PFI
PFO
WDO
V
CC
RESET
BATT ON
LOW LINE
OSC IN
OSC SEL
RESET
LL
IN
NC
WDI
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TOP VIEW
(Not to Scale)
ADM697
LL
IN
TEST
NC
PFI
PFO
WDO
V
CC
RESET
GND
LOW LINE
OSC IN
OSC SEL
RESET
CE
IN
CE
OUT
WDI
ADM696/ADM697
REV. 0
4
PIN FUNCTION DESCRIPTION
Pin No.
Mnemonic
ADM696
ADM697
Function
V
CC
3
3
Power Supply Input +3 V to +5 V.
V
BATT
1
--
Backup Battery Input. Connect to Ground if a backup battery is not used.
V
OUT
2
--
Output Voltage, V
CC
or V
BATT
is internally switched to V
OUT
depending on which is at the
highest potential. V
OUT
can supply up to 100 mA to power CMOS RAM. Connect V
OUT
to
V
CC
if V
OUT
and V
BATT
are not used.
GND
4
5
0 V. Ground reference for all signals.
RESET
15
15
Logic Output. RESET goes low whenever LL
IN
falls below 1.3 V or when V
CC
falls below
the V
BATT
input voltage. RESET remains low for 50 ms after LL
IN
goes above 1.3 V,
RESET
also goes low for 50 ms if the watchdog timer is enabled but not serviced within its
timeout period. The RESET pulse width can be adjusted as shown in Table I.
WDI
11
11
Watchdog Input, WDI is a three level input. If WDI remains either high or low for longer
than the watchdog timeout period, RESET pulses low and WDO goes low. The timer resets
with each transition at the WDI input. The watchdog timer is disabled when WDI is left
floating or is driven to midsupply.
PFI
9
9
Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is
less than 1.3 V, PFO goes low. Connect PFI to GND or V
OUT
when not used. See Figure 1.
PFO
10
10
Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI
is less than 1.3 V. The comparator is turned off and PFO goes low when V
CC
is below
V
BATT
.
CE
IN
--
13
Logic Input. The input to the CE gating circuit. Connect to GND or V
OUT
if not used.
CE
OUT
--
12
Logic Output. CE
OUT
is a gated version of the CE
IN
signal. CE
OUT
tracks CE
IN
when LL
IN
is above 1.3 V. If LL
IN
is below 1.3 V, CE
OUT
is forced high.
BATT ON
5
--
Logic Output. BATT ON goes high when V
OUT
is internally switched to the V
BATT
input.
It goes low when V
OUT
is internally switched to V
CC
. The output typically sinks 7 mA and
can directly drive the base of an external PNP transistor to increase the output current above
the 100 mA rating of V
OUT
.
LOW LINE
6
6
Logic Output. LOW LINE goes low when LL
IN
falls below 1.3 V. It returns high as soon as
LL
IN
rises above 1.3 V.
RESET
16
16
Logic Output. RESET is an active high output. It is the inverse of RESET.
OSC SEL
8
8
Logic Oscillator Select Input. When OSC SEL is unconnected or driven high, the internal
oscillator sets the reset time delay and watchdog time-out period. When OSC SEL is low,
the external oscillator input, OSC IN, is enabled. OSC SEL has a 3
A internal pullup. See
Table I and Figure 4.
OSC IN
7
7
Logic Oscillator Input. When OSC SEL is low, OSC IN can be driven by an external clock
to adjust both the reset delay and the watchdog time-out period. The timing can also be
adjusted by connecting an external capacitor to this pin. See Table I and Figure 4. When
OSC SEL is high or floating, OSC IN selects between fast and slow watchdog time-out periods.
WDO
14
14
Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low
for longer than the watchdog time-out period. WDO is set high by the next transition at
WDI. If WDI is unconnected or at midsupply, WDO remains high. WDO also goes high
when LOW LINE goes low.
NC
12
2
No Connect. It should be left open.
LL
IN
13
4
Voltage Sensing Input. The voltage on the low line input, LL
IN
, is compared with a 1.3 V
reference voltage. This input is normally used to monitor the power supply voltage. The
output of the comparator generates a LOW LINE output signal. It also generates a
RESET/RESET output.
TEST
--
1
This is a special test pin using during device manufacture. It should be connected to GND.
ADM696/ADM697
REV. 0
5
Low Line RESET OUTPUT
RESET
is an active low output which provides a RESET signal
to the microprocessor whenever the Low Line Input (LL
IN
) is
below 1.3 V. The LL
IN
input is normally used to monitor the
power supply voltage. An internal timer holds RESET low for
50 ms after the voltage on LL
IN
rises above 1.3 V. This is in-
tended as a power-on RESET signal for the processor. It allows
time for the power supply and microprocessor to stabilize. On
power-down, the RESET output remains low with V
CC
as low
as 1 V. This ensures that the microprocessor is held in a stable
shutdown condition.
The LL
IN
comparator has approximately 12 mV of hysteresis
for enhanced noise immunity.
In addition to RESET, an active high RESET output is also
available. This is the complement of RESET and is useful for
processors requiring an active high RESET.
t
1
t
1
= RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2V1
V2
V2
V1
V1
t
1
LL
IN
LOW LINE
RESET
Figure 2. Power-Fail Reset Timing
Watchdog Timer RESET
The watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within
the selected timeout period, a RESET pulse is generated. The
ADM696/ADM697 may be configured for either a fixed
"short" 100 ms or a "long" 1.6 second timeout period or for an
adjustable timeout period. If the "short" period is selected some
systems may be unable to service the watchdog timer immedi-
ately after a reset, so a "long" timeout is automatically initiated
directly after a reset is issued. The watchdog timer is restarted
at the end of Reset, whether the Reset was caused by lack of ac-
tivity on WDI or by LL
IN
falling below the reset threshold.
The normal (short) timeout period becomes effective following
the first transition of WDI after RESET has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to high transition on the WDI pin
must occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be is-
sued after each timeout period (1.6 s). The watchdog monitor
can be deactivated by floating the Watchdog Input (WDI) or by
connecting it to midsupply.
CIRCUIT INFORMATION
Battery-Switchover Section (ADM696)
The battery switchover circuit compares V
CC
to the V
BATT
input, and connects V
OUT
to whichever is higher. Switchover
occurs when V
CC
is 50 mV higher than V
BATT
as V
CC
falls, and
when V
CC
is 70 mV greater than V
BATT
as V
CC
rises. This
20 mV of hysteresis prevents repeated rapid switching if V
CC
falls very slowly or remains nearly equal to the battery voltage.
During normal operation with V
CC
higher than V
BATT
, V
CC
is
internally switched to V
OUT
via an internal PMOS transistor
switch. This switch has a typical on resistance of 1.5
and can
supply up to 100 mA at the V
OUT
terminal. V
OUT
is normally
used to drive a RAM memory bank which may require instanta-
neous currents of greater than 100 mA. If this is the case, then
a bypass capacitor should be connected to V
OUT
. The capacitor
will provide the peak current transients to the RAM. A capaci-
tance value of 0.1
F or greater may be used.
If the continuous output current requirement at V
OUT
exceeds
100 mA or if a lower V
CC
V
OUT
voltage differential is desired,
an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output can directly
drive the base of the external transistor.
A 20
MOSFET switch connects the V
BATT
input to V
OUT
during battery backup. This MOSFET has very low input-to-
output differential (dropout voltage) at the low current levels
required for battery backup of CMOS RAM or other low power
CMOS circuitry. The supply current in battery backup is typi-
cally 0.6
A.
The ADM696 operates with battery voltages from 2.0 V to V
CC
0.3 V). High value capacitors, either standard electrolytic or
the farad-size double layer capacitors, can also be used for short-
term memory backup. A small charging current of typically
10 nA (0.1
A max) flows out of the V
BATT
terminal. This cur-
rent is useful for maintaining rechargeable batteries in a fully
charged condition. This extends the life of the backup battery
by compensating for its self discharge current. Also note that
this current poses no problem when lithium batteries are used
for backup since the maximum charging current (0.1
A) is safe
for even the smallest lithium cells.
If the battery-switchover section is not used, V
BATT
should be
connected to GND and V
OUT
should be connected to V
CC
.
V
BATT
V
CC
BATT ON
(ADM691, ADM693,
ADM695, ADM696)
V
OUT
700
mV
GATE DRIVE
100
mV
INTERNAL
SHUT DOWN SIGNAL
WHEN
V
BATT
> (V
CC
+ 0.7V)
Figure 1. Battery Switchover Schematic
ADM696/ADM697
REV. 0
6
Table I. ADM696, ADM697 Reset Pulse Width and Watchdog Timeout Selections
Watchdog Timeout Period
Reset Active Period
OSC SEL
OSC IN
Normal
Immediately After Reset
Low
External Clock Input
1024 CLKS
4096 CLKS
512 CLKS
Low
External Capacitor
400 ms
C/47 pF
1.6 s
C/47 pF
200 ms
C/47 pF
Floating or High
Low
100 ms
1.6 s
50 ms
Floating or High
Floating or High
1.6 s
1.6 s
50 ms
NOTE
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: F
OSC
(Hz) = 184,000/C (pF).
t
2
RESET
WDO
WDI
t
1
= RESET TIME
t
2
= NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD
t
3
= WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET
t
1
t
1
t
1
t
3
Figure 3. Watchdog Timeout Period and Reset Active Time
The watchdog timeout period defaults to 1.6 s and the reset
pulse width defaults to 50 ms but these times to be adjusted as
shown in Table I. Figure 4 shows the various oscillator configu-
rations which can be used to adjust the reset pulse width and
watchdog timeout period.
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. In either case, immedi-
ately after a reset the timeout period is 1.6 s. This gives the mi-
croprocessor time to reinitialize the system. If OSC IN is low,
then the 100 ms watchdog period becomes effective after the
first transition of WDI. The software should be written such
that the I/O port driving WDI is left in its power-up reset state
until the initialization routines are completed and the micropro-
cessor is able to toggle WDI at the minimum watchdog timeout
period of 70 ms.
OSC IN
OSC SEL
ADM69x
CLOCK
0 TO 250kHz
8
7
Figure 4a. External Clock Source
OSC IN
OSC SEL
ADM69x
8
7
C
OSC
Figure 4b. External Capacitor
OSC IN
OSC SEL
ADM69x
8
7
NC
NC
Figure 4c. Internal Oscillator (1.6 s Watchdog)
OSC IN
OSC SEL
ADM69x
8
7
NC
Figure 4d. Internal Oscillator (100 ms Watchdog)
Watchdog Output (WDO)
The Watchdog Output WDO provides a status output which
goes low if the watchdog timer "times out" and remains low
until set high by the next transition on the watchdog input.
WDO
is also set high when LL
IN
goes below the reset threshold.
ADM696/ADM697
REV. 0
7
Fail Output (PFO) goes low when the voltage at PFI is less than
1.3 V. Typically PFI is driven by an external voltage divider
which senses either the unregulated dc input to the system's 5 V
regulator or the regulated 5 V output. The voltage divider ratio
can be chosen such that the voltage at PFI falls below 1.3 V
several milliseconds before the +5 V power supply falls below
the reset threshold. PFO is normally used to interrupt the
microprocessor so that data can be stored in RAM and the shut-
down procedure executed before power is lost.
ADM69x
POWER
FAIL
INPUT
R2
INPUT
POWER
1.3V
PFO
POWER
FAIL
OUTPUT
R1
Figure 7. Power Fail Comparator
Table II. Input and Output Status In Battery Backup Mode
Signal
Status
V
OUT
(ADM696) V
OUT
is connected to V
BATT
via an
internal PMOS switch.
RESET
Logic low.
RESET
Logic high. The open circuit output voltage is
equal to V
OUT
.
LOW LINE
Logic low.
BATT ON
(ADM696) Logic high. The open circuit voltage
is equal to V
OUT
.
WDI
WDI is ignored. It is internally disconnected
from the internal pullup resistor and does not
source or sink current as long as its input voltage
is between GND and V
OUT
. The input voltage
does not affect supply current.
WDO
Logic high. The open circuit voltage is equal to
V
OUT
.
PFI
The Power Fail Comparator is turned off and
has no effect on the Power Fail Output.
PFO
Logic low.
CE
IN
CE
IN
is ignored. It is internally disconnected
from its internal pullup and does not source or
sink current as long as its input voltage is be-
tween GND and V
OUT
. The input voltage does
not affect supply current.
CE
OUT
Logic high. The open circuit voltage is equal to
V
OUT
.
OSC IN
OSC IN is ignored.
OSC SEL
OSC SEL is ignored.
CE Gating and RAM Write Protection (ADM697)
The ADM697 contains memory protection circuitry which
ensures the integrity of data in memory by preventing write
operations when LL
IN
is below the threshold voltage. When
LL
IN
is greater than 1.3 V, CE
OUT
is a buffered replica of CE
IN
,
with a 5 ns propagation delay. When LL
IN
falls below the 1.3 V
threshold, an internal gate forces CE
OUT
high, independent of
CE
IN
.
CE
OUT
typically drives the CE, CS, or Write input of battery
backed up CMOS RAM. This ensures the integrity of the data
in memory by preventing write operations when V
CC
is at an in-
valid level.
If the 5 ns typical propagation delay of CE
OUT
is excessive, con-
nect CE
IN
to GND and use the resulting CE
OUT
to control a
high speed external logic gate.
ADM697
CE
OUT
CE
IN
LL
IN
LOW = 0
LL
IN
OK = 1
Figure 5. Chip Enable Gating
t
1
t
1
= RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2V1
V2
V2
V1
V1
t
1
LL
IN
LOW LINE
RESET
CE
IN
CE
OUT
Figure 6. Chip Enable Timing
Power Fail Warning Comparator
An additional comparator is provided for early warning of fail-
ure in the microprocessor's power supply. The Power Fail Input
(PFI) is compared to an internal +1.3 V reference. The Power
ADM696/ADM697Typical Performance Curves
REV. 0
8
5.00
4.80
0
100
4.95
4.85
20
4.90
80
60
40
V
CC
= +5V
T
A
= +25C
SLOPE = 1.5
V
OUT
V
I
OUT
mA
Figure 8. V
OUT
vs. I
OUT
Normal Operation
2.80
2.76
0
1000
2.79
2.77
200
2.78
800
600
400
I
OUT
A
V
OUT
V
SLOPE = 20
V
CC
= 0V
V
BATT
= +2.8V
T
A
= +25
C
Figure 9. V
OUT
vs. Battery Backup
1.303
1.299
20
120
1.302
1.300
40
1.301
100
80
60
PFI INPUT THRESHOLD V
TEMPERATURE
C
Figure 10. PFI Input Threshold vs. Temperature
53
49
20
120
52
50
40
51
100
80
60
V
CC
= +5V
TEMPERATURE
C
RESET ACTIVE TIME ms
Figure 11. RESET Active Time vs. Temperature
10
90
100
0%
1V
A4
500ms
3.36 V
1V
Figure 12. RESET Output Voltage vs. Supply Voltage
5.5
3.0
2.0
10
100
10000
1000
4.5
2.5
3.5
4.0
5.0
TIME DELAY ms
V
CC
Volts
T
A
= +25
C
Figure 13. RESET Timeout Delay vs. V
CC
ADM696/ADM697
REV. 0
9
APPLICATIONS INFORMATION
Increasing the Drive Current (ADM696)
If the continuous output current requirements at V
OUT
exceeds
100 mA or if a lower V
CC
V
OUT
voltage differential is desired,
an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output (ADM696)
can directly drive the base of the external transistor.
V
OUT
V
CC
BATTERY
+5V
INPUT
POWER
0.1F
BATT
ON
V
BATT
PNP TRANSISTOR
ADM696
0.1F
Figure 14. Increasing the Drive Current
Using a Rechargeable Battery for Backup (ADM696)
If a capacitor or a rechargeable battery is used for backup, then
the charging resistor should be connected to V
OUT
since this
eliminates the discharge path that would exist during power-
down if the resistor is connected to V
CC
.
V
OUT
V
CC
RECHARGABLE
BATTERY
+5V
INPUT
POWER
0.1F
0.1F
V
BATT
ADM696
R
I =
V
OUT
V
BATT
R
Figure 15. Rechargeable Battery
Adding Hysteresis to the Power Fail Comparator
For increased noise immunity, hysteresis may be added to the
power fail comparator. Since the comparator circuit is nonin-
verting, hysteresis can be added simply by connecting a resistor
between the PFO output and the PFI input as shown in Fig-
ure 16. When PFO is low, resistor R3 sinks current from the
summing junction at the PFI pin. When PFO is high, the series
combination of R3 and R4 source current into the PFI summing
junction. This results in differing trip levels for the comparator.
Alternate Watchdog Input Drive Circuits
The watchdog feature can be enabled and disabled under pro-
gram control by driving WDI with a 3-state buffer (Figure 17a).
When three-stated, the WDI input will float thereby disabling
the watchdog timer.
This circuit is not entirely foolproof, and it is possible that a
software fault could erroneously 3-state the buffer. This would
then prevent the ADM69x from detecting that the microproces-
sor is no longer operating correctly. In most cases a better
ADM69x
R2
1.3V
PFO
R1
7805
R4
R3
+7V TO +15V
INPUT
POWER
+5V
PFI
V
CC
TO
P NMI
V
H
= 1.3V
(
1+ +
)
V
L
= 1.3V
(
1+
)
ASSUMING R
4
< <
R
3
THEN
HYSTERESIS V
H
V
L
= 5V
(
)
R
1
R
2
R
1
R
3
R
1
R
2
R
1
R
2
R
1
(5V 1.3V)
1.3V (R
3 +
R
4
)
Figure 16. Adding Hysteresis to the Power Fail Comparator
method is to extend the watchdog period rather than disabling
the watchdog. This may be done under program control using
the circuit shown in Figure 17b. When the control input is high,
the OSC SEL pin is low and the watchdog timeout is set by the
external capacitor. A 0.01
F capacitor sets a watchdog timeout
delay of 100 s. When the control input is low, the OSC SEL pin
is driven high, selecting the internal oscillator. The 100 ms or
the 1.6 s period is chosen, depending on which diode in Fig-
ure 17b is used. With D1 inserted, the internal timeout is set at
100 ms while with D2 inserted the timeout is set at 1.6 s.
WDI
ADM69x
WATCHDOG
STROBE
CONTROL
INPUT
Figure 17a. Programming the Watchdog Input
OSC IN
OSC SEL
ADM69x
CONTROL
INPUT*
D1
D2
*LOW = INTERNAL TIMEOUT
HIGH = EXTERNAL TIMEOUT
Figure 17b. Programming the Watchdog Input
ADM696/ADM697
REV. 0
10
Replacing the Back-Up Battery
When changing the back-up battery with system power on, spu-
rious resets can occur when the battery is removed. This occurs
because the leakage current flowing out of the V
BATT
pin will
charge up the stray capacitance. If the voltage on V
BATT
reaches
within 50 mV of V
CC
, a reset pulse is generated.
If spurious resets during battery replacement are acceptable,
then no action is required. If not, then one of the following solu-
tions should be considered:
1. A capacitor from V
BATT
to GND. This gives time while the
capacitor is charging up to change the battery. The leakage
current will charge up the external capacitor towards the
V
CC
level. The time taken is related to the charging current,
the size of external capacitor and the voltage differential be-
tween the capacitor and the charging voltage supply.
t = C
EXT
V
DIFF
/I
The maximum leakage (charging) current is 1
A over tem-
perature and V
DIFF
= V
CC
V
BATT
. Therefore, the capacitor
size should be chosen such that sufficient time is available to
make the battery replacement.
C
EXT
= T
REQD
(1
A/(V
CC
V
BATT
))
If a replacement time of 5 s is allowed and assuming a V
CC
of 4.5 V and a V
BATT
of 3 V,
C
EXT
= 3.33
F
2. A resistor from V
BATT
to GND. This will prevent the voltage
on V
BATT
from rising to within 50 mV of V
CC
during battery
replacement.
R = (V
CC
50 mV)/1
A
Note that the resistor will discharge the battery slightly.
With a V
CC
supply of 4.5 V, a suitable resistor is 4.3 M
.
With a 3 V battery, this will draw around 700 nA. This will
be negligible in most cases.
TYPICAL APPLICATIONS
ADM696
Figure 18 shows the ADM696 in a typical power monitoring,
battery backup application. V
OUT
powers the CMOS RAM.
Under normal operating conditions with V
CC
present, V
OUT
is
internally connected to V
CC
. If a power failure occurs, V
CC
will
decay and V
OUT
will be switched to V
BATT
, thereby maintaining
power for the CMOS RAM.
Power Fail RESET
The V
CC
power supply is also monitored by the Low Line In-
put, LL
IN
. A RESET pulse is generated when LL
IN
falls below
1.3 V. RESET will remain low for 50 ms after LL
IN
returns
above 1.3 V. This allows for a power-on reset and prevents re-
peated toggling of RESET if the V
CC
power supply is unstable.
Resistors R3 and R4 should be chosen to give the desired V
CC
reset threshold.
Watchdog Timer
The Watchdog Timer Input (WDI) monitors an I/O line from
the
P system. This line must be toggled once every 1.6 s to
verify correct software execution. Failure to toggle the line indi-
cates that the
P system is not correctly executing its program
and may be tied up in an endless loop. If this happens, a reset
pulse is generated to initialize the processor.
If the watchdog timer is not needed the WDI input should be
left floating.
Power Fail Detector
The Power Fail Input, PFI, monitors the input power supply via
a resistive divider network R1 and R2. This input is intended as
an early warning power fail input. The voltage on the PFI input
is compared with a precision 1.3 V internal reference. If the in-
put voltage drops below 1.3 V, a power fail output (PFO) signal
is generated. This warns of an impending power failure and may
be used to interrupt the processor so that the system may be
shut down in an orderly fashion. The resistors in the sensing
network are ratioed to give the desired power fail threshold volt-
age V
T
. The threshold should be set at a higher voltage than the
RESET threshold so that there is sufficient time available to
complete the shutdown procedure before the processor is
RESET and power is lost.
ADM696
R2
R1
PFO
+5V
V
CC
CMOS RAM
POWER
I/O LINE
P NMI
P RESET
P SYSTEM
P POWER
V
OUT
RESET
WDI
GND
PFI
V
BATT
BATTERY
+
R4
R3
LL
IN
RESET
Figure 18a. ADM696 Typical Application Circuit A
Figure 18b shows a similar application for the ADM696 but in
this case the PFI input monitors the unregulated input to the
7805 voltage regulator. This gives an earlier warning of an im-
pending power failure. It is useful with processors operating at
low speeds or where there are a significant number of house-
keeping tasks to be completed before the power is lost.
ADM696
R2
R1
PFO
INPUT
POWER
V
CC
V
OUT
WDI
GND
PFI
V
BATT
0.1F
3V
BATTERY
RESET
OSC IN
OSC SEL
LOW LINE
WDO
SYSTEM STATUS
INDICATORS
CMOS
RAM
I/O LINE
NMI
RESET
A0A15
P
BATT
ON
NC
V
CC
LL
IN
P
POWER
RESET
R4
R3
7805
0.1F
Figure 18b. ADM696 Typical Application Circuit B
ADM696/ADM697
REV. 0
11
This application also shows an optional, external transistor
which may be used to provide in excess of 100 mA current on
V
OUT
. When V
CC
is higher than V
BATT
, the BATT ON output
goes low, providing 25 mA of base drive for the external PNP
transistor. The maximum current available is dependent on the
power rating of the external transistor.
RAM Write Protection
The ADM697 CE
OUT
line drives the Chip Select inputs of the
CMOS RAM. CE
OUT
follows CE
IN
as long as LL
IN
is above the
reset threshold. If LL
IN
falls below the reset threshold, CE
OUT
goes high, independent of the logic level at CE
IN
. This prevents
the microprocessor from writing erroneous data into RAM dur-
ing power-up, power-down, brownouts and momentary power
interruptions.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Pin Plastic DIP (N-16)
0.840 (21.33)
0.745 (18.93)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
PIN 1
0.280 (7.11)
0.240 (6.10)
9
1
6
1
8
0.210
(5.33)
0.200 (5.05)
0.125 (3.18)
0.022 (0.558)
0.014 (0.356)
0.100 (2.54)
BSC
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
0.070 (1.77)
0.045 (1.15)
16-Pin Cerdip (Q-16)
PIN 1
0.840 (21.34) MAX
0.060 (1.52)
0.015 (0.38)
0.015 (0.381)
0.008 (0.204)
0.150
(3.81)
MIN
0.200
(5.08)
MAX
0.022 (0.558)
0.014 (0.356)
0.100 (2.54)
BSC
0.070 (1.78)
0.30 (0.76)
PLANE
SEATING
0.310 (7.87)
0.220 (5.59)
0.320 (8.13)
0.290 (7.37)
1
8
9
16
16-Lead SOIC (R-16)
0.019 (0.49)
0.05 (1.27)
REF
0.104
(2.65)
0.012
(0.3)
0.413 (10.50)
0.419
(10.65)
0.042
(1.07)
0.013
(0.32)
0.030
(0.75)
0.299
(7.60)
1
8
9
16
C1783184/93
PRINTED IN U.S.A.
12
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