FUNCTIONAL BLOCK DIAGRAMS
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
INPUT (WDI)
POWER-FAIL
INPUT (PFI)
POWER-FAIL
OUTPUT (
PFO)
WATCHDOG
OUTPUT (
WDO)
RESET
*VOLTAGE REFERENCE = 4.65V (ADM705), 4.40V (ADM706)
ADM705/
ADM706
RESET &
WATCHDOG
TIMEBASE
RESET
GENERATOR
MR
V
CC
250 A
V
CC
WATCHDOG
TIMER
4.65V*
1.25V
1.25V
4.65V*
POWER-FAIL
INPUT (PFI)
POWER-FAIL
OUTPUT (
PFO)
RESET
*VOLTAGE REFERENCE = 4.65V (ADM707), 4.40V (ADM708)
ADM707/
ADM708
RESET
GENERATOR
MR
V
CC
250 A
V
CC
RESET
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Low Cost P
Supervisory Circuits
ADM705ADM708
FEATURES
Guaranteed
RESET Valid with V
CC
= 1 V
190 A Quiescent Current
Precision Supply-Voltage Monitor
4.65 V (ADM705/ADM707)
4.40 V (ADM706/ADM708)
200 ms Reset Pulsewidth
Debounced TTL/CMOS Manual Reset Input (
MR)
Independent Watchdog Timer--1.6 sec Timeout
(ADM705/ADM706)
Active High Reset Output (ADM707/ADM708)
Voltage Monitor for Power-Fail or Low Battery
Warning
Superior Upgrade for MAX705MAX708
Also Available in MicroSOIC Packages
APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Critical P Monitoring
Automotive Systems
Critical P Power Monitoring
GENERAL DESCRIPTION
The ADM705ADM708 are low cost
P supervisory circuits.
They are suitable for monitoring the 5 V power supply/battery
and can also monitor microprocessor activity.
The ADM705/ADM706 provide the following functions:
1. Power-On Reset output during power-up, power-down and
brownout conditions. The
RESET output remains opera-
tional with V
CC
as low as 1 V.
2. Independent watchdog timeout,
WDO, that goes low if the
watchdog input has not been toggled within 1.6 seconds.
3. A 1.25 V threshold detector for power-fail warning, low
battery detection or to monitor a power supply other than
5 V.
4. An active low debounced manual reset input (
MR).
The ADM707/ADM708 differ in that:
1. A watchdog timer function is not available.
2. An active high reset output in addition to the active low
output is available.
Two supply-voltage monitor levels are available. The ADM705/
ADM707 generate a reset when the supply voltage falls below
4.65 V, while the ADM706/ADM708 require that the supply
fall below 4.40 V before a reset is issued.
All parts are available in 8-lead DIP and SOIC packages. The
ADM707 and ADM708 are also available in space-saving
microSOIC packages.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2000
ADM705ADM708SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
V
CC
Operating Voltage Range
1.0
5.5
V
Supply Current
190
250
A
Reset Threshold
4.5
4.65
4.75
V
ADM705, ADM707
4.25
4.40
4.50
V
ADM706, ADM708
Reset Threshold Hysteresis
40
mV
Reset Pulsewidth
160
200
280
ms
RESET Output Voltage
V
CC
1.5
V
I
SOURCE
= 800
A
0.4
V
I
SINK
= 3.2 mA
0.3
V
V
CC
= 1 V, I
SINK
= 50
A
0.3
V
V
CC
= 1.2 V, I
SINK
= 100
A
RESET Output Voltage
V
CC
1.5
V
ADM707, ADM708, I
SOURCE
= 800
A
0.4
V
ADM707, ADM708, I
SINK
= 1.2 mA
Watchdog Timeout Period (t
WD
)
1.00
1.60
2.25
sec
WDI Pulsewidth (t
WP
)
50
ns
V
IL
= 0.4 V, V
IH
= V
CC
0.8
WDI Input Threshold
Logic Low
0.8
V
Logic High
3.5
V
WDI Input Current
50
150
A
WDI = V
CC
150
50
A
WDI = 0 V
WDO Output Voltage
V
CC
1.5
V
I
SOURCE
= 800
A
0.4
V
I
SINK
= 1.2 mA
MR Pull-Up Current
100
250
600
A
MR = 0 V
MR Pulsewidth
150
ns
MR Input Threshold
0.8
V
2.0
V
MR to Reset Output Delay
250
ns
PFI Input Threshold
1.2
1.25
1.3
V
PFI Input Current
25
0.01
25
nA
PFO Output Voltage
V
CC
1.5
V
I
SOURCE
= 800
A
0.4
V
I
SINK
= 3.2 mA
Specifications subject to change without notice.
REV. B
2
(V
CC
= 4.75 V to 5.5 V, T
A
= T
MIN
to T
MAX
unless otherwise noted.)
ORDERING GUIDE
Model
Temperature Range
Package Option
ADM705AN
40
C to +85C
N-8
ADM705AR
40
C to +85C
SO-8
ADM706AN
40
C to +85C
N-8
ADM706AR
40
C to +85C
SO-8
ADM707AN
40
C to +85C
N-8
ADM707AR
40
C to +85C
SO-8
ADM707ARM
40
C to +85C
RM-8
ADM708AN
40
C to +85C
N-8
ADM708AR
40
C to +85C
SO-8
ADM708ARM
40
C to +85C
RM-8
ABSOLUTE MAXIMUM RATINGS
*
(T
A
= 25
C unless otherwise noted)
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +6 V
All Other Inputs . . . . . . . . . . . . . . . . . . 0.3 V to V
CC
+ 0.3 V
Input Current
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Power Dissipation, N-8 DIP . . . . . . . . . . . . . . . . . . . . 727 mW
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135
C/W
Power Dissipation, SO-8 SOIC . . . . . . . . . . . . . . . . . . 470 mW
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110
C/W
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . . 40
C to +85C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300
C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
C
Storage Temperature Range . . . . . . . . . . . . . 65
C to +150C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >5 kV
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods of time may affect device reliability
ADM705ADM708
REV. B
3
PIN FUNCTION DESCRIPTION
Pin No.
ADM705
ADM707
ADM706
ADM708
Mnemonic
DIP, SOIC
DIP, SPOC
MicroSOIC
Function
MR
1
1
3
Manual Reset Input. When taken below 0.8 V, a RESET is gener-
ated.
MR can be driven from TTL, CMOS logic or from a manual
reset switch as it is internally debounced. An internal 250
A pull-up
current holds the input high when floating.
V
CC
2
2
4
5 V Power Supply Input.
GND
3
3
5
0 V. Ground reference for all signals.
PFI
4
4
6
Power-Fail Input. PFI is the noninverting input to the Power-Fail
Comparator. When PFI is less than 1.25 V,
PFO goes low. If unused,
PFI should be connected to GND or V
CC
.
PFO
5
5
7
Power-Fail Output.
PFO is the output from the Power-Fail Compara-
tor. It goes low when PFI is less than 1.25 V.
WDI
6
N/A
N/A
Watchdog Input. WDI is a three-level input. If WDI remains either
high or low for longer than the watchdog timeout period, the watch-
dog output
WDO goes low. The timer resets with each transition at
the WDI input.
Either a high-to-low or a low-to-high transition will clear the counter.
The internal timer is also cleared whenever reset is asserted. The
watchdog timer is disabled when WDI is left floating or connected to
a three-state buffer.
NC
N/A
6
8
No Connect.
RESET
7
7
1
Logic Output.
RESET goes low for 200 ms when triggered. It can be
triggered either by V
CC
being below the reset threshold or by a low
signal on the manual reset (
MR) input. RESET will remain low
whenever V
CC
is below the reset threshold (4.65 V in ADM705, 4.4 V
in ADM706). It remains low for 200 ms after V
CC
goes above the
reset threshold or
MR goes from low to high. A watchdog timeout
will not trigger
RESET unless WDO is connected to MR.
WDO
8
N/A
N/A
Logic Output. The Watchdog Output,
WDO, goes low if the internal
watchdog timer times out as a result of inactivity on the WDI input. It
remains low until the watchdog timer is cleared.
WDO also goes low
during low line conditions. Whenever V
CC
is below the reset threshold,
WDO remains low. As soon as V
CC
goes above the reset threshold,
WDO goes high immediately.
RESET
N/A
8
2
Logic Output. RESET is an active high output suitable for systems
that use active high RESET logic. It is the inverse of
RESET.
PIN CONFIGURATION
DIP, SOIC DIP, SOIC MicroSOIC
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
NC = NO CONNECT
ADM707/
ADM708
RESET
GND
PFI
PFO
NC
RESET
MR
V
CC
8
7
6
5
1
2
3
4
TOP VIEW
(Not to Scale)
ADM705/
ADM706
MR
PFO
WDI
RESET
WDO
V
CC
GND
PFI
8
7
6
5
1
2
3
4
TOP VIEW
(Not to Scale)
NC = NO CONNECT
ADM707/
ADM708
MR
PFO
NC
RESET
RESET
V
CC
GND
PFI
REV. B
4
ADM705ADM708
Manual Reset (ADM707/ADM708)
The manual reset input (
MR) allows other reset sources, such as
a manual reset switch, to generate a processor reset. The input
is effectively debounced by the timeout period (200 ms typical).
The
MR input is TTL/CMOS compatible, so it may also be
driven by any logic reset output.
V
CC
RESET
MR
WDO
VRT
VRT
t
RS
t
RS
MR EXTERNALLY
DRIVEN LOW
Figure 3.
RESET, MR, and WDO Timing
Watchdog Timer (ADM705/ADM706)
The watchdog timer circuit may be used to monitor the activity
of the microprocessor in order to check that it is not stalled in an
indefinite loop. An output line on the processor is used to toggle
the Watchdog Input (WDI) line. If this line is not toggled
within the timeout period (1.6 sec), the watchdog output
(
WDO) goes low. The WDO output may be connected to a
nonmaskable interrupt (NMI) on the processor; therefore, if the
watchdog timer times out, an interrupt is generated. The inter-
rupt service routine should then be used to rectify the problem.
If a
RESET signal is required when a timeout occurs, the WDO
output should be connected to the manual reset input (
MR).
The watchdog timer is cleared by either a high-to-low or by a
low-to-high transition on WDI. It is also cleared by
RESET
going low; therefore, the watchdog timeout period begins after
RESET goes high.
When V
CC
falls below the reset threshold,
WDO is forced low
whether or not the watchdog timer has timed out. Normally,
this would generate an interrupt, but it is overridden by
RESET
going low.
The watchdog monitor can be deactivated by floating the
Watchdog Input (WDI). The
WDO output can now be used as
a low-line output since it will only go low when V
CC
falls below
the reset threshold.
t
WP
WDI
WDO
RESET
t
RS
RESET EXTERNALLY
TRIGGERED BY
MR
t
WD
t
WD
t
WD
Figure 4. Watchdog Timing
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
INPUT (WDI)
POWER-FAIL
INPUT (PFI)
POWER-FAIL
OUTPUT (
PFO)
WATCHDOG
OUTPUT (
WDO)
RESET
*VOLTAGE REFERENCE = 4.65V (ADM705), 4.40V (ADM706)
ADM705/
ADM706
RESET &
WATCHDOG
TIMEBASE
RESET
GENERATOR
MR
V
CC
250 A
V
CC
WATCHDOG
TIMER
4.65V*
1.25V
Figure 1. ADM705/ADM706 Functional Block Diagram
1.25V
4.65V*
POWER-FAIL
INPUT (PFI)
POWER-FAIL
OUTPUT (
PFO)
RESET
*VOLTAGE REFERENCE = 4.65V (ADM707), 4.40V (ADM708)
ADM707/
ADM708
RESET
GENERATOR
MR
V
CC
250 A
V
CC
RESET
Figure 2. ADM707/ADM708 Functional Block Diagram
CIRCUIT INFORMATION
Power-Fail
RESET Output
RESET is an active low output that provides a RESET signal to
the Microprocessor whenever the V
CC
input is below the reset
threshold. An internal timer holds RESET low for 200 ms after
the voltage on V
CC
rises above the threshold. This is intended as
a power-on RESET signal for the microprocessor. It allows time
for both the power supply and the microprocessor to stabilize
after power-up. The
RESET output is guaranteed to remain
valid (low) with V
CC
as low as 1 V. This ensures that the micro-
processor is held in a stable shutdown condition as the power
supply voltage ramps up.
In addition to
RESET, an active high RESET output is also
available on the ADM707/ADM708. This is the complement of
RESET and is useful for processors requiring an active high
RESET signal.
ADM705ADM708
REV. B
5
Power-Fail Comparator
The power-fail comparator is an independent comparator that
may be used to monitor the input power supply. The comparator's
inverting input is internally connected to a 1.25 V reference
voltage. The noninverting input is available at the PFI input.
This input may be used to monitor the input power supply via
a resistive divider network. When the voltage on the PFI input
drops below 1.25 V, the comparator output (
PFO) goes low,
indicating a power failure. For early warning of power failure,
the comparator may be used to monitor the preregulator input
simply by choosing an appropriate resistive divider network.
The
PFO output can be used to interrupt the processor so that
a shutdown procedure is implemented before the power is lost.
INPUT
POWER
R1
R2
POWER-FAIL
INPUT
1.25V
PFI
PFO
POWER-FAIL
OUTPUT
ADM70x
Figure 5. Power-Fail Comparator
Adding Hysteresis to the Power-Fail Comparator
For increased noise immunity, hysteresis may be added to the
power-fail comparator. Since the comparator circuit is non-
inverting, hysteresis can be added simply by connecting a
resistor between the
PFO output and the PFI input as shown in
Figure 6. When
PFO is low, resistor R3 sinks current from the
summing junction at the PFI pin. When
PFO is high, resistor
R3 sources current into the PFI summing junction. This results
in differing trip levels for the comparator. Further noise immu-
nity may be achieved by connecting a capacitor between PFI
and GND.
7V TO 15V
INPUT POWER
TO P NMI
R3
5V
V
CC
R1
R2
1.25V
PFI
PFO
ADM70x
ADM663
5V
PFO
0V
0V
V
L
V
IN
V
H
Figure 6. Adding Hysteresis to the Power-Fail Comparator
V
R
R
R
R
R
V
R
R
V
RE
V
R
R
R
H
L
CC
MID
=
[
+
+
=
+
=
+
1 25 1
2
3
2
3
1
1 25
1
1 25
2
1 25
1 25
1
2
2
.
]
.
.
.
.
Valid
RESET Below 1 V V
CC
The ADM70x family of products is guaranteed to provide a
valid reset level with V
CC
as low as 1 V; please refer to the Typi-
cal Performance Characteristics. As V
CC
drops below 1 V, the
internal transistor will not have sufficient drive to hold it ON so
the voltage on
RESET will no longer be held at 0 V. A pull-down
resistor as shown in Figure 7 may be connected externally to
hold the line low if it is required.
ADM70x
GND
RESET
R1
Figure 7.
RESET Valid Below 1 V
REV. B
6
ADM705ADM708Typical Performance Characteristics
1.3V
4.4V
0V
1.2V
PFO
PFI
500ns/DIV
V
CC
= 5V
T
A
= 25 C
Figure 11. PFI Comparator Deassertion Response Time
5V
0V
5V
100ns/DIV
0V
V
CC
= V
RT
T
A
= 25 C
RESET
RESET
Figure 12.
RESET, RESET Assertion
5V
0V
5V
100ns/DIV
0V
V
CC
= V
RT
T
A
= 25 C
RESET
RESET
Figure 13.
RESET, RESET Deassertion
10
0%
100
90
500msHo
1V
4.50V
A!
1V
V
CC
RESET
Figure 8.
RESET Output Voltage vs. Supply Voltage
100
90
500msHo
1V
4.50V
A1
1V
V
CC
RESET
10
0%
Figure 9. ADM707/ADM708 RESET Output Voltage vs.
Supply Voltage
1.2V
0V
5V
1.3V
PFI
PFO
500ns/DIV
V
CC
= 5V
T
A
= 25 C
Figure 10. PFI Comparator Assertion Response Time
ADM705ADM708
REV. B
7
If, in the event of inactivity on the WDI line, a system reset is
required, then the
WDO output should be connected to the MR
input as shown in Figure 16.
ADM705/
ADM706
RESET
GND
I/O LINE
P
MR
WDI
WDO
RESET
Figure 16.
RESET from WDO
Monitoring Additional Supply Levels
It is possible to use the power-fail comparator to monitor a
second supply as shown in Figure 17. The two sensing resistors,
R1 and R2, are selected so that the voltage on PFI drops below
1.25 V at the minimum acceptable input supply. The
PFO
output may be connected to the
MR input so that a RESET is
generated when the supply drops out of tolerance. In this case, if
either supply drops out of tolerance, a
RESET will be generated.
ADM705/
ADM706
RESET
GND
P
MR
PFI
PFO
RESET
V
CC
R1
R2
V
X
5V
Figure 17. Monitoring 5 V and an Additional Supply, V
X
Ps With Bidirectional
RESET
In order to prevent contention for microprocessors with a bidi-
rectional reset line, a current limiting resistor should be inserted
between the ADM70x
RESET output pin and the
P reset pin.
This will limit the current to a safe level if there are conflicting
output reset levels. A suitable resistor value is 4.7 k
. If the
reset output is required for other uses, it should be buffered as
shown in Figure 18.
ADM70x
RESET
GND
P
RESET
GND
BUFFERED
RESET
5V
V
CC
Figure 18. Bidirectional I-O
RESET
APPLICATIONS
A Typical Operating Circuit is shown in Figure 15. The unregu-
lated dc input supply is monitored using the PFI input via the
resistive divider network. Resistors R1 and R2 should be selected
so that when the supply voltage drops below the desired level
(e.g., 8 V), the voltage on PFI drops below the 1.25 V threshold
thereby generating an interrupt to the
P. Monitoring the pre-
regulator input gives additional time to execute an orderly
shutdown procedure before power is lost.
ADM705/
ADM706
RESET
GND
P
MR
PFI
WDI
PFO
RESET
V
CC
5V
WDO
V
CC
UNREGULATED
DC
I/O LINE
INTERRUPT
NMI
MANUAL
RESET
GND
IN
OUT
ADM666
R1
R2
Figure 15. Typical Application Circuit
Microprocessor activity is monitored using the WDI input. This
is driven using an output line from the processor. The software
routines should toggle this line at least once every 1.6 seconds.
If a problem occurs and this line is not toggled,
WDO goes low
and a nonmaskable interrupt is generated. This interrupt rou-
tine may be used to clear the problem.
4V
V
CC
5V
2 s/DIV
0V
5V
RESET
T
A
= 25 C
Figure 14. ADM705/ADM707
RESET Response Time
REV. B
8
ADM705ADM708
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP
(N-8)
0.125 (3.18)
MIN
0.165
0.01
(4.19
0.25)
0.035
0.01
(0.89
0.25)
0.018
0.003
(0.46
0.08)
0.10 (2.54)
TYP
0.18
0.03
(4.57
0.76)
0.033
(0.84)
NOM
SEATING
PLANE
0.39 (9.91)
MAX
0.25
(6.35)
0.31
(7.87)
8
1
4
5
PIN 1
0.011
0.003
(4.57
0.76)
0 - 15
0.30 (7.62)
REF
8-Lead SOIC
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
8
5
4
1
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
0
0.0196 (0.50)
0.0099 (0.25)
x 45
8-Lead MicroSOIC
(RM-8)
8
5
4
1
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
PIN 1
0.0256 (0.65) BSC
0.122 (3.10)
0.114 (2.90)
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.018 (0.46)
0.008 (0.20)
0.043 (1.09)
0.027 (0.68)
0.120 (3.05)
0.112 (2.84)
0.011 (0.28)
0.003 (0.08)
0.027 (0.68)
0.015 (0.38)
33
27
0.120 (3.05)
0.112 (2.84)
PRINTED IN U.S.A.
C00088a08/00 (rev. B)
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