REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
ADP1148, ADP1148-3.3, ADP1148-5
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1997
High Efficiency Synchronous
Step-Down Switching Regulators
FUNCTIONAL BLOCK DIAGRAM
Q
R
S
V
TH1
V
IN
SENSE()
V
TH2
1.25V
OFF-TIME
CONTROL
100k
13k
B
V
IN
P-DRIVE
SENSE(+)
SENSE()
G
4
6
C
T
I
TH
SHUTDOWN
8
1
3
ADP1148
10mV to
150mV
C
V
FB
INT V
CC
REFERENCE
5
10
T
N-DRIVE
PWR
GND
14
12
ADJUSTABLE
VERSION
V
FB
9
7
S
1
Q
R
S
2
V
SLEEP
SIGNAL
GND
11
NON-OVERLAP
DRIVE
FEATURES
Operation From 3.5 V to 18 V Input Voltage
Ultrahigh Efficiency > 95%
Low Shutdown Current
Current Mode Operation for Excellent Line and Load
Transient Response
High Efficiency Maintained Over Wide Current Range
Logic Controlled Micropower Shutdown
Short Circuit Protection
Very Low Dropout Operation
Synchronous FET Switching for High Efficiency
Adaptive Nonoverlap Gate Drives
APPLICATIONS
Notebook and Palmtop Computers
Portable Instruments
Battery Operated Digital Devices
Industrial Power Distribution
Avionics Systems
Telecom Power Supplies
GPS Systems
Cellular Telephones
GENERAL DESCRIPTION
The ADP1148 is part of a family of synchronous step-down
switching regulator controllers featuring automatic sleep mode
to maintain high efficiencies at low output currents. These
devices drive external complementary power MOSFETs at
switching frequencies up to 250 kHz using a constant off-time
current-mode architecture.
V
IN
INT V
CC
I
TH
C
T
S-GND
P-DRIVE
SENSE(+)
SENSE()
SHUTDOWN
N-DRIVE
P-GND
ADP1148
+
+
P-CH
IRF7204
N-CH
IRF7403
1000pF
C
T
470pF
R
C
1k
C
C
3300pF
C1
10BQ040
L*
62 H
R
SENSE
**
0.05
+
C
OUT
390 F
C
IN
100 F
V
IN
(5.2V TO 18V)
1 F
10nF
0V = NORMAL
>1.5V = SHUTDOWN
*COILTRONICS CTX-68-4
**KRL SL-1-C1-0R050L
V
OUT
5V/2A
Figure 1. High Efficiency Step-Down Converter
Figure 2. ADP1148-5 Typical Efficiency
The constant off-time architecture maintains constant ripple
current in the inductor, easing the design of wide input range
converters. Current-mode operation provides excellent line and
load transient response. The operating current level is user
programmable via an external current sense resistor.
The ADP1148 incorporates automatic Power Saving Sleep
Mode operation when load currents drop below the level re-
quired for continuous operation. In sleep mode, standby power
is reduced to only about 2 mW at V
IN
= 10 V. In shutdown,
both MOSFETs are turned off.
TYPICAL APPLICATIONS
LOAD CURRENT A
100
85
70
0.02
2
95
90
80
75
EFFICIENCY %
0.2
V
IN
= 6V
V
IN
= 10V
FIGURE 1 CIRCUIT
2
REV. A
ADP1148, ADP1148-3.3, ADP1148-5SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
2
Min
Typ
Max
Units
FEEDBACK VOLTAGE
ADP1148 Only
V
10
V
IN
= 9 V
1.21
1.25
1.29
V
FEEDBACK CURRENT
ADP1148 Only
I
10
0.2
1.0
A
REGULATED OUTPUT VOLTAGE
V
OUT
V
IN
= 9 V
ADP1148-3.3
I
LOAD
= 700 mA
3.23
3.33
3.43
V
ADP1148-5
I
LOAD
= 700 mA
4.9
5.05
5.2
V
OUTPUT VOLTAGE LINE
T
A
= +25
C, V
IN
= 7 V to 12 V,
REGULATION
dV
OUT
I
LOAD
= 50 mA
40
+40
mV
OUTPUT VOLTAGE LOAD
REGULATION
dV
OUT
ADP1148-3.3
5 mA < I
LOAD
< 2 A
40
65
mV
ADP1148-5
5 mA < I
LOAD
< 2 A
60
100
mV
SLEEP MODE OUTPUT RIPPLE
dV
OUT
I
LOAD
= 0 A
50
mV p-p
INPUT DC SUPPLY CURRENT
3
I
Q
T
A
= +25
C
Normal Mode
V
IN
= 4 V < V
IN
< 18 V
1.6
2.3
mA
Sleep Mode (ADP1148-3.3)
V
IN
= 4 V < V
IN
< 18 V
160
250
A
Sleep Mode (ADP1148-5)
V
IN
= 4 V < V
IN
< 18 V
160
250
A
Shutdown
V
SHUTDOWN
= 2.1 V,
10
20
A
4 V < V
IN
< 15 V
CURRENT SENSE THRESHOLD
V
8
V
7
V
9
= V
OUT
/4 + 25 mV (Forced),
VOLTAGE
4
V
7
= 5 V, T
A
= +25
C
25
mV
ADP1148 Only
V
9
= V
OUT
/4 mV 25 mV (Forced),
V
7
= 5 V
130
150
170
mV
ADP1148-3.3
V
7
= V
OUT
+ 100 mV (Forced)
25
mV
V
7
= V
OUT
100 mV (Forced)
130
150
170
mV
ADP1148-5
V
7
= V
OUT
+ 100 mV (Forced
25
mV
V
7
= V
OUT
100 mV (Forced)
130
150
170
mV
SHUTDOWN PIN THRESHOLD
ADP1148-3.3, ADP1148-5
V
10
T
A
= +25
C
0.6
0.8
2.0
V
SHUTDOWN PIN INPUT CURRENT
I
10
0 V < V
SHUTDOWN
< 8 V, V
IN
= 18 V
1.2
5
A
C
T
PIN DISCHARGE CURRENT
I
4
T
A
= +25
C, V
OUT
in Regulation,
V
7
= V
OUT
,
50
65
90
A
V
OUT
= 0 V
2
10
A
OFF-TIME
t
OFF
C
T
= 390 pF, I
LOAD
= 700 mA
4
5
6
s
DRIVER OUTPUT TRANSITION
t
R
, t
F
C
L
= 3000 pF (Pins 1, 14)
TIMES
V
IN
= 6 V, T
A
= +25
C
100
200
ns
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Quality Control methods. Specifications subject to change without notice.
2
T
J
is calculated from the ambient temperature T
A
and power dissipation P
D
according to the following formulas:
ADP1148AR, ADP1148AR-3.3, ADP1148AR-5:
T
J
= T
A
+ (P
D
110
C/W)
ADP1148AN, ADP1148AN-3.3, ADP1148AN-5:
T
J
= T
A
+ (P
D
70
C/W)
3
Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. The allowable operating frequency may be limited by power
dissipation at high input voltages.
4
The ADP1148 version is tested with external feedback resistors, setting the nominal output voltage to 3.3 V.
Specifications subject to change without notice.
(0 C
T
A
+70 C,
1
V
IN
= 10 V, V
SHUTDOWN
= 0 V, unless otherwise noted. See Figure 17.)
3
REV. A
ADP1148, ADP1148-3.3, ADP1148-5
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
2
Min
Typ
Max
Units
FEEDBACK VOLTAGE
ADP1148 Only
V
10
V
IN
= 9 V
1.20
1.25
1.30
V
REGULATED OUTPUT VOLTAGE
V
OUT
V
IN
= 9 V
ADP1148-3.3
I
LOAD
= 700 mA
3.17
3.33
3.4
V
ADP1148-5
I
LOAD
= 700 mA
4.85
5.05
5.2
V
INPUT DC SUPPLY CURRENT
3
I
Q
Normal Mode
V
IN
= 4 V < V
IN
< 18 V
1.6
2.6
mA
Sleep Mode (ADP1148-3)
V
IN
= 4 V < V
IN
< 18 V
160
280
A
Sleep Mode (ADP1148-5)
V
IN
= 6 V < V
IN
< 18 V
160
280
A
Shutdown
V
SHUTDOWN
= 2.1 V,
10
24
A
4 V < V
IN
< 12 V
CURRENT SENSE THRESHOLD
VOLTAGE
4
V
8
V
7
ADP1148 Only
V
9
= V
OUT
/4 + 25 mV (Forced),
0
mV
V
7
= 5 V
V
9
= V
OUT
/4 25 mV (Forced),
115
150
175
mV
V
7
= 5 V
ADP1148-3.3
V
7
= V
OUT
+ 100 mV (Forced)
0
mV
V
7
= V
OUT
100 mV (Forced)
115
150
175
mV
ADP1148-5.0
V
7
= V
OUT
+ 100 mV (Forced)
0
mV
V
7
= V
OUT
100 mV (Forced)
115
150
175
mV
SHUTDOWN PIN THRESHOLD
V
10
ADP1148-3.3, ADP1148-5
0.55
0.8
2
V
OFF-TIME
t
OFF
C
T
= 390 pF, I
LOAD
= 700 mA
4
5
6.2
s
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Quality Control method.
2
T
J
is calculated from the ambient temperature T
A
and power dissipation P
D
according to the following formulas:
ADP1148AR, ADP1148AR-3, ADP1148AR-5: T
J
= T
A
+ (P
D
110
C/W)
ADP1148AN, ADP1148AN-3, ADP1148AN-5: T
J
= T
A
+ (P
D
70
C/W)
3
Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. The allowable operating frequency may be limited by power
dissipation at high input voltages.
4
The ADP1148 version is tested with external feedback resistors setting the nominal output voltage to 3.3 V.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage (Pin 3) . . . . . . . . . . . . . 0.3 V to +20 V
Continuous Output Currents (Pins 1, 14) . . . . . . . . . . 50 mA
Sense Voltages (Pins 7, 8) . . . . . . . . . . . . . . . . 0.3 V to V
CC
Operating Temperature Range . . . . . . . . . . . . 0
C to +70
C
Extended Commercial Temperature Range . . 40
C to +85
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150
C
Storage Temperature Range . . . . . . . . . . . . 65
C to +150
C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300
C
(40 C
T
A
+85 C,
1
V
IN
= 10 V, V
SHUTDOWN
= 0 V, unless otherwise noted. See Figure 17.)
ORDERING GUIDE
Output
Package
Package
Model
Voltage
Description
Option
ADP1148AN
ADJ
Plastic DIP
N-14
ADP1148AR
ADJ
Small Outline Package SO-14
ADP1148AN-3.3
3.3 V
Plastic DIP
N-14
ADP1148AR-3.3
3.3 V
Small Outline Package SO-14
ADP1148AN-5
5 V
Plastic DIP
N-14
ADP1148AR-5
5 V
Small Outline Package SO-14
ADP1148, ADP1148-3.3, ADP1148-5
4
REV. A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP1148, ADP1148-3.3, ADP1148-5 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS
Pin #
Mnemonic
Function
1
P-Channel Drive
High Current Gate Drive for Top P-Channel MOSFET. The voltage swing at Pin 4 is from V
IN
to
ground.
2
NC
No Connection.
3
V
IN
Input Voltage.
4
C
T
External Capacitor C
T
from Pin 4 to Ground Sets the Operating Frequency. The frequency is also
dependent on the ratio V
OUT
/V
IN
.
5
Int V
CC
Internal Supply Voltage, Nominally 3.3 V. Must be decoupled to signal ground. Do not externally load
this pin.
6
I
TH
Error Amplifier Decoupling Point. The current comparator threshold increases with the Pin 7 voltage.
7
Sense
Connects to internal resistive divider that sets the output voltage in ADP1148-3.3 and ADP1148-5
versions. Pin 7 is also the () input for the current comparator.
8
Sense+
The (+) Input for the Current Comparator. A built-in offset between Pins 7 and 8, in conjunction with
R
SENSE
, sets the current trip threshold.
9
V
FB
For the ADP1148 adjustable version, Pin 9 serves as the feedback pin from an external resistive divider
used to set the output voltage. On ADP1148-3.3 and ADP1148-5 versions, this pin is not used.
10
Shutdown
Taking Pin 10 of the ADP1148, ADP1148-3.3 or ADP1148-5 high holds both MOSFETs off. Must be
at ground potential for normal operation.
11
Signal GND
Small Signal Ground. Must be routed separately from other grounds to the () terminal of C
OUT
.
12
Power GND
Driver Power Ground. Connects to source of N-channel MOSFET and the () terminal of C
IN
.
13
NC
No Connection.
14
N-Channel Drive
High Current Drive for bottom N-channel MOSFET. The voltage swing at Pin 13 is from ground to
V
IN
.
PIN CONFIGURATIONS
14-Lead Plastic DIP
14-Lead Plastic SO
14
13
12
11
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
NC = NO CONNECT
P-DRIVE
SIGNAL GND
POWER GND
NC
N-DRIVE
NC
V
IN
C
T
ADP1148
SENSE(+)
V
FB
*
SHUTDOWN
INT V
CC
I
TH
SENSE()
*FIXED OUTPUT VERSIONS = SD1
WARNING!
ESD SENSITIVE DEVICE
Typical Performance CharacteristicsADP1148, ADP1148-3.3, ADP1148-5
5
REV. A
MAXIMUM OUTPUT CURRENT A
200
0
0
5
1
2
3
4
150
100
50
R
SENSE
m
Figure 3. Selecting R
SENSE
vs. Maxi-
mum Output Current
OUTPUT CURRENT A
EFFICIENCY/LOSS %
100
95
80
0.01
0.03
3.0
0.1
0.3
1.0
90
85
I
Q
GATE CHARGE
I
2
R
Figure 6. Typical Efficiency Losses
LOAD CURRENT A
V
OUT
mV
60
40
60
0
0.5
2.5
1.0
1.5
2.0
20
0
20
40
FIGURE 1 CIRCUIT
V
IN
= 6V
V
IN
= 12V
Figure 9. Load Regulation
L = 50 H
R
SENSE
= 0.02
L = 25 H
R
SENSE
= 0.02
L = 50 H
R
SENSE
= 0.05
(V
IN
V
OUT
) VOLTAGE V
1000
800
0
0
5
2
3
4
1
600
400
200
C
OUT
F
Figure 5. Selecting Minimum Output
Capacitor vs. (V
IN
V
OUT
) and Inductor
V
OUT
mV
V
IN
+40
+20
60
0
4
16
6
8
10
12
14
0
20
40
FIGURE 1 CIRCUIT
I
LOAD
= 1A
I
LOAD
= 0.1A
Figure 8. ADP1148-5 Output Voltage
Change vs. Input Voltage
V
SHUTDOWN
= 2V
INPUT VOLTAGE V
SUPPLY CURRENT
A
30
0
4
6
20
8
10
12
14
16
18
25
20
15
10
5
Figure 11. Supply Current in Shutdown
FREQUENCY kHz
1000
0
0
300
100
200
400
200
800
600
V
IN
= 12V
V
IN
= 10V
V
IN
= 7V
V
SENSE
= V
OUT
= 5V
CAPACITANCE pF
Figure 4. Operating Frequency vs.
Timing Capacitor Value
INPUT VOLTAGE V
100
86
80
0
20
4
8
12
16
98
88
84
82
92
90
96
94
EFFICIENCY %
FIGURE 1 CIRCUIT
I
LOAD
= 1A
I
LOAD
= 100mA
Figure 7. Efficiency vs. Input Voltage
INPUT VOLTAGE V
SUPPLY CURRENT mA
1.6
0.0
4
6
20
ACTIVE MODE
SLEEP MODE
8
10
12
14
16
18
1.4
0.8
0.6
0.4
0.2
1.2
1.0
Figure 10. DC Supply Current
(V
IN
V
OUT
) V
1
2
NORMALIZED FREQUENCY
12
4
6
8
10
1.8
1.6
0.0
0.8
0.6
0.4
0.2
1.4
1.0
1.2
0 C
25 C
70 C
Figure 12. Operating Frequency vs.
(V
IN
V
OUT
)
TEMPERATURE C
155
120
0
100
25
70
85
150
145
140
135
SENSE VOLTAGE mV
130
125
MAXIMUM THRESHOLD
Figure 15. Current Sense Threshold
Voltage
OPERATING FREQUENCY kHz
GATE CHARGE CURRENT mA
30
0
20
50
260
80
110
140
170
200
230
25
20
15
10
5
Qn+Qp = 50nC
Qn+Qp = 100nC
Figure 13. Gate Charge Supply
Current
OUTPUT VOLTAGE V
OFF TIME
sec
80
30
0
0.3 0.5
5.0
1.0 1.5 2.0 2.5 3.0 3.3 3.5 4.0 4.5
70
40
20
10
60
50
5V
3.3V
Figure 14. Off Time vs. V
OUT
ADP1148, ADP1148-3.3, ADP1148-5Typical Performance Characteristics
6
REV. A
ADP1148, ADP1148-3.3, ADP1148-5
7
REV. A
APPLICATIONS
The ADP1148 uses a current-mode, constant off-time structure
to switch a pair of external complementary N- and P-channel
MOSFETs. The operating frequency of the device is deter-
mined by the value of the external capacitor connected to the
C
T
pin.
The output voltage is sensed by an internal voltage divider which is
connected to the Sense() pin (ADP1148-3.3 and AD1148-5) or
an external voltage divider returned to V
FB
(ADP1148). A voltage
comparator V, and a gain block G compare the values of the
divided output voltage with a reference voltage of 1.25 V.
To maximize the efficiency, the ADP1148 automatically switches
between two operational modes, power-saving and continuous.
The Flip-Flop 1 is the main control element when the device is
in its power-saving mode while the gain block is the main con-
trol when the output voltage moves to continuous mode. During
the continuous mode of the PMOS switch on-cycle, the current
comparator C, monitors the voltage between Sense() and
Sense(+). When the voltage level reaches the threshold level, the
P drive output is switched to V
IN
which turns off the P-channel
MOSFET. The timing capacitor C
T
is now able to discharge at
a rate determined by the off-time controller. The discharge
current is made to be proportional to the value of the output
voltage (measured at the Sense() pin) to model the inductor
current which decays at a rate which is proportional to the out-
put voltage. While the timing capacitor is discharging, the N
drive output goes to V
IN
, turning on the N-channel MOSFET.
When the voltage level on the timing capacitor has discharged to
the threshold voltage level V
TH1
, comparator T switches setting
Flip-Flop 1. This forces the N drive to go off and the P drive
output low and subsequently turns the P-channel MOSFET on.
The sequence is then repeated. As load current increases, the
output voltage starts to reduce. This results in the output of the
gain circuit increasing the level of the current comparator thresh-
old, thus tracking the load current.
At very low load currents the power-saving sequence will be
interrupted by the Set of Flip-Flop 2, by voltage comparator B,
which also monitors the voltage across R
SENSE
. When the load
current decreases to half the designed inductor ripple current,
the voltage across R
SENSE
will reverse polarity. When this hap-
pens, comparator B will set the Q-bar output of Flip-Flop 2,
which will go to logic zero state and interrupt the cycle-by-cycle
operation and inhibit the output FET-driver. The output of the
power supply storage capacitor will slowly be drained by the
load and the output voltage starts decreasing. When this
decreased voltage exceeds the V
OS
of comparator V, this in turn
will reset Flip-Flop 2, and normal cycle-by-cycle operation will
resume. If the load is very small, it will take a long time for Flip-
Flop 2 to reset, and during that time the oscillator capacitor
may discharge below V
TH2
. At the point at which the timing
capacitor discharges below V
TH2
, comparator S trips causing the
internal sleep-bar to go low. The circuit is now in sleep mode
and the N-channel Power MOSFET remains turned off. While
the circuit remains in this mode, a significant amount of the
circuit of the IC is turned off dropping the ground current from
approximately 1.6 mA to a level of 160
A. In this state the load
current is supplied by the output capacitor. The sleep mode is
also terminated by the reset of Flip-Flop 2.
To prevent both the external MOSFETs from ever being turned
on simultaneously, feedback is incorporated to sense the state of
the driver output pins.
Before the N drive output can go high, the P drive output must
also be high. Likewise, the P drive output is unable to go low
while the N drive output is high. By utilizing a constant off-time
structure, the device operation is a function of the input voltage.
To limit the effect of frequency variation as the device approaches
dropout, the controller begins to increase the discharge current
as V
IN
drops below V
OUT
+1.5 V. While the device is in drop-
out, the P-channel MOSFET is on constantly.
R
SENSE
Selection For Output Current
The choice of R
SENSE
is based on the required output current.
The ADP1148 current comparator has a threshold range which
extends from 0 mV to a maximum of 150 mV/R
SENSE
. The
current comparator threshold sets the peak of the inductor cur-
rent, yielding a maximum output current I
MAX
equal to the peak
value less half the peak-to-peak ripple current. The ADP1148
operates effectively with values of R
SENSE
from 20 m
to
200 m
. A graph for selecting R
SENSE
versus maximum output
current is given in Figure 3. Solving for R
SENSE
and allowing a
margin for variations in the ADP1148 and external component
values yields:
R
SENSE
= 100 mV/I
MAX
The peak short circuit current, (I
SC(PK)
) tracks I
MAX
. Once
R
SENSE
has been chosen, I
SC(PK)
can be predicted from the fol-
lowing equation:
I
SC(PK)
= 150 mV/R
SENSE
The load current, below which power-saving mode commences
(I
POWER-SAVING
) is determined by the offset in comparator B and
the value of the inductor chosen. Comparator B is designed to
have approximately 5 mV offset. This offset and the inductor
can now be used to predict the power saving mode current as
follows:
I
POWER-SAVING
~ 5 mV/R
SENSE
+ V
O
t
OFF
/2 L
The ADP1148 automatically extends t
OFF
during a short circuit
to provide adequate time for the inductor current to decay be-
tween switch cycles. The resulting ripple current causes the
average short circuit current, I
SC(AVG)
, to be lowered to approxi-
mately I
MAX
.
L and C
T
Selection for Operating Frequency
The ADP1148 uses a constant off-time architecture with t
OFF
determined by an external timing capacitor C
T
. Each time the
P-channel MOSFET switch turns on, the voltage on C
T
is reset
to approximately 3.3 V. During the off time, C
T
is discharged by
a current which is proportional to V
OUT
. The voltage on C
T
is
analogous to the current in inductor L, which likewise decays at
a rate proportional to V
OUT
. Therefore, the inductor value must
track the timing capacitor value.
The value of C
T
is calculated from the preferred continuous
mode operating frequency:
C
T
= 1/2.6
10
4
f
Assumes V
IN
= 2 V
OUT
(Figure 1 circuit).
A graph for selecting C
T
versus frequency including the effects
of input voltage is given in Figure 5.
*Component, voltage, current, etc., values are in SI-units (international standard)
unless otherwise indicated.
ADP1148, ADP1148-3.3, ADP1148-5
8
REV. A
As the operating frequency is increased, the gate charge losses
will cause reduced efficiency (see Efficiency section). The full
formula for operating frequency is given by:
f = ( 1 V
OUT
/V
IN
)/t
OFF
where t
OFF
= 1.3
10
4
C
T
V
REG
/V
OUT.
V
REG
is the desired output voltage (i.e., 5 V or 3.3 V), V
OUT
is
the measured output voltage. Thus, V
REG
/V
OUT
= 1 in regulation.
Note that as V
IN
reduces, the frequency also decreases. When
the input to output voltage differential drops below 1.5 V, the
ADP1148 reduces t
OFF
by increasing the discharge current in
C
T
. This prevents audible operation before the device goes into
dropout.
Once the frequency has been set by C
T
, the inductor L must be
chosen to provide no more than 25 mV/R
SENSE
of peak-to-peak
inductor ripple current. This is set by the equation:
25 mV
R
SENSE
=
V
OUT
t
OFF
L
MIN
or
L
MIN
=
V
OUT
t
OFF
R
SENSE
25 mV
Substituting for t
OFF
from above gives the minimum required
inductor value of:
L
MIN
= 5.1
10
5
R
SENSE
C
T
V
REG
As the inductor value increases above the minimum value, the
ESR requirements for the output capacitor are relaxed at the
expense of efficiency. If too small an inductor is used, the induc-
tor current will decrease past zero and change polarity. A result
of this occurrence will be that the ADP1148 may not be in
power saving mode operation and efficiency will be significantly
reduced at low currents.
Inductor Core
Once the minimum value for L is known, the selection of the
inductor must be made. High efficiency converters -
generally
cannot accommodate the core loss found in low cost powdered
iron cores, forcing the use of more expensive ferrite, molypermalloy
(MPP), or Kool M
cores. Actual core loss is independent of
core size for a fixed inductor value, but it is very dependent on
inductance selected. As inductance increases, core losses de-
crease. Unfortunately, increased inductance requires more turns
of wire and therefore copper losses will increase.
Ferrite designs have very low core loss, so design goals can focus
on copper loss and preventing saturation. Ferrite core material
saturates "hard," which causes the inductance to collapse
abruptly when the peak design current is exceeded. This results
in a sharp increase in inductor ripple current and subsequently
output voltage ripple which can cause the power saving mode
operation to be falsely triggered in the ADP1148. To prevent
this action from occurring, do not allow the core to saturate!
Molypermalloy from Magnetics, Inc., is a very good, low loss
core material for toroids, but it is more expensive than ferrite. A
reasonable compromise from the same manufacturer is Kool
M
. Toroids are very space efficient, especially when you can
use several layers of wire. Because they generally lack a bobbin,
mounting is more difficult. Many new designs for surface mount
components are also available from Coiltronics which do not
increase the component height significantly.
Power MOSFET
Two external power MOSFETs must be selected for use with
the ADP1148, a P-channel MOSFET for the main switch, and
an N-channel MOSFET for the synchronous switch. The main
selection parameters for the power MOSFETs are the threshold
voltage V
GS(TH)
and on resistance R
DS(ON)
.
The minimum input voltage dictates whether standard threshold
or logic-level threshold MOSFETs must be used. For V
IN
> 8 V,
standard threshold MOSFETs (V
GS(TH
) < 4 V) may be used. If
V
IN
is expected to drop below 8 V, logic-level threshold MOSFETs
(V
GS(TH)
< 2.5 V) are strongly recommended. When logic-level
MOSFETs are used, the ADP1148 supply voltage must be less
than the absolute maximum V
GS
rating for the MOSFETs (e.g.,
>
8 V of IRF7304.
The maximum output current I
MAX
determines the R
DS(ON)
requirement for the two power MOSFETs. When the ADP1148
is operating in continuous mode, the simplifying assumption can
be made that one of the two MOSFETs is always conducting
the average load current. The duty cycles for the MOSFET and
diode are given by:
P-Channel Duty Cycle = V
OUT
/V
IN
N-Channel Duty Cycle = (V
IN
V
OUT
)/V
IN
From the duty cycle the required R
DS(ON)
for each MOSFET
can be derived:
P-Ch
RDS(ON)
= (V
IN
P
P
)/[V
OUT
I
MAX
2
(1 + d
P
)]
N-Ch
RDS(ON)
= (V
IN
P
N
)/[(V
IN
V
OUT
)
I
MAX
2
(1+d
N
)]
where P
p
and P
N
are the allowable power dissipations and d
p
and
d
N
are the temperature dependency of R
DS(ON)
. P
P
and P
N
will
be determined by efficiency and/or thermal requirements (see
Efficiency). (1+d) is generally given for a MOSFET in the form
of a normalized R
DS(ON)
vs. temperature curve, but d = 0.007/
C
can be used as an approximation for low voltage MOSFETs.
The Schottky diode D1 shown in Figure 1 conducts only during
the deadtime between the conduction of the two power
MOSFETs. D1's purpose is to prevent the body-diode of the
N-channel MOSFET from turning on and storing charge during
the dead time, which could cost as much as 1% in efficiency. D1
should be selected for forward voltage of less than 0.5 V when
conducting I
MAX
.
C
IN
and C
OUT
Selection
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle V
OUT
/V
lN
. To prevent
large voltage transients, a low ESR input capacitor sized for the
maximum rms current must be used. The maximum rms ca-
pacitor current is given by:
C
IN
required I
RMS
~ [V
OUT
(V
IN
V
OUT
)]
0.5
I
MAX
/V
IN
This formula has a maximum at V
IN
= 2 V
OUT
, where I
RMS
=
I
OUT
/2. This simple worst case condition is commonly used for
design because even significant deviations do not offer much
relief. Note that capacitor manufacturer's ripple current ratings
are often based on only 2000 hours of life. This makes it advis-
able to further derate the capacitor, or to choose a capacitor
rated at a higher temperature than required. Several capacitors
may also be paralleled to meet size or height requirements in the
design. Always consult the manufacturer if there is any question.
All trademarks are the property of their respective holders.
ADP1148, ADP1148-3.3, ADP1148-5
9
REV. A
An additional 0.1
F 1
F ceramic bypass capacitor is advised
on V
IN
Pin 3 parallel with C
IN
. The selection of C
OUT
is driven
by the required effective series resistance (ESR). The ESR of
C
OUT
must be less than twice the value of R
SENSE
for proper
operation of the ADP1148:
C
OUT
required ESR < 2 R
SENSE.
Optimum efficiency is obtained by making the ESR equal to
R
SENSE
. As the ESR is increased up to 2 R
SENSE
, the efficiency
degrades by less than 1%.
Manufacturers such as Sprague, and United Chemmicon should
be considered for high performance capacitors. The OS-CON
semiconductor dielectric capacitor has the lowest ESR for its
size, at a somewhat higher price. Once the ESR requirement for
C
OUT
has been met, the RMS current rating generally far ex-
ceeds the I
RIPPLE(P-P)
requirement.
In surface-mount applications multiple capacitors may have to
be paralleled to meet the capacitance, ESR, or RMS current
handling requirements of the application. Aluminum electrolytic
and dry tantalum capacitors are both available in surface-mount
configurations. In the case of tantalum, it is critical that the
capacitors are surge tested for use in switching power supplies.
Consult the manufacturer for other specific recommendations.
The C
O
output filter capacitor has to be sized correctly to avoid
excessive ripple voltages at low frequencies. See Figure 5 for
output capacitor selection.
Transient Response
The regulator loop response can be checked by looking at the
load transient response. Switching regulators take several cycles
to respond to a step in dc (resistive) load current. When a load
step occurs, V
OUT
shifts by an amount equal to D1
LOAD
ESR
,
where ESR is the effective series resistance of C
OUT.
D1
LOAD
also begins to charge or discharge C
OUT
until the regulator loop
adapts to the current change and returns V
OUT
to its steady-
state value. During this recovery time V
OUT
can be monitored
for overshoot or ringing which would indicate a stability prob-
lem. The external components on the I
TH
pin shown in the
Figure 1 circuit will prove adequate compensation for most
applications.
A second, more severe transient is caused by switching in loads
with large (>1 mF) supply bypass capacitors. The discharged
bypass capacitors are effectively put in parallel with C
OUT
, caus-
ing a rapid drop in V
OUT
. No regulator can deliver enough cur-
rent to prevent this problem if the load switch resistance is low
and it is driven quickly. The only solution is to limit the inrush
current to these capacitors below the current limit of the circuit.
Efficiency
The percent efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is limiting
the efficiency and which change would produce the most im-
provement. Percent efficiency can be expressed as:
% Efficiency = 100% - (L1 + L2 + L3 +. . . )
where L1, L2, etc. are the individual losses as a percentage of
input power. (For high efficiency circuits only small errors are
incurred by expressing losses as a percentage of output power.)
Although all dissipative elements in the circuit produce losses,
three main sources usually account for most of the losses in
ADP1148 circuits:
1) ADP1148 dc bias current,
2) MOSFET gate charge currents,
3) I
2
R losses.
1) The dc supply current is the current which flows into V
IN
Pin
3 less the gate charge current. For V
IN
= 10 V the ADP1148
dc supply current is 160
A for no load, and increases pro-
portionally with load up to a constant 1.6 mA after the
ADP1148 has entered continuous mode. Because the dc bias
current is drawn from V
IN
, the resulting loss increases with
input voltage. For V
IN
= 10 V the dc bias losses are generally
less than 1% for load currents over 30 mA. However, at very
low load currents the dc bias current accounts for nearly all
of the loss.
2) MOSFET gate charge currents result from switching the gate
capacitance of the power MOSFETs. Each time a MOSFET
gate is switched from low to high to low again, a packet of
charge dQ moves from V
IN
to ground. The resulting dQ/dt is
a current out of V
IN
which is typically much larger than the
dc supply current. In continuous mode, I
GATECHG
= f (Q
P
+
Q
N
). The typical gate charge for a 100 m
N-channel power
MOSFET is 25 nC and for the P-channel about twice that
value. This results in I
GATECHG
= 7.5 mA in 100 kHz continu-
ous operation for a 2% to 3% typical midcurrent loss with
V
IN
= 10 V.
Note that the gate charge loss increases directly with both
input voltage and operating frequency. This is the principal
reason why the highest efficiency circuits operate at moderate
frequencies. Furthermore, it argues against using a larger
MOSFET than necessary to control I
2
R losses.
3) I
2
R losses are easily predicted from the dc resistances of
the MOSFET, inductor, and current shunt. In continuous
mode the average output current flows through L and
R
SENSE
, but is "chopped" between the P-channel and N-
channel MOSFETs. If the two MOSFETs have about the
same R
DS(ON)
, the resistance of one MOSFET can be simply
summed with the resistances of L and R
SENSE
to obtain I
2
R
losses. For example, if each R
DS(ON)
= 100 m
, R
L
= 150 m
,
and R
SENSE
= 50 m
, then the total resistance is 300 m
.
This results in losses ranging from 3% to 10% as the output
current increases from 0.5 A to 2 A. I
2
R losses cause the
efficiency to roll-off at high output currents.
Figure 6 shows how the efficiency losses in a typical ADP1148
regulator. The gate charge loss is responsible for the majority of
the efficiency lost in the midcurrent region. If power saving
mode operation was not employed at low currents, the gate
charge loss alone would cause the efficiency to drop to unac-
ceptable levels. With power saving mode operation, the dc supply
current represents the lone (and unavoidable) loss component
which continues to become a higher percentage as output cur-
rent is reduced. As expected, the I
2
R losses dominate at high
load currents. Other losses including C
IN
and C
OUT
ESR dissi-
pative losses, MOSFET switching losses, Schottky conduction
losses during deadtime and inductor core losses, generally
account for less than 2% total additional loss.
ADP1148, ADP1148-3.3, ADP1148-5
10
REV. A
Design Example
As a design example, assume V
IN
= 12 V (nominal), V
OUT
= 5 V,
I
MAX
= 2 A, and f = 200 kHz, R
SENSE
. C
T
, and L can immedi-
ately be calculated:
R
SENSE
= 100 mV/2 = 50 m
t
OFF
= (1/200 kHz)
[1 (5/12)] = 2.92
s
C
T
= 2.92
s/(1.3
10
4
) = 220 pF
L min = 5.1
10
5
50 E-3
220 pF
5 V = 28
H
Assume that the MOSFET dissipations are to be limited to
P
N
= 2P
P
= 250 mW.
If T
A
= 50
C and the thermal resistance of each MOSFET is
50
C/W, then the junction temperatures will be 63
C and d
P
=
d
P
= 0.007
(6325) = 0.27.
The required R
DS(ON)
for each MOSFET can now be calculated:
P-Ch R
DS(ON)
= 12
0.25/5
2
1.27 = 120 m
N-Ch R
DS(ON)
= 12
0.25/7
2
1.27 = 85 m
The P-channel requirement can be met by a IRF7204. The
N-channel requirement can be met by a IRF7404. Note that
the most stringent requirement for the N-channel MOSFET is
with V
OUT
= 0 (i.e., short circuit). During a continuous short
circuit, the worst case N-channel MOSFET dissipation rises to:
P
N
~ I
SC(AVG)
2
R
DS(ON)
(1 + d
N
)
With the 50 m
sense resistor I
SC(AVG)
= 2 A will result, increas-
ing the N-channel dissipation to 0.45 W at die temperature of
73
C.
C
IN
will require an rms current rating of at least 1 A at tempera-
ture, and C
OUT
will require an ESR of 50 m
for optimum
efficiency.
Now allow V
IN
to drop to its minimum value. At lower input
voltages, the operating frequency will decrease and the P-
channel will be conducting most of the time causing the power
dissipation to increase. At V
IN(MIN)
= 7 V, the frequency shifts
to:
f
MIN
=
(1 V
OUT
/V
IN
)/t
OFF
= (1/2.92
s)
(1 5/7) = 98 kHz
and the P-channel power dissipation increases to:
P
P
= (120 m
) (2 A)
2
(1.27) 5 V/7 V = 435 mW
This last step is needed to ensure the maximum temperature of
the P-channel MOSFET is not exceeded.
ADP1148 Adjustable Applications
When an output voltage other than 3.3 V or 5 V is required, the
ADP1148 adjustable version is used with an external resistive
divider from V
OUT
to V
FB
Pin 9. The regulated voltage is deter-
mined by:
V
OUT
= 1.25 (1 + R2/R1)
To prevent a stray pickup, a 100 pF capacitor is suggested across
R1 located close to the ADP1148.
Auxiliary Windings
The ADP1148 synchronous switch removes the normal limita-
tion that power must be drawn from the inductor primary wind-
ing in order to extract power from auxiliary windings. With
synchronous switching, auxiliary outputs may be loaded without
regard to the primary output load, providing that the loop re-
mains in continuous mode operation.
Output Crowbar
An added feature to using an N-channel MOSFET as the syn-
chronous switch is the ability to crowbar the output with the
same MOSFET. Pulling the timing cap C
T
pin above 1.5 V
when the output voltage is greater than the desired regulated
value will turn "on" the N-channel MOSFET and turn "off" the
P-channel MOSFET.
A fault condition such as an external short between V
IN
and
V
OUT
, or an internal short of the P-channel device which causes
the output voltage to go above a maximum allowable value can
be detected by external circuity. Turning on the N-channel
MOSFET when this fault is detected will cause large currents to
flow and blow the system fuse.
The N-channel MOSFET needs to be sized so it will safely
handle this over current condition. The typical delay from pull-
ing the C
T
pin high and the N drive, Pin 14 going high is 250 ns.
Note: under shutdown conditions, the N-channel MOSFET
is held OFF and pulling the C
T
pin high will not cause the
N-channel MOSFET to crowbar the output.
A simple N-channel FET can be used as an interface between
the overvoltage detect circuitry and the ADP1148 as shown in
Figure 16.
ADP1148
INT V
CC
C
T
5
4
VN2222LL
*FROM CROWBAR
DETECT CIRCUIT
*ACTIVE WHEN V
GATE
= VIN
OFF WHEN V
GATE
= GROUND
Figure 16. Output Crowbar Interface
Troubleshooting
Since efficiency is critical to ADP1148 applications, it is very
important to verify that the circuit is functioning correctly in
both continuous and power saving mode operation. The wave-
form to monitor is the voltage on the timing capacitor
C
T
pin.
In continuous mode (I
LOAD
> I
POWER SAVING MODE
), the voltage
on the C
T
pin should be a sawtooth with a 0.9 V
p-p swing. This
voltage should never dip below 2 V as shown in Figure 17a.
When load currents are low (I
LOAD
< I
POWER SAVING MODE
)
,
power
saving mode operation occurs. The voltage on the C
T
pin now
falls to ground for periods of time as shown in Figure 17b. If the
C
T
pin is observed falling to ground at high output currents, it
indicates poor decoupling or improper grounding. Refer to the
Board Layout list.
3.3V
0V
3.3V
0V
(A) CONTINOUS MODE OPERATION
(B) POWER-SAVING MODE
Figure 17. C
T
Waveforms
ADP1148, ADP1148-3.3, ADP1148-5
11
REV. A
Board Layout
When laying out the printed circuit board, the following check
list should be used to ensure proper operation of the ADP1148.
These items are also illustrated graphically in the layout diagram
of Figure 18. Check the following in your layout:
1) Are the signal and power grounds segregated? The ADP1148
SIGNAL GND (Pin 11) must return to the () plate of C
OUT
.
The power ground returns to the source of the N-channel
MOSFET, anode of the Schottky diode, and () plate of C
IN
,
which should have as short lead lengths as possible.
2) Does the ADP1148 SENSE(), (Pin 7), connect to a point
close to R
SENSE
and the (+) plate Of C
OUT
? In adjustable
versions the resistive divider R1, R2 must be connected be-
tween the (+) plate of C
OUT
and signal ground.
3) Are the SENSE() and SENSE(+) leads routed together with
minimum PC trace spacing? The 1000 pF capacitor between
Pins 7 and 8 should be as close as possible to the ADP1148.
4) Does the (+) plate of C
IN
connect to the source of the
P-channel MOSFET as closely as possible? This capacitor
provides the ac current to the P-channel MOSFET.
5) Is the input decoupling capacitor (1
F) connected closely
between V
IN
(Pin 3) and POWER GND (Pin 12)? This
capacitor carries the MOSFET driver peak currents.
6) Is INTV
CC
(Pin 5) decoupled with a 10 nF capacitor to
signal ground?
7) Is the SHUTDOWN (Pin 10) actively pulled to ground
during normal operation? The Shutdown pin is high imped-
ance and must not be allowed to float.
To prevent noise spikes from erroneously tripping the current
comparator, a 1000 pF capacitor is needed across Sense() and
Sense(+).
P-DRIVE
NC
V
IN
C
T
INT V
CC
I
TH
SENSE()
N-DRIVE
NC
POWER GND
SIGNAL GND
SHUTDOWN
V
FB
SENSE(+)
ADP1148
3300pF
1k
D1
C
IN
L
R1
R2
C
OUT
10nF
C
T
1 F
1
2
3
4
5
6
7
14
13
12
11
10
9
8
N-CHANNEL
1000pF
R1, R2 OUTPUT DIVIDER REQUIRED
FOR ADJUSTABLE VERSION ONLY.
R
SENSE
V
IN
V
OUT
P-CHANNEL
NC = NO CONNECT
Figure 18. ADP1148 Layout Diagram (See Board Layout)
ADP1148, ADP1148-3.3, ADP1148-5
12
REV. A
P-DRIVE
NC
V
IN
C
T
INT V
CC
I
TH
SENSE()
N-DRIVE
NC
POWER GND
SIGNAL GND
SHUTDOWN
V
FB
SENSE(+)
ADP1148-3.3
C
C
3300pF
R
C
1k
IRF7403
D1
10BQ040
V
IN
4V TO 18V
IRF7204
C
IN
100 F
20V
*L
50 H
C
OUT
220 F
10V
2
AVX
1000pF
**R
SENSE
0.1
10nF
C
T
300pF
1 F
1
2
3
4
5
6
7
14
13
12
11
10
9
8
*COILTRONICS CTX50-2-MP
**KRL SP-1/2-A1-0R100J
V
OUT
3.3V/1A
NC = NO CONNECT
Figure 19. ADP1148 Low Dropout, 3.3 V/1 A High Efficiency Regulator
P-DRIVE
NC
V
IN
C
T
INT V
CC
I
TH
SENSE()
N-DRIVE
NC
POWER GND
SIGNAL GND
SHUTDOWN
V
FB
SENSE(+)
ADP1148
C
C
6800pF
R
C
1k
IRF7403
D1
10BQ015
V
IN
4V TO 9V
IRF7204
C
IN
220 F
20V
V
OUT
5V/1.4A
25k
1%
75k
1%
C
OUT
220 F
2
10V
200pF
1000pF
**R
SENSE
0.05
10nF
C
T
560pF
1 F
1
2
3
4
5
6
7
14
13
12
11
10
9
8
*COILTRONICS CTX50-2-MP
**KRL SL-1-C1-0R05J
*L
50 H
NC = NO CONNECT
Figure 20. 4 V to 9 V Input Voltage to 5 V/1.4 A Regulator
ADP1148, ADP1148-3.3, ADP1148-5
13
REV. A
P-DRIVE
NC
V
IN
C
T
INT V
CC
I
TH
SENSE()
N-DRIVE
NC
POWER GND
SIGNAL GND
SHUTDOWN
V
FB
SENSE(+)
ADP1148
C
C
3300pF
R
C
1k
IRF7403
D1
10BQ040
V
IN
5.2V TO 14V
IRF7204
C
IN
100 F
20V
*L
50 H
R1B
43k
1%
R2
56k
1%
C
OUT
220 F
10V
2
OS-CON
100pF
1000pF
**R
SENSE
0.05
10nF
C
T
390pF
1 F
1
2
3
4
5
6
7
14
13
12
11
10
9
8
R1A
33k
1%
0V: V
OUT
= 3.3V
5V: V
OUT
= 5V
VN2222LL
V
OUT
3.3V/2A
OR 5V/2A
*COILTRONICS CTX50-2-MP
**KRL SL-1-C1-0R050J
NC = NO CONNECT
Figure 21. Logic Selectable 5 V/1 A or 3.3 V/2 A High Efficiency Regulator
ADP1148, ADP1148-3.3, ADP1148-5
14
REV. A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead Plastic DIP
(N-14)
14
1
7
8
0.795 (20.19)
0.725 (18.42)
0.280 (7.11)
0.240 (6.10)
PIN 1
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.160 (4.06)
0.115 (2.93)
14-Lead Plastic SO
(SO-14)
14
8
7
1
0.3444 (8.75)
0.3367 (8.55)
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0688 (1.75)
0.0532 (1.35)
0.0500
(1.27)
BSC
0.0099 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
0
0.0196 (0.50)
0.0099 (0.25)
x 45
15
16
C2219a212/97
PRINTED IN U.S.A.
PDF 
ZIP