ADP3335 Data Sheet
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
ADP3335
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2000
High Accuracy Ultralow I
Q
, 500 mA
anyCAP
Low Dropout Regulator
FUNCTIONAL BLOCK DIAGRAM
THERMAL
PROTECTION
CC
IN
ADP3335
OUT
R1
R2
GND
Q1
SD
BANDGAP
REF
DRIVER
g
m
NR
FEATURES
High Accuracy Over Line and Load: 0.9% @ 25 C,
1.8% Over Temperature
Ultralow Dropout Voltage: 200 mV (Typ) @ 500 mA
Requires Only C
O
= 1.0 F for Stability
anyCAP = Stable with Any Type of Capacitor
(Including MLCC)
Current and Thermal Limiting
Low Noise
Low Shutdown Current: < 1.0 A
2.6 V to 12 V Supply Range
40 C to +85 C Ambient Temperature Range
Ultrasmall Thermally-Enhanced 8-Lead MSOP Package
APPLICATIONS
PCMCIA Card
Cellular Phones
Camcorders, Cameras
Networking Systems, DSL/Cable Modems
Cable Set-Top Box
MP3/CD Players
DSP Supply
anyCAP is a registered trademark of Analog Devices Inc.
V
OUT
ADP3335
NR
OUT
ON
OFF
SD
GND
C
OUT
1 F
+
OUT
OUT
C
IN
1 F
+
V
IN
IN
IN
Figure 1. Typical Application Circuit
GENERAL DESCRIPTION
The ADP3335 is a member of the ADP330x family of precision
low dropout anyCAP voltage regulators. The ADP3335 operates
with an input voltage range of 2.6 V to 12 V and delivers a con-
tinuous load current up to 500 mA. The ADP3335 stands out
from conventional LDOs with the lowest thermal resistance of
any MSOP-8 package and an enhanced process that enables it
to offer performance advantages beyond its competition. Its
patented design requires only a 1.0
F output capacitor for sta-
bility. This device is insensitive to output capacitor Equivalent
Series Resistance (ESR), and is stable with any good quality
capacitor, including ceramic (MLCC) types for space-restricted
applications. The ADP3335 achieves exceptional accuracy of
0.9% at room temperature and 1.8% over temperature, line,
and load. The dropout voltage of the ADP3335 is only 200 mV
(typical) at 500 mA. This device also includes a safety current
limit, thermal overload protection and a shutdown feature. In
shutdown mode, the ground current is reduced to less than
1
A. The ADP3335 has ultralow quiescent current 80 A
(typical) in light load situations.
2
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ADP3335SPECIFICATIONS
1, 2, 3
(V
IN
= 6.0 V, C
IN
= C
OUT
= 1.0 F, T
A
= 40 C to +85 C, unless otherwise noted)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
OUTPUT
Voltage Accuracy
4
V
OUT
V
IN
= V
OUT(NOM)
+ 0.4 V to 12 V
0.9
+0.9
%
I
L
= 0.1 mA to 500 mA
T
A
= 25
C
V
IN
= V
OUT(NOM)
+ 0.4 V to 12 V
1.8
+1.8
%
I
L
= 0.1 mA to 500 mA
T
A
= 85
C
V
IN
= V
OUT(NOM)
+ 0.4 V to 12 V
2.3
+2.3
%
I
L
= 0.1 mA to 500 mA
T
J
= 150
C
Line Regulation
4
V
IN
= V
OUT(NOM)
+ 0.4 V to 12 V
0.04
mV/V
I
L
= 0.1 mA
T
A
= 25
C
Load Regulation
I
L
= 0.1 mA to 500 mA
0.04
mV/mA
T
A
= 25
C
Dropout Voltage
V
DROP
V
OUT
= 98% of V
OUT(NOM)
I
L
= 500 mA
200
370
mV
I
L
= 300 mA
140
230
mV
I
L
= 50 mA
30
110
mV
I
L
= 0.1 mA
10
40
mV
Peak Load Current
I
LDPK
V
IN
= V
OUT(NOM)
+ 1 V
800
mA
Output Noise
V
NOISE
f = 10 Hz100 kHz, C
L
= 10
F
47
V rms
I
L
= 500 mA, C
NR
= 10 nF
f = 10 Hz100 kHz, C
L
= 10
F
95
V rms
I
L
= 500 mA, C
NR
= 0 nF
GROUND CURRENT
In Regulation
I
GND
I
L
= 500 mA
4.5
10
mA
I
L
= 300 mA
2.6
6
mA
I
L
= 50 mA
0.5
2.5
mA
I
L
= 0.1 mA
80
110
A
In Dropout
I
GND
V
IN
= V
OUT(NOM)
100 mV
120
400
A
I
L
= 0.1 mA
In Shutdown
I
GNDSD
SD = 0 V, V
IN
= 12 V
0.01
1
A
SHUTDOWN
Threshold Voltage
V
THSD
ON
2.0
V
OFF
0.4
V
SD Input Current
I
SD
0
SD 5 V
1.2
3
A
Output Current In Shutdown
I
OSD
T
A
= 25
C, V
IN
= 12 V
1.2
5
A
T
A
= 85
C, V
IN
= 12 V
1.2
5
A
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
2
Ambient temperature of 85
C corresponds to a junction temperature of 125C under pulsed full load test conditions.
3
Application stable with no load.
4
V
IN
= 2.6 V to 12 V for models with V
OUT(NOM)
2.2 V.
Specifications subject to change without notice.
ADP3335
3
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ABSOLUTE MAXIMUM RATINGS
*
Input Supply Voltage . . . . . . . . . . . . . . . . . . . 0.3 V to +16 V
Shutdown Input Voltage . . . . . . . . . . . . . . . . 0.3 V to +16 V
Power Dissipation . . . . . . . . . . . . . . . . . . . Internally Limited
Operating Ambient Temperature Range . . . . 40
C to +85C
Operating Junction Temperature Range . . . 40
C to +150C
JA
2-layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
C/W
JA
4-layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
C/W
Storage Temperature Range . . . . . . . . . . . . 65
C to +150C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300
C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 215
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
1, 2, 3
OUT
Output of the Regulator. Bypass to
ground with a 1.0
F or larger capacitor.
All pins must be connected together for
proper operation.
4
GND
Ground Pin.
5
NR
Noise Reduction Pin. Used for further
reduction of output noise (see text for
detail).
Capacitor required if C
OUT
> 3.3
F.
6
SD
Active Low Shutdown Pin. Connect to
ground to disable the regulator output.
When shutdown is not used, this pin
should be connected to the input pin.
7, 8
IN
Regulator Input. All pins must be con-
nected together for proper operation.
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
SD
IN
IN
OUT
ADP3335
NR
OUT
OUT
GND
ORDERING GUIDE
Output
Package
Branding
Model
Voltage
*
Option
Information
ADP3335ARM-1.8
1.8 V
RM-8 (MSOP-8)
LFA
ADP3335ARM-2.5
2.5 V
RM-8 (MSOP-8)
LFC
ADP3335ARM-2.85
2.85 V
RM-8 (MSOP-8)
LFD
ADP3335ARM-3.3
3.3 V
RM-8 (MSOP-8)
LFE
ADP3335ARM-5
5 V
RM-8 (MSOP-8)
LFF
*Contact the factory for other output voltage options.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3335 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ADP3335
4
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INPUT VOLTAGE Volts
OUTPUT VOLTAGE Volts
2.202
2.201
2.194
2
4
12
6
8
10
2.198
2.197
2.196
2.195
2.200
2.199
I
L
= 0
V
OUT
= 2.2V
500mA
150mA
300mA
Figure 2. Line Regulation Output
Voltage vs. Supply Voltage
OUTPUT LOAD mA
GROUND CURRENT
mA
5.0
0
0
100
500
200
300
400
2.0
1.0
4.0
3.0
Figure 5. Ground Current vs. Load
Current
OUTPUT LOAD mA
DROPOUT VOLTAGE
mV
250
200
0
0
100
500
200
300
400
150
100
50
Figure 8. Dropout Voltage vs.
Output Current
Typical Performance Characteristics
OUTPUT LOAD mA
OUTPUT VOLTAGE
Volts
2.201
2.200
2.193
0
100
500
200
300
400
2.197
2.196
2.195
2.194
2.199
2.198
V
OUT
= 2.2V
V
IN
= 6V
Figure 3. Output Voltage vs. Load
Current
JUNCTION TEMPERATURE C
OUTPUT CHANGE
%
1
0.5
40
105
15
5
25
45
65
85
0.6
0.9
0.8
0.7
125
0
0.2
0.1
0.4
0.3
0.2
0.3
0.1
0.4
500mA
0
300mA
0
500mA
Figure 6. Output Voltage Variation %
vs. Junction Temperature
TIME Sec
INPUT/OUTPUT VOLTAGE
Volts
0
0.5
1.0
1.5
2.0
2.5
3.0
1
2
3
4
V
OUT
= 2.2V
SD = V
IN
R
L
= 4.4
Figure 9. Power-Up/Power-Down
INPUT VOLTAGE Volts
GROUND CURRENT
A
140
60
0
0
12
2
4
6
8
10
120
100
40
20
80
V
OUT
= 2.2V
I
L
= 100 A
I
L
= 0
Figure 4. Ground Current vs. Supply
Voltage
JUNCTION TEMPERATURE C
GROUND CURRENT
mA
8
6
40
105
15
5
25
45
65
85
7
125
5
3
4
1
2
0
300mA
0
100mA
I
L
= 500mA
50mA
Figure 7. Ground Current vs. Junction
Temperature
TIME s
0
2
4
0
1
2
3
200
V
OUT
= 2.2V
SD = V
IN
R
L
= 4.4
V
IN
Volts
V
OUT
Volts
C
OUT
= 10 F
C
OUT
= 1 F
400
600
800
Figure 10. PowerUp Response
(T
A
= 25 C unless otherwise noted.)
ADP3335
5
REV. 0
V
OUT
= 2.2V
R
L
= 4.4
C
L
= 1 F
TIME s
3.000
3.500
2.179
2.189
2.190
2.200
2.210
40
80
140
180
V
IN
Volts
V
OUT
Volts
Figure 11. Line Transient Response
V
OUT
= 2.2V
R
L
= 4.4
C
L
= 10 F
TIME s
0
200
400
2.1
2.2
2.3
200
400
600
800
mA
Volts
Figure 14. Load Transient Response
FREQUENCY Hz
RIPPLE REJECTION
dB
10
100
1k
10k
100k
1M
10M
20
30
40
50
60
70
80
90
C
L
= 1 F
I
L
= 500mA
C
L
= 1 F
I
L
= 50 A
C
L
= 10 F
I
L
= 500mA
C
L
= 10 F
I
L
= 50 A
V
OUT
= 2.2V
Figure 17. Power Supply Ripple
Rejection
V
OUT
= 2.2V
R
L
= 4.4
C
L
= 10 F
TIME s
3.000
3.500
2.179
2.189
2.190
2.200
2.210
40
80
140
180
V
IN
Volts
V
OUT
Volts
Figure 12. Line Transient Response
TIME s
0
1
2
0
2.2
200
400
600
800
A
V
olts
V
IN
= 4V
800m
SHORT
FULL SHORT
3
Figure 15. Short Circuit Current
120
160
0
50
10
20
30
40
100
80
60
140
C
L
F
RMS NOISE
V
40
20
0
C
NR
= 10nF
I
L
= 0mA WITH NOISE REDUCTION
I
L
= 0mA WITHOUT
NOISE REDUCTION
I
L
= 500mA WITHOUT
NOISE REDUCTION
I
L
= 500mA WITH
NOISE REDUCTION
Figure 18. RMS Noise vs. C
L
(10 Hz100 kHz)
V
IN
= 4V
V
OUT
= 2.2
C
L
= 1 F
TIME s
200
400
600
800
0
200
400
2.1
2.2
2.3
mA
Volts
Figure 13. Load Transient Response
TIME s
0
2
0
1
200
400
600
800
V
SD
10 F
V
OUT
2
3
V
IN
= 6V
V
OUT
= 2.2V
R
L
= 4.4
1 F
10 F
1 F
Figure 16. Turn OnTurn Off Response
FREQUENCY Hz
VOLTAGE NOISE SPECTRAL
DENSITY
V/ Hz
100
10
100
1M
1k
10k
100k
10
1
0.1
0.01
0.001
V
OUT
= 2.2V
I
L
= 1mA
C
L
= 1 F
C
NR
= 0
C
L
= 10 F
C
NR
= 0
C
L
= 1 F
C
NR
= 10nF
C
L
= 10 F
C
NR
= 10nF
Figure 19. Output Noise Density
ADP3335
6
REV. 0
THEORY OF OPERATION
The new anyCAP
LDO ADP3335 uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider consisting of R1 and R2 which is
varied to provide the available output voltage option. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
PTAT
V
OS
g
m
NONINVERTING
WIDEBAND
DRIVER
INPUT
Q1
ADP3335
COMPENSATION
CAPACITOR
ATTENUATION
(V
BANDGAP
/V
OUT
)
R1
D1
R2
R3
R4
OUTPUT
PTAT
CURRENT
(a)
GND
C
LOAD
R
LOAD
Figure 20. Functional Block Diagram
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that equilibrium pro-
duces a large, temperature-proportional input ,"offset voltage"
that is repeatable and very well controlled. The temperature-
proportional offset voltage is combined with the complementary
diode voltage to form a "virtual bandgap" voltage, implicit in
the network, although it never appears explicitly in the circuit.
Ultimately, this patented design makes it possible to control
the loop with only one amplifier. This technique also improves
the noise characteristics of the amplifier by providing more flex-
ibility on the trade-off of noise sources that leads to a low noise
design.
The R1, R2 divider is chosen in the same ratio as the bandgap
voltage to the output voltage. Although the R1, R2 resistor divider
is loaded by the diode D1 and a second divider consisting of R3
and R4, the values can be chosen to produce a temperature stable
output. This unique arrangement specifically corrects for the load-
ing of the divider thus avoiding the error resulting from base
current loading in conventional circuits.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this spe-
cial noninverting driver enables the frequency compensation
to include the load capacitor in a pole-splitting arrangement
to achieve reduced sensitivity to the value, type, and ESR of
the load capacitance.
Most LDOs place very strict requirements on the range of ESR
values for the output capacitor because they are difficult to stabilize
due to the uncertainty of load capacitance and resistance. More-
over, the ESR value, required to keep conventional LDOs stable,
changes depending on load and temperature. These ESR limita-
tions make designing with LDOs more difficult because of their
unclear specifications and extreme variations over temperature.
With the ADP3335 anyCAP LDO, this is no longer true. It can
be used with virtually any good quality capacitor, with no con-
straint on the minimum ESR. This innovative design allows the
circuit to be stable with just a small 1
F capacitor on the out-
put. Additional advantages of the pole-splitting scheme include
superior line noise rejection and very high regulator gain, which
leads to excellent line and load regulation. An impressive
1.8%
accuracy is guaranteed over line, load, and temperature.
Additional features of the circuit include current limit and ther-
mal shutdown and noise reduction.
APPLICATION INFORMATION
Capacitor Selection
Output Capacitors: as with any micropower device, output
transient response is a function of the output capacitance. The
ADP3335 is stable with a wide range of capacitor values, types
and ESR (anyCAP). A capacitor as low as 1
F is all that is
needed for stability; larger capacitors can be used if high output
current surges are anticipated. The ADP3335 is stable with
extremely low ESR capacitors (ESR
0), such as multilayer
ceramic capacitors (MLCC) or OSCON. Note that the effective
capacitance of some capacitor types may fall below the mini-
mum at cold temperature. Ensure that the capacitor provides
more than 1
F at minimum temperature.
Input Bypass Capacitor
An input bypass capacitor is not strictly required but is advisable
in any application involving long input wires or high source
impedance. Connecting a 1
F capacitor from IN to ground
reduces the circuit's sensitivity to PC board layout. If a larger
value output capacitor is used, then a larger value input capaci-
tor is also recommended.
Noise Reduction
A noise reduction capacitor (C
NR
) can be used to further reduce
the noise by 6 dB10 dB (Figure 18) low leakage capacitors in
10 pF500 pF range provide the best performance. Since the
noise reduction pin (NR) is internally connected to a high imped-
ance node, any connection to this node should be carefully done
to avoid noise pickup from external sources. The pad connected
to this pin should be as small as possible and long PC board
traces are not recommended.
When adding a noise reduction capacitor, maintain a mini-
mum load current of 1 mA when not in shutdown.
ADP3335
7
REV. 0
It is important to note that as C
NR
increases, the turn-on time
will be delayed. With NR values greater than 1 nF, this delay
may be on the order of several milliseconds.
V
IN
V
OUT
ADP3335
ON
OFF
SD
GND
C
OUT
1 F
+
NR
C
N R
OUT
OUT
OUT
IN
IN
C
IN
1 F
+
Figure 21. Typical Application Circuit
Paddle-Under-Lead Package
The ADP3335 uses a patented paddle-under-lead package
design to ensure the best thermal performance in an MSOP-8
footprint. This new package uses an electrically isolated die
attach that allows all pins to contribute to heat conduction.
This technique reduces the thermal resistance to 110
C/W on a
4-layer board as compared to >160
C/W for a standard MSOP-8
leadframe. Figure 22 shows the standard physical construc-
tion of the MSOP-8 and the paddle-under-lead leadframe.
DIE
Figure 22. Thermally Enhanced Paddle-Under-Lead Package
Thermal Overload Protection
The ADP3335 is protected against damage from excessive power
dissipation by its thermal overload protection circuit which limits
the die temperature to a maximum of 165
C. Under extreme
conditions (i.e., high ambient temperature and power dissipation)
where die temperature starts to rise above 165
C, the output
current is reduced until the die temperature has dropped to a
safe level. The output current is restored when the die tempera-
ture is reduced.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, device power dissipation should be externally limited
so that junction temperatures will not exceed 150
C.
Calculating Junction Temperature
Device power dissipation is calculated as follows:
P
V
V
I
V
I
D
IN
OUT
LOAD
IN
GND
=
-
(
)
+
( )
Where I
LOAD
and I
GND
are load current and ground current, V
IN
and V
OUT
are input and output voltages respectively.
Assuming I
LOAD
= 400 mA, I
GND
= 4 mA, V
IN
= 5.0 V and
V
OUT
= 3.3 V, device power dissipation is:
P
D
= (5 3.3) 400 mA + 5.0(4 mA) = 700 mW
The proprietary package used in the ADP3335 has a thermal
resistance of 110
C/W, significantly lower than a standard
MSOP-8 package. Assuming a 4-layer board, the junction tem-
perature rise above ambient temperature will be approximately
equal to:
T
W
C W
C
A
J
=
=
0 700
110
77 0
.
/
.
To limit the maximum junction temperature to 150
C, maxi-
mum allowable ambient temperature will be:
T
AMAX
= 150
C 77.0C = 73.0C
Printed Circuit Board Layout Consideration
All surface mount packages rely on the traces of the PC board to
conduct heat away from the package.
In standard packages the dominant component of the heat resis-
tance path is the plastic between the die attach pad and the
individual leads. In typical thermally enhanced packages one or
more of the leads are fused to the die attach pad, significantly
decreasing this component. To make the improvement mean-
ingful, however, a significant copper area on the PCB must be
attached to these fused pins.
The patented paddle-under-lead frame design of the ADP3335
uniformly minimizes the value of the dominant portion of the
thermal resistance. It ensures that heat is conducted away by all
pins of the package. This yields a very low 110
C/W thermal
resistance for an MSOP-8 package, without any special board
layout requirements, relying only on the normal traces connected
to the leads. This yields a 33% improvement in heat dissipation
capability as compared to a standard MSOP-8 package. The
thermal resistance can be decreased by, approximately, an addi-
tional 10% by attaching a few square cm of copper area to the
IN pin of the ADP3335 package.
It is not recommended to use solder mask or silkscreen on the
PCB traces adjacent to the ADP3335's pins since it will increase
the junction-to-ambient thermal resistance of the package.
Shutdown Mode
Applying a TTL high signal to the shutdown (SD) pin or tying
it to the input pin, will turn the output ON. Pulling SD down to
0.4 V or below, or tying it to ground will turn the output OFF.
In shutdown mode, quiescent current is reduced to much less
than 1
A.
8
C377454/00 (rev. 0)
PRINTED IN U.S.A.
ADP3335
REV. 0
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead mini_SO
(RM-8)
0.011 (0.28)
0.003 (0.08)
0.028 (0.71)
0.016 (0.41)
33
27
0.120 (3.05)
0.112 (2.84)
8
5
4
1
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
PIN 1
0.0256 (0.65) BSC
0.122 (3.10)
0.114 (2.90)
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.018 (0.46)
0.008 (0.20)
0.043 (1.09)
0.037 (0.94)
0.120 (3.05)
0.112 (2.84)
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