ADT7462 Flexible Temperature and Voltage Monitor and System Fan Controller Data Sheet (Rev. 0)

Flexible Temperature and Voltage Monitor

and System Fan Controller

ADT7462

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

FEATURES

One local and up to three remote temperature channels

Series resistance cancellation on remote channels

Thermal protection using THERM pins

Up to four PWM fan drive outputs

Supports both high and low frequency PWM drives

Up to eight TACH inputs

Measures the speed of 3-wire and 4-wire fans

Automatic fan speed control loop

Includes dynamic T

MIN

control

Monitors up to 13 voltage inputs
Monitors up to 7 VID inputs

Includes VID-on-fly support

Bidirectional reset
Chassis intrusion detect
SMBus 1.1- and SMBus 1.0-compatible
3.3 V and 5 V operation
Extended operating range from -40°C to +125°C
Space-saving 32-lead chip scale package

APPLICATIONS

Servers and personal computers
Telecommunications equipment
Test equipment and measurement instruments

GENERAL DESCRIPTION

The ADT7462 is a flexible systems monitor IC, suitable for use
in a wide variety of applications. It can monitor temperature in
up to three remote locations, as well as its ambient temperature.

There are up to four PWM outputs. These can be used to control
the speed of a cooling fan by varying the % duty cycle of the
PWM drive signal applied to the fan. The ADT7462 supports
high frequency PWM for 4-wire fans and low frequency PWM
for 2-wire and 3-wire fans. There are up to eight TACH inputs,
which can be used to measure the speed of 3-wire and 4-wire
fans. There are up to 13 voltage monitoring inputs, ranging
from 12 V to 0.9 V.

The ADT7462 is fully compatible with SMBus 1.1 and SMBus 1.0.
The ADT7462 also includes a THERM I/O and a RESET I/O.

The ADT7462 is available in a 32-lead LFCSP_VQ. Many of the
pins are multifunctional. There are five easy configuration options,
which are set up using the easy configuration register. Users pick
the configuration closest to their requirements; individual pins
can be reconfigured after the easy configuration option has
been chosen.

FUNCTIONAL BLOCK DIAGRAM

SMBus

ADDRESS

SELECTION

SERIAL BUS

INTERFACE

VID

REGISTER

PWM REGISTERS

ADDRESS POINTER

REGISTER

PWM

CONFIGURATION

REGISTERS

INTERRUPT

MASKING

RESET

CIRCUIT

GPIO STATUS AND

CONFIGURATION

REGISTERS

SCSI STATUS

PERFORMANCE

MONITORING

THERMAL

PROTECTION

INPUT SIGNAL

CONDITIONING

AND ANALOG

MULTIPLEXER

BAND GAP

TEMPERATURE

SENSOR

VID0 TO VID6

PWM1 TO PWM4

TACH1 TO TACH8

VR_HOT2

SCSI_TERM1 AND
SCSI_TERM2

VR_HOT1

THERM2

THERMAL DIODE INPUTS

VOLTAGE INPUTS

ADT7462

VALUE AND LIMIT

REGISTERS

LIMIT

COMPARATORS

INTERRUPT

STATUS

REGISTERS

AUTOMATIC

FAN SPEED

CONTROL

ACOUSTIC

ENHANCEMENT

CONTROL

DYNAMIC T

MIN

CONTROL

13-BIT

ADC

BAND GAP

REFERENCE

GPIO1 TO GPIO8

RESET

GND

SMBus

ADDRESS

SCL SDA

ALERT

FAN SPEED

COUNTER

569

-
00

FAN2MAX

THERM1

Figure 1.

ADT7462

Rev. 0 | Page 2 of 92

TABLE OF CONTENTS

Features ...................................................................................... 1

Applications............................................................................... 1

General Description ................................................................. 1

Functional Block Diagram ...................................................... 1

Revision History ....................................................................... 3

Specifications............................................................................. 4

Timing Diagram ................................................................... 5

Absolute Maximum Ratings.................................................... 6

Thermal Resistance .............................................................. 6

ESD Caution.......................................................................... 6

Pin Configuration and Function Descriptions..................... 7

Functional Description: Easy Configuration Options ..10

Typical Performance Characteristics ...................................15

Serial Bus Interface.................................................................18

ADD Input...........................................................................18

SMBus Fixed Address ........................................................ 18

SMBus Operation ...............................................................18

Write Operations ................................................................20

Read Operations .................................................................21

Alert Response Address.....................................................22

SMBus Timeout ..................................................................22

Temperature and Voltage Measurement..............................23

Temperature Measurement ...............................................23

Series Resistance Cancellation..........................................24

Voltage Measurement ........................................................ 26

Battery Measurement Input (V

BATT

).................................28

ADC Information...............................................................29

Dynamic VID Monitoring ....................................................30

VID Code ............................................................................ 30

Dynamic VID Monitoring ................................................30

Status and Mask Registers and ALERT................................32

Fan Control.............................................................................. 33

Fan Drive Using PWM Control........................................33

Fan Speed Measurement and Control..................................35

TACH Inputs .......................................................................35

Fan Speed Measurement....................................................35

PWM Logic State ................................................................37

Fan Speed Control ..............................................................37

Programming the Automatic Fan Speed Control Loop 39

Step 1--Configuring the MUX.........................................40

Step 2--T

MIN

Settings for Thermal Calibration Channels . 40

Step 3--PWM

MIN

for Each PWM (Fan) Output.............42

Step 4--PWM

MAX

for PWM (Fan) Outputs ....................42

Step 5--T

RANGE

for Temperature Channels ......................43

Step 6--T

THERM

for Temperature Channels......................46

Step 7--T

HYST

for Temperature Channels ........................47

Dynamic T

MIN

Control Programming .............................49

Step 8--Operating Points for Temperature Channels ...49

Step 9--High and Low Limits for Temperature Channels 49

Step 10--Monitoring THERM..........................................52

Enhancing System Acoustics.............................................52

Step 11--Ramp Rate for Acoustic Enhancement ...........54

Fan Freewheeling Test Mode.............................................56

THERM I/O Operation .........................................................57

General-Purpose I/O Pins .....................................................59

EDO Circuitry.....................................................................59

Other Digital Inputs ...........................................................60

Reset I/O ..............................................................................60

Chassis Intrusion Input......................................................60

Power-Up Sequence................................................................61

XOR Tree Test..........................................................................62

Outline Dimensions ...............................................................90

Ordering Guide...................................................................90

ADT7462

Rev. 0 | Page 4 of 92

SPECIFICATIONS

= T

MIN

to T

MAX

, V

= V

MIN

to V

MAX

, unless otherwise noted.

Table 1.

Parameter Min

Typ

Max

Unit

Test

Conditions/Comments

POWER SUPPLY

Supply Voltage

3.0

3.3

5.5

Supply Current

1.5

ADC active, interface inactive

TEMPERATURE-TO-DIGITAL CONVERTER

Conditions

Internal Sensor, T

, Accuracy

±0.5

±2.25

°C

0 T

85°C

3 V V

3.6 V

±0.5

±3.25

°C

-40

+100°C

3 V V

3.6 V

±0.5

±3

°C

85°C

4.5 V V

5.5 V

±0.5

±4

°C

-40

+100°C

4.5 V V

5.5 V

Resolution

0.25

°C

Remote Sensor, T

, Accuracy (-40 T

+125°C)

±0.5

±2.25

°C

0 T

85°C

3 V V

3.6 V

±0.5

±3.25

°C

-40

+100°C

3 V V

3.6 V

±0.5

±2.75

°C

85°C

4.5 V V

5.5 V

±0.5

±3.5

°C

-40

+100°C

4.5 V V

5.5 V

Resolution

0.25

°C

Remote Sensor Source Current

High

level

Mid

level

Low

level

Series Resistance Cancellation

The ADT7462 cancels 2 k in series with the
remote thermal diode

ANALOG-TO-DIGITAL CONVERTER

Total Unadjusted Error, TUE

4, 5

±3.5

Differential Nonlinearity, DNL

±1

LSB

8 bits

Conversion Time (Voltage Input)

8.53

9.86

Conversion Time (Local Temperature)

9.01

10.38

Conversion Time (Remote Temperature)

38.36

42.09

INPUT RESISTANCE

Pin 7, Pin 8, Pin 13, Pin 21, Pin 22, Pin 25, Pin 28,

Pin 29

140

Attenuators

enabled

Pin 15, Pin 19

225

Attenuators enabled

Pin 23, Pin 24

Attenuators enabled

Pin 26, V

BATT

and +1.2V (When Measured)

100

120

140

Attenuators cannot be disabled

BATT

Current Drain (When Measured)

100

CR2032 battery life > 10 years

BATT

Current Drain (When Not Measured)

CR2032 battery life > 10 years

FAN RPM TO DIGITAL CONVERTER

Accuracy

±8

Internal Clock Frequency

82.8

97.2

kHz

OPEN DRAIN OUTPUTS (PWM, GPIO)

High Level Output Leakage Current, I

0.1

±1

OUT

= V

Output Low Voltage, V

0.4

OUT

= -3 mA, V

= +3.3 V

DIGITAL OUTPUT (RESET, ALERT, THERM)

Output Low Voltage, V

0.4

OUT

= -3 mA, V

= +3.3 V

RESET Pulse Width

140 180

RESET Threshold

3 3.05

3.1

Falling

voltage

RESET Hysteresis

OPEN DRAIN SERIAL BUS OUTPUT (SDA)

Output Low Voltage, V

0.4

OUT

= -3 mA, V

= +3.3 V

High Level Output Leakage Current

, I

0.1

±1

OUT

= V

ADT7462

Rev. 0 | Page 5 of 92

Parameter Min

Typ

Max

Unit

Test

Conditions/Comments

SERIAL BUS DIGITAL INPUTS (SDA AND SCL)

Input High Voltage, V

2.1

Input Low Voltage, V

0.4

Hysteresis

500

DIGITAL INPUT LOGIC LEVELS (VID0 to VID6) AND
THERM, TACH, GPIO, VR_HOT, SCSI_TERM)

Input High Voltage, V

1.7

Bit 3 and Bit 4 of Configuration Register 3 = 0

Input Low Voltage, V

0.8

Bit 3 and Bit 4 of Configuration Register 3 = 0

Input High Voltage, V

(VID0 to VID6)

0.65

Bit 3 of Configuration Register 3 = 1

Input High Voltage, V

(THERM)

2/3 V

CCP1

Bit 4 of Configuration Register 3 = 1

Input Low Voltage, V

0.4

Bit 3 and Bit 4 of Configuration Register 3 = 1

Hysteresis

500

DIGITAL INPUT CURRENTS

Input High Current, I

-1

= V

Input Low Current, I

= 0

Input Capacitance

SERIAL BUS TIMING

Clock Frequency

400

kHz

See Figure 2

Glitch Immunity, t

See

Figure 2

Bus Free Time

1.3

See Figure 2

Start Setup Time, t

SU;STA

0.6

See

Figure 2

Start Hold Time, t

HD;STA

0.6

See

Figure 2

SCL Low Time, t

LOW

1.3

See

Figure 2

SCL High Time, t

HIGH

0.6

See

Figure 2

SCL, SDA Rise Time, t

1000

See

Figure 2

SCL, SDA Fall Time, t

300

See

Figure 2

Data Setup Time, t

SU;DAT

100

See

Figure 2

Detect Clock Low Timeout

Can be optionally enabled

All voltages are measured with respect to GND, unless otherwise specified. Typical values are at T

= 25°C and represent the most likely parametric norm. Logic inputs

accept input high voltages up to 5 V, even when the device is operating at supply voltages below 5 V. Timing specifications are tested at logic levels of V

= 0.8 V for a

falling edge and V

= 2.0 V for a rising edge.

Unused digital inputs connected to GND.

Guaranteed by design, not production tested.

Note that this specification does not apply if Pin 26 (V

BATT

, +1.2V) is being measured in single-channel mode. See Figure 22 in Typical Performance Characteristics for

BATT

accuracy.

For Pin 23 and Pin 24 configured as +1.8V or +2.5V only, restricted conditions of V

3.3 V and +25°C T

+125°C apply.

TIMING DIAGRAM

SCL

SDA

SU;STO

HD;STA

SU;STA

SU;DAT

HD;DAT

HD;STA

HIGH

BUF

LOW

Figure 2. Serial Bus Timing Diagram

ADT7462

Rev. 0 | Page 6 of 92

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage

6.5 V

Voltage on +12V Pin

20 V

Voltage on V

BATT

4 V

Voltage on Any Other Input or

Output Pin

-0.3 V to +6.5 V

Input Current at Any Pin

±5 mA

Package Input Current

±20 mA

Maximum Junction Temperature

150°C

Operating Temperature Range

-40°C to +125°C

Storage Temperature Range

-65°C to +150°C

Lead Temperature

(Soldering 10 sec)

300°C

IR Reflow Peak Temperature

260°C

ESD Rating

1500 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

is specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type

Unit

32-Lead LFCSP_VQ

32.5

32.71

°C/W

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

ADT7462

Rev. 0 | Page 7 of 92

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

VID0/GPIO1/TACH1

VID1/GPIO2/TACH2

VID2/GPIO3/TACH3

VID3/GPIO4/TACH4

GND

TACH5/+12V1

TACH6/+12V2

CCP2

/+1.5V/+1.8V/+2.5V

CCP1

/+1.5V/+1.8V/+2.5V

TACH8/+12V3

TACH7/+5V

D3/SCSI_TERM2

D3+/+1.25V/+0.9V

D2

D2+

1
0

1
1

1
2

1
3

4
/
+

3
.
3
V

1
4

1
5

1
+

/
+

2
.
5
V

/
+

1
.
8
V

1
6

1

/
S

I
_
T

3
2

I
D

5
/
G

I
O

6
/
P

3
1

I
D

4
/
G

I
O

5
/
P

3
0

2
9

2
/
+

1
.
5
V

2
/
G

I
O

2
8

1
/
+

1
.
5
V

1
/
G

I
O

7
/
V

I
D

2
7

2
M

/
C

2
6

_
H

2
/
+

1
.
2
V

/
V

2
5

ADT7462

TOP VIEW

(Not to Scale)

-
00

_
H

1
/
+

1
.
2
V

/
+

3
.
3
V

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin
No.

Mnemonic Description

POR
Default

1 VID0/GPIO1/TACH1

VID0: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to
the VID value register (0x97).

TACH1

GPIO1: Open Drain I/O. General-purpose input/output.

TACH1: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1.

2 VID1/GPIO2/TACH2

VID1: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to
the VID value register (0x97).

TACH2

GPIO2: Open Drain I/O. General-purpose input/output.

TACH2: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2.

3 VID2/GPIO3/TACH3

VID2: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to
the VID value register (0x97).

TACH3

GPIO3: Open Drain I/O. General-purpose input/output.

TACH3: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3.

4 VID3/GPIO4/TACH4

VID3: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to
the VID value register (0x97).

TACH4

GPIO4: Open Drain I/O. General-purpose input/output.

TACH4: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4.

5 V

Power Supply. Can be powered by 3.3 V standby if monitoring in low power states is
required. The ADT7462 can also be powered from a 5 V supply.

6 GND

Ground

Pin.

GND

TACH5/+12V1

TACH5: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 5.

TACH5

+12V1: Analog Input. Monitors 12 V power supply (#1). Attenuators switched on by default.

TACH6/+12V2

TACH6: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 6.

TACH6

+12V2: Analog Input. Monitors 12 V power supply (#2). Attenuators switched on by default.

SCL

Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up.

SCL

SDA

Digital I/O (Open Drain). SMBus bidirectional serial data. Requires SMBus pull-up.

SDA

ADD

The state of this pin on power-up determines the SMBus device address.

ADD

ALERT

Active Low Digital Output. The ALERT pin is used to signal out-of-limit comparisons of
temperature, voltage, and fan speed. This is compatible with SMBus ALERT.

ALERT

ADT7462

Rev. 0 | Page 8 of 92

Pin
No. Mnemonic

Description

POR
Default

13 PWM4/+3.3V

PWM4: Digital Output (Open Drain). Requires 10 k typical pull-up. Pulse width modulated
output to control the speed of Fan 4.

PWM4

+3.3V: Analog Input. Monitors 3.3 V power supply.

RESET

Active Low Open Drain Digital I/O. Power-on reset, 5 mA driver (weak 100 k

pull-up), active

low output (100 k

pull-up) with a 180 ms typical pulse width. RESET is asserted whenever

is below the reset threshold. It remains asserted for approximately 180 ms after V

rises

above the reset threshold. Pin 14 also functions as an active low RESET input and resets all
unlocked registers to their default values.

RESET

D1+/+2.5V/+1.8V

D1+: Anode Connection to Thermal Diode 1.

D1+

+2.5V: Monitors 2.5 V analog input.

+1.8V: Monitors 1.8 V analog input.

D1-/SCSI_TERM1

D1-: Cathode Connection to Thermal Diode 1.

D1-

SCSI_TERM1: Digital Input, SCSI Termination 1.

D2+

Anode Connection to Thermal Diode 2.

D2+

D2-

Cathode Connection to Thermal Diode 2.

D2-

D3+/+1.25V/+0.9V

D3+: Anode Connection to Thermal Diode 3.

D3+

+1.25V: Monitors 1.25 V analog input.

+0.9V: Monitors 0.9 V analog input.

D3-/SCSI_TERM2

D3-: Cathode connection to Thermal Diode 3.

D3-

SCSI_TERM2: Digital Input, SCSI Termination 2.

TACH7/+5V

TACH7: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 7.

TACH7

+5V: Analog Input. Monitors 5 V power supply.

TACH8/+12V3

TACH8: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 8.

TACH8

+12V3: Analog Input. Monitors 12 V power supply (#3).

23 V

CCP1

/+1.5V/+1.8V/+2.5V V

CCP1

: Monitors 1.2 V analog input.

+1.8V

+1.5V: Monitors 1.5 V analog input.

+1.8V: Monitors 1.8 V analog input.

+2.5V: Monitors 2.5 V analog input.

24 V

CCP2

/+1.5V/+1.8V/+2.5V V

CCP2

: Monitors 1.2 V analog input.

+2.25V

+1.5V: Monitors 1.5 V analog input.

+1.8V: Monitors 1.8 V analog input.

+2.5V: Monitors 2.5 V analog input.

VR_HOT1/+1.2V/+3.3V

VR_HOT1: Digital Input Indicating Overtemperature Event on Voltage Regulator.

+3.3V

+1.2V1: 0 V to 1.2 V Analog Input. For example, can be used to monitor G

BIT

+3.3V: Analog Input. Monitors +3.3 V power supply.

26 VR_HOT2/+1.2V/V

BATT

VR_HOT2: Digital Input Indicating Overtemperature Event on Voltage Regulator.

BATT

+1.2V2: 0 V to 1.2 V Analog Input. For example, can be used to monitor FSB_V

BATT

: Analog Input. Monitors battery voltage, nominally 3 V.

FAN2MAX/CI FAN2MAX: Sets fan to maximum speed when a fan fault condition occurs. Bidirectional open

drain, active low I/O.

CI: An active high input that captures a chassis intrusion event in Bit 6 of the digital status
register. This bit remains set until cleared, as long as battery voltage is applied to the V

BATT

input, even when the ADT7462 is powered off.

THERM1/+1.5V1/GPIO7/
VID6

THERM1: Can be reconfigured as a bidirectional THERM pin. Can be connected to PROCHOT
output of the Intel® Pentium 4 processor to time and monitor PROCHOT assertions. Can be
used as an output to signal overtemperature conditions or for clock modulation purposes.

THERM1

+1.5V1: 0 V to 1.5 V Analog Input. Can be used to monitor ICH.

GPIO7: Open Drain I/O. General-purpose input/output.

VID6: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to
the VID value register (0x97).

ADT7462

Rev. 0 | Page 9 of 92

Pin
No. Mnemonic

Description

POR
Default

THERM2/+1.5V2/GPIO8

THERM2: Can be reconfigured as a bidirectional THERM pin. Can be connected to PROCHOT
output of the Intel Pentium 4 processor to time and monitor PROCHOT assertions. Can be
used as an output to signal overtemperature conditions or for clock modulation purposes.

THERM2

+1.5V2: 0 V to 1.5 V Analog Input. Can be used to monitor 3GIO.

GPIO8: Open Drain I/O. General-purpose input/output.

30 PWM3

Digital Output (Open Drain). Requires 10 k typical pull-up. Pulse width modulated output
to control speed of Fan 3.

PWM3

31 VID4/GPIO5/PWM1

VID4: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to
the VID value register (0x97).

PWM1

GPIO5: Open Drain I/O. General-purpose input/output.

PWM1: Digital Output (Open Drain). Requires 10 k typical pull-up. Pulse-width modulated
output to control the speed of Fan 1.

32 VID5/GPIO6/PWM2

VID5: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to
the VID value register (0x97).

PWM2

GPIO6: Open Drain I/O. General-purpose input/output.

PWM2: Digital Output (Open Drain). Requires 10 k typical pull-up. Pulse width modulated
output to control the speed of Fan 2.

ADT7462

Rev. 0 | Page 10 of 92

FUNCTIONAL DESCRIPTION:
EASY CONFIGURATION OPTIONS

There are a number of multifunctional pins on the ADT7462
that need to be configured on power-up to suit the desired
application. Note that due to the large number of pins that need
to be configured, it could take several SMBus transactions to
achieve the required configuration. For this reason, the ADT7462
has five easy configuration options. The user sets a bit in the
easy configuration option register (0x14) to set up the required
configuration (see Table 5).

Table 5. Easy Configuration Register Settings

Easy Configuration Option

Register 0x14 Setting

Option 1

Bit 0 = 1

Option 2

Bit 1 = 1

Option 3

Bit 2 = 1

Option 4

Bit 3 = 1

Option 5

Bit 4 = 1

Once the most convenient easy configuration option has been
set, the user can configure any of the pins individually. The
setup complete bit (Bit 5 of Register 0x01) must then be set to 1
to indicate that the ADT7462 is configured correctly, and then
monitoring of the selected channels begins.

The following is a detailed description of the five easy
configuration options that are available.

Configuration Option 1

Configuration Option 1 is the default configuration. It is also
the most suitable for thermal monitoring, voltage monitoring,
and fan control for single and dual processor systems.

Features of Configuration Option 1 include the following:

One local and three remote temperature channels

Four PWM drives and eight TACH inputs

Two THERM I/Os

Voltage monitoring

+3.3V
+2.5V
+1.8V
V

BATT

RESET I/O

CI (chassis intrusion) or FAN2MAX

Figure 4 shows the pin configuration when Configuration
Option 1 is chosen.

PIN 1

INDICATOR

TACH1

TACH2

TACH3

TACH4

GND

TACH5

TACH6

+2.5V

+1.8V

TACH8

TACH7

D3

D3+

D2

D2+

1
0

1
1

1
2

1
3

1
4

1
5

1
+

1
6

3
2

3
1

3
0

2
9

2
8

2
7

2
6

2
5

3
.
3
V

ADT7462

TOP VIEW

(Not to Scale)

Figure 4. Configuration Option 1

Table 6. Configuration Option 1

Pin Function Configuration

Register

Bit

Value

TACH1

Pin Configuration Register 1

Bit 4 = 1

TACH2

Pin Configuration Register 1

Bit 3 = 1

TACH3

Pin Configuration Register 1

Bit 2 = 1

TACH4

Pin Configuration Register 1

Bit 1 = 1

TACH5

Pin Configuration Register 1

Bit 0 = 1

TACH6

Pin Configuration Register 2

Bit 7 = 1

PWM4

Pin Configuration Register 2

Bit 6 = 1

D1+

Pin Configuration Register 1

Bit 6 = 1

D1-

Pin Configuration Register 1

Bit 6 = 1

D3+

Pin Configuration Register 1

Bit 5 = 1

D3-

Pin Configuration Register 1

Bit 5 = 1

TACH7

Pin Configuration Register 2

Bit 3 = 1

TACH8

Pin Configuration Register 2

Bit 2 = 1

+1.8V

Pin Configuration Register 2

Bits [1:0] = 10

+2.5V

Pin Configuration Register 3

Bits [7:6] = 01

+3.3V

Pin Configuration Register 3

Bits [5:4] = 00

26 V

BATT

Pin Configuration Register 3

Bits [3:2] = 00

Pin Configuration Register 3

Bit 1 = 1

THERM1

Pin Configuration Register 4

Bits [7:6] = 1×

THERM2

Pin Configuration Register 4

Bits [5:4] = 1×

PWM1

Pin Configuration Register 4

Bit 3 = 1

PWM2

Pin Configuration Register 4

Bit 2 = 1

If VIDs are selected, these pins are configured as VIDs. To enable VIDs, set Bit

of Pin Configuration Register 1 (0x10) = 1.

ADT7462

Rev. 0 | Page 11 of 92

Configuration Option 2

Configuration Option 2 is used for thermal monitoring and fan
control for Processor 1 and Processor 2 in a dual processor
system. It can also monitor one set of VIDs, if required.

Features of Configuration Option 2 include the following:

One local and three remote thermal channels

Up to four PWM drives and up to eight TACH inputs

(VID pins and TACHs/PWMs are MUX'd together)

Two THERM I/Os

· Two VRD inputs

RESET I/O

Two V

CCP

voltage monitoring channels

Figure 5 shows the pin configuration when Configuration
Option 2 is chosen.

PIN 1

INDICATOR

TACH1

TACH2

TACH3

TACH4

GND

TACH5

TACH6

CCP2

CCP1

TACH8

TACH7

D3

D3+

D2

D2+

1
0

1
1

1
2

1
3

1
4

1
5

1
+

1
6

3
2

3
1

3
0

2
9

2
8

2
7

2
M

2
6

_
H

2
5

_
H

ADT7462

TOP VIEW

(Not to Scale)

Figure 5. Configuration Option 2

Table 7. Configuration Option 2

Pin Function Configuration

Register

Bit

Value

TACH1

Pin Configuration Register 1

Bit 4 = 1

TACH2

Pin Configuration Register 1

Bit 3 = 1

TACH3

Pin Configuration Register 1

Bit 2 = 1

TACH4

Pin Configuration Register 1

Bit 1 = 1

TACH5

Pin Configuration Register 1

Bit 0 = 1

TACH6

Pin Configuration Register 2

Bit 7 = 1

PWM 4

Pin Configuration Register 2

Bit 6 = 1

D1+

Pin Configuration Register 1

Bit 6 = 1

D1-

Pin Configuration Register 1

Bit 6 = 1

D3+

Pin Configuration Register 1

Bit 5 = 1

D3-

Pin Configuration Register 1

Bit 5 = 1

TACH7

Pin Configuration Register 2

Bit 3 = 1

TACH8

Pin Configuration Register 2

Bit 2 = 1

23 V

CCP1

Pin Configuration Register 2

Bits [1:0] = 00

24 V

CCP2

Pin Configuration Register 3

Bits [7:6] = 00

VR_HOT1

Pin Configuration Register 3

Bits [5:4] = 1×

VR_HOT2

Pin Configuration Register 3

Bits [3:2] = 1×

FAN2MAX

Pin Configuration Register 3

Bit 1 = 0

THERM1

Pin Configuration Register 4

Bits [7:6] = 1×

THERM2

Pin Configuration Register 4

Bits [5:4] = 1×

PWM1

Pin Configuration Register 4

Bit 3 = 1

PWM2

Pin Configuration Register 4

Bit 2 = 1

If VIDs are selected, these pins are configured as VIDs. To enable VIDs,

set Bit 7 of Pin Configuration Register 1 (0x01) = 1.

ADT7462

Rev. 0 | Page 12 of 92

Configuration Option 3

Configuration Option 3 is chosen when the user wants to
monitor all the voltages in the system for Processor 1 and
Processor 2. Additional pins can be configured for fan control,
VIDs, or GPIOs, as required.

Features of Configuration Option 3 include the following:

· Up to 13 different voltages monitored

Three +12V
+5V
+3.3V
+2.5V
Mem_Core (+1.8V or +2.5V)
Two +1.5V (3GIO and ICH)
+1.2V (V

CCP1

, V

CCP2

, V

CCP

, G

BIT

)

Mem_V

(0.984 V)

BATT

One local and one remote temperature channels

Up to three PWM drives and up to four TACH inputs

RESET I/O

Figure 6 shows the pin configuration when Configuration
Option 3 is chosen.

PIN 1

INDICATOR

TACH1

TACH2

TACH3

TACH4

GND

+12V1

+12V2

CCP2

CCP1

+12V3

+5V

SCSI_TERM2

+0.9V

D2

D2+

1
0

1
1

1
2

1
3

3
.
3
V

1
4

1
5

1
.
8
V

1
6

I
_
T

3
2

3
1

3
0

2
9

1
.
5
V

/
G

I
O

2
8

1
.
5
V

/
G

I
O

2
7

2
6

2
5

1
.
2
V

ADT7462

TOP VIEW

(Not to Scale)

556

Figure 6. Configuration Option 3

Table 8. Configuration Option 3

Pin Function

Configuration

Register

Bit

Value

TACH1

Pin Configuration Register 1

Bit 4 = 1

TACH2

Pin Configuration Register 1

Bit 3 = 1

TACH3

Pin Configuration Register 1

Bit 2 = 1

TACH4

Pin Configuration Register 1

Bit 1 = 1

+12V1

Pin Configuration Register 1

Bit 0 = 0

+12V2

Pin Configuration Register 2

Bit 7 = 0

+3.3V

Pin Configuration Register 2

Bit 6 = 0

+1.8V

Pin Configuration Register 1

Bit 6 = 0

SCSI_TERM1

Pin Configuration Register 1

Bit 6 = 0

+0.9V

Pin Configuration Register 1

Bit 5 = 0

SCSI_TERM2

Pin Configuration Register 1

Bit 5 = 0

+5V

Pin Configuration Register 2

Bit 3 = 0

+12V3

Pin Configuration Register 2

Bit 2 = 0

23 V

CCP1

Pin Configuration Register 2

Bits [1:0] = 00

24 V

CCP2

Pin Configuration Register 3

Bits [7:6] = 00

+1.2V

Pin Configuration Register 3

Bits [5:4] = 01

26 V

BATT

Pin Configuration Register 3

Bits [3:2] = 00

Pin Configuration Register 3

Bit 1 = 1

+1.5V/GPIO7

Pin Configuration Register 4

Bits [7:6] = 01

+1.5V/GPIO8

Pin Configuration Register 4

Bits [5:4] = 01

PWM1

Pin Configuration Register 4

Bit 3 = 1

PWM2

Pin Configuration Register 4

Bit 2 = 1

If VIDs are selected, these pins are configured as VIDs. To enable VIDs, set Bit

of Pin Configuration Register 1 (0x01) = 1.

ADT7462

Rev. 0 | Page 13 of 92

Configuration Option 4

Configuration Option 4 is chosen when the user wants to
monitor temperature, voltages, and fans for Processor 1 in
a dual processor system.

Features of Configuration Option 4 include the following:

One local and two remote temperature channels

Up to four PWM drives and six TACH inputs

Up to eight voltages monitored

+12V
+5V
+3.3V
Two +1.5V
+1.2V (V

CCP1

)

+0.984V (Mem_V

)

BATT

THERM I/O

VRD input

RESET I/O

Figure 7 shows the pin configuration when Configuration
Option 4 is chosen.

PIN 1

INDICATOR

TACH1

TACH2

TACH3

TACH4

TACH5

TACH6

+2.5V

CCP1

+12V3

+5V

SCSI_TERM2

+0.9V

1
0

1
1

1
2

1
3

1
4

1
5

1
+

1
6

3
2

3
1

3
0

2
9

2
/
+

1
.
5
V

2
8

1
/
+

1
.
5
V

2
7

2
M

2
6

2
5

_
H

ADT7462

TOP VIEW

(Not to Scale)

GND

D2
D2+

-
01

Figure 7. Configuration Option 4

Table 9. Configuration Option 4

Pin Function Configuration

Register Bit

Value

TACH1

Pin Configuration Register 1

Bit 4 = 1

TACH2

Pin Configuration Register 1

Bit 3 = 1

TACH3

Pin Configuration Register 1

Bit 2 = 1

TACH4

Pin Configuration Register 1

Bit 1 = 1

TACH5

Pin Configuration Register 1

Bit 0 = 1

TACH6

Pin Configuration Register 2

Bit 7 = 1

PWM4

Pin Configuration Register 2

Bit 6 = 1

D1+

Pin Configuration Register 1

Bit 6 = 1

D1-

Pin Configuration Register 1

Bit 6 = 1

+0.9V

Pin Configuration Register 1

Bit 5 = 0

SCSI_TERM2

Pin Configuration Register 1

Bit 5 = 0

+5V

Pin Configuration Register 2

Bit 3 = 0

+12V3

Pin Configuration Register 2

Bit 2 = 0

23 V

CCP1

Pin Configuration Register 2

Bits [1:0] = 00

+2.5V

Pin Configuration Register 3

Bits [7:6] = 01

VR_HOT1

Pin Configuration Register 3

Bits [5:4] = 1×

26 V

BATT

Pin Configuration Register 3

Bits [3:2] = 00

FAN2MAX

Pin Configuration Register 3

Bit 1 = 0

1, 2

THERM1/
+1.5V

Pin Configuration Register 4

See
Table 51

THERM2/
+1.5V

Pin Configuration Register 4

See
Table 51

PWM1

Pin Configuration Register 4

Bit 3 = 1

PWM2

Pin Configuration Register 4

Bit 2 = 1

If VIDs are selected, these pins are configured as VIDs. To enable VIDs, set

Bit 7 of Pin Configuration Register 1 (0x01) = 1.

It is not possible to monitor +1.5V monitoring on Pin 29 and THERM1 on

Pin 28. Pin 28 and Pin 29 must BOTH be configured as either +1.5V moni-
toring or as THERM I/O (see Table 51).

ADT7462

Rev. 0 | Page 14 of 92

Configuration Option 5

Configuration Option 5 is chosen when the user wants to
monitor temperature, voltages, and fans for Processor 2 in
a dual processor system.

Features of Configuration Option 5 include the following:

One local and two remote temperature channels

Up to three PWM drives and up to six TACHs

Voltage monitoring

Two +12V
+3.3V
Mem_Core (+1.969V)
+1.8 V
Two +1.5V
+1.2V (V

CCP2

)

RESET I/O

Figure 8 shows the pin configuration when Configuration
Option 5 is chosen.

2
/
+

1
.
5
V

1
/
+

1
.
5
V

PIN 1

INDICATOR

TACH1

TACH2

TACH3

TACH4

+12V1

+12V2

CCP2

+1.8V

TACH8

TACH7

D3

D3+

1
0

1
1

1
2

1
3

3
.
3
V

1
4

1
5

2
.
5
V

1
6

I
_
T

3
2

3
1

3
0

2
9

2
8

2
7

2
M

2
6

_
H

2
5

1
.
2
V

ADT7462

TOP VIEW

(Not to Scale)

GND

D2
D2+

556

Figure 8. Configuration Option 5

Table 10. Configuration Option 5

Pin Function Configuration

Register Bit

Value

TACH1

Pin Configuration Register 1

Bit 4 = 1

TACH2

Pin Configuration Register 1

Bit 3 = 1

TACH3

Pin Configuration Register 1

Bit 2 = 1

TACH4

Pin Configuration Register 1

Bit 1 = 1

+12V1

Pin Configuration Register 1

Bit 0 = 0

+12V2

Pin Configuration Register 2

Bit 7 = 0

+3.3V

Pin Configuration Register 2

Bit 6 = 0

+2.5V

Pin Configuration Register 1

Bit 6 = 0

SCSI_TERM1

Pin Configuration Register 1

Bit 6 = 0

D3+

Pin Configuration Register 1

Bit 5 = 1

D3-

Pin Configuration Register 1

Bit 5 = 1

TACH7

Pin Configuration Register 2

Bit 3 = 1

TACH8

Pin Configuration Register 2

Bit 2 = 1

+1.8V

Pin Configuration Register 2

Bits [1:0] = 10

24 V

CCP2

Pin Configuration Register 3

Bits [7:6] = 00

+1.2V

Pin Configuration Register 3

Bits [5:4] = 01

VR_HOT2

Pin Configuration Register 3

Bits [3:2] = 1×

FAN2MAX

Pin Configuration Register 3

Bit 1 = 0

1, 2

THERM1/
+1.5V

Pin Configuration Register 4

See
Table 51

THERM2/
+1.5V

Pin Configuration Register 4

See
Table 51

PWM1

Pin Configuration Register 4

Bit 3 = 1

PWM2

Pin Configuration Register 4

Bit 2 = 1

If VIDs are selected, these pins are configured as VIDs. To enable VIDs, set

Bit 7 of Pin Configuration Register 1 (0x01) = 1.

It is not possible to monitor +1.5V monitoring on Pin 28 and THERM2 on

Pin 29. Pin 28 and Pin 29 must BOTH be configured as either +1.5V
monitoring or as THERM I/O. See Table 51 for more information.

ADT7462

Rev. 0 | Page 15 of 92

TYPICAL PERFORMANCE CHARACTERISTICS

0.00160

0.00125

2.9

3.4

3.9

4.4

4.9

5.4

569

-
003

SUPPLY VOLTAGE (V)

s
)

DEV1

DEV2

DEV3

0.00155

0.00150

0.00145

0.00140

0.00135

0.00130

Figure 9. Supply Current vs. Supply Voltage

0.00144

0.00122

45

105

055

69-

TEMPERATURE (°C)

s
)

0.00142

0.00140

0.00138

0.00136

0.00134

0.00132

0.00130

0.00128

0.00126

0.00124

DEV1

DEV2

DEV3

Figure 10. Supply Current vs. Temperature

40

20

100

120

TEMPERATURE (°C)

RAT

URE

RRO

(
°
C)

= 5.5V

= 3.3V

Figure 11. Local Sensor Temperature Error

40

20

100

120

TEMPERATURE (°C)

RAT

URE

RRO

(
°
C)

= 3.3V

= 5.5V

Figure 12. Remote Sensor Temperature Error

40

20

100

120

TEMPERATURE (°C)

RAT

URE

RRO

(
°
C)

MEAN

LO SPEC

HI SPEC

Figure 13. Temperature Error Measuring Intel Pentium 4 Processor

140

120

055

69-

TIME (Seconds)

I
NG

(

°
C)

120

100

INT
EXT1
EXT2
EXT3

Figure 14. DUT Response to Thermal Shock

ADT7462

Rev. 0 | Page 16 of 92

60

100

556

RESISTANCE (M)

URE

RRO

R (

°
C

)

20

40

D+ TO GND

D+ TO V

Figure 15. Temperature Error vs. Resistance (SRC)

20

556

POWER SUPPLY NOISE FREQUENCY (kHz)

URE

RRO

R (

°
C

)

100

10M

100M

10

15

50mV
125mV

Figure 16. Local Temperature Error vs. Power Supply Noise Frequency

12

556

POWER SUPPLY NOISE FREQUENCY (kHz)

URE

RRO

R (

°
C

)

100

10M

100M

50mV
125mV

10

Figure 17. Remote Temperature Error vs. Power Supply Noise Frequency

10

556

NOISE FREQUENCY (kHz)

URE

RRO

R (

°
C

)

100

10M

100M

100mV

60mV

40mV

Figure 18. Temperature Error vs. Common-Mode Noise Frequency

556

NOISE FREQUENCY (kHz)

URE

RRO

R (

°
C

)

100

10M

100M

10mV
20mV

Figure 19. Temperature Error vs. Differential-Mode Noise Frequency

50

556

CAPACITANCE (nF)

URE

RRO

R (

°
C

)

10

20

30

40

DEV1, EXT1
DEV1, EXT2
DEV1, EXT3
DEV2, EXT1
DEV2, EXT2
DEV2, EXT3
DEV3, EXT1
DEV3, EXT2
DEV3, EXT3

Figure 20. Temperature Error vs. Capacitance Between D+ and D-

ADT7462

Rev. 0 | Page 17 of 92

0.200

0.180

50

150

556

TIMEOUT (Seconds)

RAT

URE

(

°
C)

0.198

0.196

0.194

0.192

0.190

0.188

0.186

0.184

0.182

100

POWER UP

STANDBY

Figure 21. Temperature vs. Power-On Reset Timeout

3.0

556

VOLTAGE APPLIED (V)

BAT

ADI

(

)

2.5

2.0

1.5

1.0

0.5

1.0

1.5

2.0

2.5

DEV1
DEV2
DEV3

Figure 22. V

BATT

Measurement vs. Applied Voltage

5.0

2.9

3.4

3.9

4.4

4.9

5.4

556

SUPPLY (V)

H E

RRO

R (

)

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

DEV1
DEV2
DEV3

Figure 23. TACH Accuracy vs. Supply Voltage

1.5

2.0

50

150

556

TEMPERATURE (°C)

H E

RRO

R (

)

1.0

0.5

1.0

1.5

100

DEV1

DEV2

DEV3

Figure 24. TACH Accuracy vs. Temperature

ADT7462

Rev. 0 | Page 18 of 92

SERIAL BUS INTERFACE

The ADT7462 is controlled through use of the serial system
management bus (SMBus). The ADT7462 is connected to this
bus as a slave device, under the control of a master controller.
The SMBus interface in the ADT7462 is fully SMBus 1.1- and
SMBus 1.0-compliant. The SMBus address is determined by the
state of the ADD input on power-up.

ADD INPUT

The ADD pin is a three-state input to the ADT7462. It is used
to determine the SMBus address used. This pin is sampled on
power-up only. Any changes subsequent to power-up are not
reflected until the ADT7462 is powered down and back up
again. The corresponding 7-bit SMBus address for the state of
the ADD pin is shown in Table 11.

Table 11. Corresponding SMBus Addresses for ADD Input

ADD Pin

SMBus Version

SMBus Address

High N/A

N/A

Float SMBus

1.1

0x5C

Low SMBus

1.1

0x58

SMBUS FIXED ADDRESS

The ADT7462 supports SMBus fixed address mode and is fully
backwards-compatible with SMBus 1.1 and SMBus 1.0. The
ADT7462 powers up with a fixed SMBus address that cannot be
changed by the assign address call. The fixed address is set by the
state of the ADD input pin on power-up.

SMBUS OPERATION

The SMBus specification defines specific conditions for different
types of read and write operations. The general SMBus protocol
operates as follows:

The master initiates data transfer by establishing a start condi-
tion, defined as a high-to-low transition on the serial data
line, SDA, while the serial clock line, SCL, remains high. This
indicates that an address/data stream follows. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next eight bits, consisting of a
7-bit address (MSB first) plus an R/W bit, which determines
the direction of the data transfer, that is, whether data is
written to or read from the slave device.

The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the
low period before the 9th clock pulse, known as the
acknowledge bit. All other devices on the bus remain idle
while the selected device waits for data to be read from it or
written to it. If the R/W bit = 0, the master writes to the
slave device. If the R/W bit = 1, the master reads from the
slave device.

Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, because a low-to-high
transition when the clock is high can be interpreted as
a stop signal. The number of data bytes that can be
transmitted over the serial bus in a single read or write
operation is limited only by what the master and slave
devices can handle.

When all data bytes have been read or written, stop
conditions are established. In write mode, the master releases
the data line during the 10th clock pulse to assert a stop
condition. In read mode, the master device overrides the
acknowledge bit by pulling the data line high during the
low period before the 9th clock pulse. This is known as a
No Acknowledge. The master then takes the data line low
during the low period before the 10th clock pulse and then
takes it high during the 10th clock pulse to assert a stop
condition.

Any number of bytes of data can be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.

For the ADT7462, write operations contain either one or two
bytes, and read operations contain one byte. To write data to
one of the device data registers or read data from it, the address
pointer register must be set so that the correct data register is
addressed. Then data can be written into that register or read
from it. The first byte of a write operation always contains an
address that is stored in the address pointer register. If data is to
be written to the device, the write operation contains a second
data byte that is written to the register selected by the address
pointer register.

This write operation is shown in Figure 25. The device address
is sent over the bus, and then R/W is set to 0. This is followed
by two data bytes. The first data byte is the address of the
internal data register to be written to, which is stored in the
address pointer register. The second data byte is the data to be
written to the internal data register.

ADT7462

Rev. 0 | Page 19 of 92

When reading data from a register, there are two possibilities.

If the ADT7462's address pointer register value is
unknown or not the desired value, it must be set to the
correct value before data can be read from the desired data
register. This is done by performing a write to the ADT7462
as before, but only the data byte containing the register
address is sent because no data is written to the register
(see Figure 26).

A read operation is then performed, consisting of the serial
bus address and the R/W bit set to 1, followed by the data
byte read from the data register (see Figure 27).

If the address pointer register is known to be already at the
desired address, data can be read from the corresponding
data register without first writing to the address pointer
register (see Figure 27).

It is possible to read a data byte from a data register without
first writing to the address pointer register, if the address
pointer register is already at the correct value.

However, it is not possible to write data to a register without
writing to the address pointer register, because the first data
byte of a write is always written to the address pointer register.

In addition to supporting the send byte and receive byte
protocols, the ADT7462 also supports the read byte protocol
(see System Management Bus Specifications Rev. 2.0 for more
information).

If several read or write operations must be performed in
succession, then the master can send a repeat start condition,
instead of a stop condition, to begin a new operation.

SCL

SDA

START BY

MASTER

ACK. BY

ADT7462

ACK. BY

ADT7462

ACK. BY

ADT7462

STOP BY

MASTER

FRAME 2

ADDRESS POINTER REGISTER BYTE

FRAME 1

SERIAL BUS ADDRESS BYTE

R/W

SCL (CONTINUED)

SDA (CONTINUED)

FRAME 3 DATA BYTE

Figure 25. Writing a Register Address to the Address Pointer Register, Then Writing Data to the Selected Register

SCL

SDA

START BY

MASTER

ACK. BY

ADT7462

ACK. BY

ADT7462

STOP BY

MASTER

FRAME 2

ADDRESS POINTER REGISTER BYTE

FRAME 1

SERIAL BUS ADDRESS BYTE

R/W

0
55

-
01

Figure 26. Writing to the Address Pointer Register Only

SCL

SDA

START BY

MASTER

ACK. BY

ADT7462

NO ACK.

BY MASTER

STOP BY

MASTER

FRAME 2

DATA BYTE FROM ADT7462

FRAME 1

SERIAL BUS ADDRESS BYTE

R/W

0
55

-
01

Figure 27. Reading Data from a Previously Selected Register

ADT7462

Rev. 0 | Page 20 of 92

WRITE OPERATIONS

The SMBus specification defines several protocols for different
types of read and write operations. The ones used in the ADT7462
are discussed below. The following abbreviations are used in the
diagrams:

S Start
P Stop
R Read
W Write
A Acknowledge
A No Acknowledge

The ADT7462 uses the following SMBus write protocols.

Send Byte

In this operation, the master device sends a single command
byte to a slave device as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts an ACK on SDA.

4. The master sends a command code.

5. The slave asserts an ACK on SDA.

6. The master asserts a stop condition on SDA, and the

transaction ends.

For the ADT7462, the send byte protocol is used to write a
register address to RAM for a subsequent single byte read from
the same address. This operation is shown in Figure 28.

SLAVE

ADDRESS

REGISTER

ADDRESS

A P

055

-
0

Figure 28. Setting a Register Address for a Subsequent Read

If it is required to read data from the register immediately after
setting up the address, the master can assert a repeat start
condition immediately after the final ACK and carry out a
single byte read without asserting an intermediate stop
condition.

Write Byte

In this operation, the master device sends a command byte and
one data byte to the slave device as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts an ACK on SDA.

4. The master sends a command code.

The slave asserts an ACK on SDA.

6. The master sends a data byte.

7. The slave asserts an ACK on SDA.

8. The master asserts a stop condition on SDA to end the

transaction.

SLAVE

ADDRESS

SLAVE

ADDRESS

W A

DATA

556

Figure 29. Single Byte Write to a Register

Block Write

In this operation, the master device writes a block of data to a
slave device. The start address for a block write must have been
set previously. In the case of the ADT7462, this is done by a
send byte operation to set a RAM address. The user writes the
number of registers to be written to in the block read command
to the #Bytes bits of the Configuration 0 register.

1. The master device asserts a start condition on the SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts an ACK on the SDA.

4. The master sends a command code that tells the slave

device to expect a block write. The ADT7462 command
code for a block write is 0xA0 (1010 0000).

5. The slave asserts ACK on the SDA.

6. The master sends the data bytes (the number of data bytes

sent is written to the #Bytes bits of the Configuration 0
register).

7. The slave asserts an ACK on the SDA after each data byte.

8. The master sends a packet error checking (PEC) byte.

9. The ADT7462 checks the PEC byte and issues an ACK,

if correct. If incorrect (NO ACK), the master resends the
data bytes.

10. The master asserts a stop condition on the SDA to end the

transaction.

W A

A DATA 1 A

A P

DATA 2 A DATA

PEC

SLAVE

ADDRESS

COMMAND

A0h BLOCK

WRITE

BYTE

COUNT

10 11 12

05569-

020

Figure 30. Block Write to ADT7462

ADT7462

Rev. 0 | Page 21 of 92

READ OPERATIONS

The ADT7462 uses the following SMBus read protocols.

Receive Byte

The receive byte is useful when repeatedly reading a single
register. The register address needs to have been set up
previously. In this operation, the master device receives a single
byte from a slave device as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

read bit (high).

3. The addressed slave device asserts an ACK on SDA.

4. The master receives a data byte.

5. The master asserts a NO ACK on SDA.

6. The master asserts a stop condition on SDA and the

transaction ends.

In the ADT7462, the receive byte protocol is used to read a
single byte of data from a register whose address has previously
been set by a send byte or write byte operation.

SLAVE

ADDRESS

DATA

9
-
02

Figure 31. Single Byte Read from a Register

Block Read

In this operation, the master device reads a block of data from
a slave device. The start address for a block read must have been
set previously, as well as the number of bytes to be read
(maximum = 32). In the case of the ADT7462, the start address
is activated by a send byte operation to set a RAM address. The
number of bytes to be read should be written to the #Bytes bits
in the Configuration 0 register. The block read operation
consists of a send byte operation that sends a block read
command to the slave, immediately followed by a repeated start
and a read operation that reads out multiple data bytes, as
follows:

1. The master device asserts a start condition on the SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts an ACK on the SDA.

4. The master sends a command code that tells the slave

device to expect a block read. The ADT7462 command
code for a block read is 0xA1 (1010 0001).

5. The slave asserts an ACK on SDA.

6. The master asserts a repeat start condition on the SDA.

7. The master sends the 7-bit slave address followed by the

read bit (high).

8. The slave asserts an ACK on the SDA.

9. The ADT7462 sends a byte count telling the master how

many data bytes to expect. The maximum number of bytes
is 32.

10. The master asserts an ACK on SDA.

11. The master receives the expected number of data bytes.

12. The master asserts an ACK on SDA after each data byte.

13. The ADT7462 issues a PEC byte to the master. The master

should check the PEC byte and issue another block read if
the PEC byte is incorrect.

14. A NO ACK is generated after the PEC byte to signal the

end of the read.

15. The master asserts a stop condition on the SDA to end the

transaction.

SLAVE

ADDRESS W A

COMMAND

A1h BLOCK

READ

DATA

PEC

BYTE

COUNT A DATA 1 A

SLAVE

ADDRESS

14 15

0
55

-
02

Figure 32. Block Read from RAM

Note that although the ADT7462 supports packet error
checking (PEC), its use is optional. The PEC byte is calculated
using CRC-8. The frame check sequence (FCS) conforms to
CRC-8 by the polynomial

( )

Consult the SMBus 1.1 specifications for more information.

ADT7462

Rev. 0 | Page 22 of 92

ALERT RESPONSE ADDRESS

Alert response address (ARA) is a feature of SMBus devices that
allows an interrupting device to identify itself to the host when
multiple devices exist on the same bus.

The SMBALERT output can be used as either an interrupt
output or an SMBALERT. One or more outputs can be
connected to a common SMBALERT line connected to the
master. If a device's SMBALERT line goes low, the following
procedure occurs:

SMBALERT is pulled low.

Master initiates a read operation and sends the alert
response address (ARA = 0001 100). This is a general call
address that must not be used as a specific device address.

The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known and can
be interrogated in the usual way.

If more than one device's SMBALERT output is low, the
one with the lowest device address has priority in
accordance with normal SMBus arbitration.

Once the ADT7462 has responded to the alert response
address, the master must read the status registers, and
the SMBALERT is cleared only if the error condition has
gone away.

SMBUS TIMEOUT

The ADT7462 includes an SMBus timeout feature. If there is no
SMBus activity for 25 ms, the ADT7462 assumes that the bus is
locked and releases the bus. This prevents the device from
locking or holding the SMBus expecting data. Some SMBus
controllers cannot handle the SMBus timeout feature, so it can
be disabled.

Configuration Register 3 (0x03)

Bit 1 SCL_Timeout = 1; SCL timeout enabled.

Bit 1 SCL_Timeout = 0; SCL timeout disabled (default).

Bit 2 SDA_Timeout = 1; SDA timeout enabled.

Bit 2 SDA_Timeout = 0; SDA timeout disabled (default).

ADT7462

Rev. 0 | Page 23 of 92

TEMPERATURE AND VOLTAGE MEASUREMENT

TEMPERATURE MEASUREMENT

The ADT7462 can measure its own ambient temperature and
the temperature of up to three remote thermal diodes. These
diodes can be discrete diode-connected 2N3904/6s or can be
located on a processor die. Figure 33 shows how to connect a
remote NPN or PNP transistor.

D+

ADT7462

2N3904

D+

ADT7462

2N3906

05569-

0
23

Figure 33. How to Measure Temperature Using Discrete Transistors

Remote Thermal Diode 1 connects to Pin 15 and Pin 16.

Remote Thermal Diode 2 connects to Pin 17 and Pin 18.

Remote Thermal Diode 3 connects to Pin 19 and Pin 20.

A simple method of measuring temperature is to exploit the
negative temperature coefficient of a diode, measuring the base-
emitter voltage (V

) of a transistor, operated at constant

current. Unfortunately, this technique requires calibration to
null out the effect of the absolute value of V

, which varies

from device to device.

The technique used in the ADT7462 is to measure the change
in V

when the device is operated at three different currents.

Previous devices have used only two operating currents;
use of a third current allows automatic cancellation of any
resistances in series with the external temperature sensor.

Figure 34 shows the input signal conditioning used to measure
the output of an external temperature sensor. This figure shows
the external sensor as a substrate transistor, but it could equally
be a discrete transistor. If a discrete transistor is used, the
collector is not grounded and should be linked to the base. To
prevent ground noise from interfering with the measurement, the
more negative terminal of the sensor is not referenced to
ground but is biased above ground by an internal diode at the
D- input. C1 can optionally be added as a noise filter
(recommended maximum value 1000 pF). However, a better
option in noisy environments is to add a filter, as described in
the Noise Filtering section.

To measure V

, the operating current through the sensor is

switched among three related currents. As shown in Figure 34,
N1 × I and N2 × I are different multiples of the Current I. The
currents through the temperature diode are switched between I
and N1 × I, giving V

BE1

, and then between I and N2 × I, giving

BE2

. The temperature can then be calculated using the two

measurements. This method can also be shown to cancel

the effect of any series resistance on the temperature
measurement.

The resulting V

waveforms are passed through a 65 kHz

low-pass filter to remove noise and then to a chopper-stabilized
amplifier. This amplifies and rectifies the waveform to produce
a dc voltage proportional to V

. The ADC digitizes this

voltage, and a temperature measurement is produced. To reduce
the effects of noise, digital filtering is performed by averaging
the results of 16 measurement cycles for low conversion rates.

Signal conditioning and measurement of the internal
temperature sensor are performed in the same manner.

C1*

D+

BIAS

DIODE

*CAPACITOR C1 IS OPTIONAL. IT SHOULD ONLY BE USED IN NOISY ENVIRONMENTS.

TO ADC

OUT+

OUT

REMOTE

SENSING

TRANSISTOR

BIAS

LOW-PASS FILTER

= 65kHz

055

69-

0
24

Figure 34. Input Signal Conditioning

Temperature Measurement Results

The results of the local and remote temperature measurements
are stored in the local and remote temperature value registers
and are compared with limits programmed into the local and
remote high and low limit registers.

Table 12. Temperature Measurement Registers

Temperature Value

Register Address

Local Temperature, LSB

Local Temperature, MSB

Remote 1 Temperature, LSB

Remote 1 Temperature, MSB

Remote 2 Temperature, LSB

Remote 2 Temperature, MSB

Remote 3 Temperature, LSB

Remote 3 Temperature, MSB

The temperature value is stored in two registers. The MSB has a
resolution of 1°C. Only two bits in the temperature LSB register
are used, Bit 7 and Bit 6, giving a temperature measurement a
resolution of 0.25°C. The temperature measurement range for
both local and remote measurements is from -64°C to +191°C.
However, the ADT7462 itself should never be operated outside
its operating temperature range, which is from -40°C to +125°C.
For the remote diode, the user should refer to the data sheet of
the diode.

Table 13. Temperature Data Format

Temperature Value

MSB

LSB

-64°C

0000 0000

-50.25°C

0000 1110

0100 0000

-25°C

0010 0111

0000 0000

0°C

0100 0000

0000 0000

+25°C

0101 1001

0000 0000

+50.25°C

0111 0010

0100 0000

+100°C

1010 0100

0000 0000

ADT7462

Rev. 0 | Page 24 of 92

When reading the full temperature value, the LSB should be
read first and then the MSB. Reading the LSBs causes the
current MSBs to be frozen until they are read. Reading the
MSBs only does not cause any register to be locked. This is
useful when a temperature reading with 1°C resolution is
required.

SERIES RESISTANCE CANCELLATION

Parasitic resistance in series with the remote diode D+ and D-
inputs can be caused by a variety of factors, including PCB track
resistance and track length. This series resistance appears as a
temperature offset in the remote sensor's temperature measure-
ment. This error typically causes a 0.8°C offset per ohm of
parasitic resistance in series with the remote diode.

The ADT7462 automatically cancels out the effect of this series
resistance on the temperature reading, giving a more accurate
result, without the need for user characterization of this
resistance. The ADT7462 is designed to automatically cancel
typically up to 2 k of resistance. By using an advanced
temperature measurement method, the process is transparent to
the user. This feature also allows an RCR filter to be added to
the sensor path, allowing the part to be used accurately in noisy
environments.

Temperature Limits

Each temperature measurement channel has a high and low
temperature limit associated with it. The temperature measure-
ments are compared with these limits, and the results of these
comparisons are stored in status registers. A Logic 0 indicates
an in-limit comparison, and a Logic 1 indicates an out-of-limit
comparison. The ADT7462 can generate an ALERT, if configured
to do so, once a status bit is set. For more information on the
status registers and ALERT, see the Status and Mask Registers
and ALERT section of this datasheet.

Each temperature channel also has a THERM1 and a THERM2
temperature limit associated with it. Once these temperature
limits are exceeded, the corresponding THERM pin is asserted
low (if THERM is configured as an output), and the fans are
boosted to full speed (if the boost bit is set). Table 14 shows
a complete list of all the temperature limits and their default
values.

Table 14. Temperature Limit Registers

Temperature Value

Local Low Temperature Limit

0x44

0x40

Remote 1 Low Temperature Limit

0x45

0x40

Remote 2 Low Temperature Limit

0x46

0x40

Remote 3 Low Temperature Limit

0x47

0x40

Local High Temperature Limit

0x48

0x95

Remote 1 High Temperature Limit

0x49

0x95

Remote 2 High Temperature Limit

0x4A

0x95

Remote 3 High Temperature Limit

0x4B

0x95

Local THERM1 Temperature Limit

0x4C 0xA4

Remote 1 THERM1 Temperature Limit

0x4D 0xA4

Remote 2 THERM1Temperature Limit

0x4E 0xA4

Remote 3 THERM1 Temperature Limit

0x4F 0xA4

Local THERM2 Temperature Limit

0x50 0xA4

Remote 1 THERM2 Temperature Limit

0x51 0xA4

Remote 2 THERM2 Temperature Limit

0x52 0xA4

Remote 3 THERM2 Temperature Limit

0x53 0xA4

Offset Registers

The ADT7462 has temperature offset registers at Register 0x56
to Register 0x59 for the local, Remote 1, Remote 2, and Remote 3
temperature channels. By doing a one-time calibration of the
system, the user can determine the offset caused by system
board noise and null it out using the offset registers. The offset
registers automatically add a twos complement, 8-bit reading to
every temperature measurement. The LSBs add 0.5°C offset to
the temperature reading so the 8-bit register effectively allows
temperature offsets of up to ±64°C with a resolution of 0.5°C.
This ensures that the readings in the temperature measurement
registers are as accurate as possible.

Temperature Offset Registers

Register 0x56 Local Temperature Offset = 0x00 (0°C default)
Register 0x57 Remote 1 Temperature Offset = 0x00 (0°C default)
Register 0x58 Remote 2 Temperature Offset = 0x00 (0°C default)
Register 0x59 Remote 3 Temperature Offset = 0x00 (0°C default)

ADT7462

Rev. 0 | Page 25 of 92

Layout Considerations

Digital boards can be electrically noisy environments. The
ADT7462 measures very small voltages from the remote sensor,
so care must be taken to minimize noise induced at the sensor
inputs. The following precautions should be taken:

Place the ADT7462 as close as possible to the remote sensing

diode. Provided that the worst noise sources, such as clock
generators, data/address buses, and CRTs, are avoided, this
distance can be 4 inches to 8 inches.

Route the D+ and D- tracks close together, in parallel, with

grounded guard tracks on each side. To minimize inductance
and reduce noise pick-up, a 5 mil track width and spacing is
recommended. If possible, provide a ground plane under the
tracks.

5MIL

GND

D+

GND

0
55

-
02

Figure 35. Typical Arrangement of Signal Tracks

Minimize the number of copper/solder joints that can cause

thermocouple effects. Where copper/solder joints are used,
make sure that they are in both the D+ and D- path and at
the same temperature.

· Thermocouple effects should not be a major problem because

1°C corresponds to about 200 mV, and thermocouple voltages
are about 3 mV/°C of temperature difference. Unless there
are two thermocouples with a big temperature differential
between them, thermocouple voltages should be much less
than 200 mV.

Place a 0.1 F bypass capacitor close to the V

pin. In

extremely noisy environments, an input filter capacitor can
be placed across D+ and D- close to the ADT7462. This
capacitance can affect the temperature measurement, so care
must be taken to ensure that any capacitance seen at D+ and
D- is a maximum of 1000 pF.

This maximum value includes the filter capacitance, plus any

cable or stray capacitance between the pins and the sensor diode.

If the distance to the remote sensor is more than 8 inches, the

use of twisted pair cable is recommended. This works up to
about 6 feet to 12 feet.

For really long distances (up to 100 feet), use shielded twisted

pair, such as Belden No. 8451 microphone cable. Connect the
twisted pair to D+ and D- and the shield to GND close to the
ADT7462. Leave the remote end of the shield unconnected to
avoid ground loops.

· Because the measurement technique uses switched current

sources, excessive cable or filter capacitance can affect the
measurement. When using long cables, the filter capacitance
can be reduced or removed.

Noise Filtering

For temperature sensors operating in noisy environments, the
industry-standard practice is to place a capacitor across the D+
and D- pins to help combat the effects of noise. However, large
capacitances affect the accuracy of the temperature
measurement, leading to a recommended maximum capacitor
value of 1000 pF. While this capacitor does reduce the noise,
it does not eliminate it, making it difficult to use the sensor in
a very noisy environment.

The ADT7462 has a major advantage over other devices when it
comes to eliminating the effects of noise on the external sensor.
The series resistance cancellation feature allows a filter to be
constructed between the external temperature sensor and the
device. The effect of any filter resistance seen in series with the
remote sensor is automatically cancelled from the temperature
result.

The construction of a filter allows the ADT7462 and the remote
temperature sensor to operate in noisy environments. Figure 36
shows a low-pass RCR filter, with the following values:

R = 100

C = 1 nF

This filtering reduces both common-mode noise and
differential noise.

100

1nF

REMOTE

SENSOR

9
-
02

D+

Figure 36. Filter Between Remote Sensor and the ADT7462

ADT7462

Rev. 0 | Page 26 of 92

VOLTAGE MEASUREMENT

The ADT7462 is capable of measuring up to 13 different voltage
inputs at one time. Table 15 is a list of the voltage measurement
inputs and the corresponding input pins. Each pin can be
configured to measure the desired voltage option using Pin
Configuration 1 (0x10) to Pin Configuration 4 (0x13) or the
easy configuration options.

Table 15. Voltage Inputs

Pin Voltage

Measured

7 +12V1
8 +12V2
13 +3.3V
15 +2.5V/+1.8V
19 +1.25V/+0.9V
21 +5V
22 +12V3
23 V

CCP1

/+1.5V/+1.8V/+2.5V

24 V

CCP2

/+1.5V/+1.8V/+2.5V

25 +1.2V1

BIT

)/+3.3V

26 +1.2V2

(FSB_V

)/V

BATT

28 +1.5V1

(ICH)

29 +1.5V2

(3GIO)

Input Circuit

The internal structure for the voltage inputs is shown in Figure 37.
Each input circuit consists of an input protection diode; an
attenuator; plus a capacitor to form a first-order, low-pass filter
that gives the input immunity to high frequency noise.

Voltages with full-scale values greater than the reference are
divided down so that the full-scale value equals the reference
(2.25 V). All analog inputs are multiplexed into the on-chip,
successive approximation ADC. This ADC has a resolution of
ten bits. The basic input range is from 0 V to 2.25 V, but the
inputs have built-in attenuators to allow measurement of larger
and smaller voltages. To allow a tolerance for these voltages, the
ADC produces an output of 3/4 full scale (decimal 768 or
0x300) for the nominal input voltage and so has enough
headroom to cope with overvoltages.

0.9V

92k

35pF

1.25V

30k

72k

10pF

32k

77k

10pF

51k

66k

8pF

1.8V

91k

35pF

2.5V

30k

72k

10pF

3.3V

57k

17k

5pF

76k

39k

5pF

12V

100k

16k

5pF

MUX

BIT

FSB_V

CCP1

CCP2

ICH,

3GIO,

1.5V

0
27

Figure 37. Voltage Input Structures

ADT7462

Rev. 0 | Page 27 of 92

A list of corresponding LSB and full-scale values for each input
voltage is shown in Table 16.

Table 16. Input Range Code Conversion

Nominal Input
Voltage (3/4 Scale)

Pin

1 LSB
Value

Full
Scale

+12V

7, 8, 22

0.0625

16 V

+5V 21

0.026

6.67

CCP1

, V

CCP2

23, 24

0.00625

1.6 V

CCP1

, when VIDs

are enabled

23 0.0125

3.2

+3.3V 13,

0.0172

4.4

BATT

26 0.0156

+2.5V

15, 23, 24

0.013

3.33 V

+1.8V

15, 23, 24

0.0094

2.4 V

+1.5V

23, 24, 28, 29

0.0078

2 V

+1.25V 19

0.0065

1.667

+1.2V 25,

0.00625

1.6

+0.9V 19

0.00469

1.2

Example Calculations

Given the LSB value for each channel, the corresponding code
for each voltage (or vice versa) can be calculated.

LSB

Voltage

Code

Example:

The code for 1.8 V in a 1.8 V channel is

(

)

scale

that

Code

192

0094

Similarly, the voltage, given the code in a particular channel, is
calculated as follows:

Voltage = Code × 1 LSB

where:

10 V is connected to the 12 V channel.
1 LSB = 0.0625.
Code = 160 decimal.

Voltage Measurement and Limit Registers

The corresponding register locations for voltage measurements
are listed in Table 17. Each voltage measurement channel has a
high and low voltage limit associated with it. The voltage
measurements are compared with these limits. The results of
these comparisons are stored in status registers. A Logic 0
indicates an in-limit condition, and a Logic 1 indicates an out-
of-limit condition. The ADT7462 can generate an ALERT, if
configured to do so, once a status bit is set. For more
information on the status registers and ALERT, see the Status
and Mask Registers and ALERT section of this datasheet. A
complete list of all the high and low voltage limits in the
ADT7462 and their default values is contained in Table 17.

Table 17. Voltage Value and Limit Registers

Low Limit

High Limit

Voltage Value

Pin

Value Register Address

Register Default Register Default

+12V1 Pin

0xA3 0x6D

0x00

0x7C

0xFF

+12V2 Pin

0xA5 0x6E

0x00

0x7D

0xFF

+3.3V Pin

0x96 0x70

0x00

0x68

0xFF

+1.8V or +2.5V

Pin 15

0x8B

0x45

0x40

0x49

0x95

+1.25V or +0.9V

Pin 19

0x8F

0x47

0x40

0x4B

0x95

+5V Pin

0xA7 0x71

0x00

0x7E

0xFF

+12V3 Pin

0xA9 0x6F

0x00

0x7F

0xFF

CCP1

, +1.5V, +1.8V, +2.5V

Pin 23

0x90

0x72

0x20

0x69

0xFF

CCP2

, +1.5V, +1.8V, +2.5V

Pin 24

0x91

0x73

0x00

0x6A

0xFF

+1.2V1 (G

BIT

) or +3.3V

Pin 25

0x92

0x74

0x00

0x6B

0xFF

+1.2V2 (FSB_V

) or V

BATT

0x93

0x75

0x80

0x6C

0xFF

+1.5V1 (ICH)

Pin 28

0x94

0x76

0x00

0x50

0xA4

+1.5V2 (3GIO)

Pin 29

0x95

0x77

0x00

0x4C

0xA4

ADT7462

Rev. 0 | Page 28 of 92

BATTERY MEASUREMENT INPUT (V

BATT

)

The V

BATT

input allows the condition of a CMOS backup battery

to be monitored. This is typically a lithium coin cell, such as a
CR2032. The V

BATT

input is accurate only for voltages greater

than 1.2 V. Note that when Pin 26 is configured as a +1.2V
input, voltages lower than 1.2 V are not accurately measured.
Input voltage and corresponding voltage measured are shown in
Figure 22. Typically, the battery in a system is required to keep
some devices powered on when the system is in a powered-off
state. The V

BATT

measurement input is designed to minimize

battery drain. To reduce current drain from the battery, the
lower resistor of the V

BATT

attenuator is not connected, except

when a V

BATT

measurement is being made. The total current

drain on the V

BATT

pin is 80 nA typical (for a maximum V

BATT

voltage = 4 V), so a CR2032 CMOS battery functions in a
system in excess of the expected 10 years. Note that when a
V

BATT

measurement is not being made, the current drain is

reduced to 6 nA typical. Under normal voltage measurement
operating conditions, all measurements are made in a round-
robin format, and each reading is actually the result of 16
digitally averaged measurements. However, averaging is not
carried out on the V

BATT

measurement to reduce measurement

time and, therefore, reduce the current drain from the battery.

The V

BATT

current drain when a measurement is being made is

calculated by

PERIOD

PULSE

BATT

100

where:

PULSE

is V

BATT

measurement time (~711 s typical).

PERIOD

is the time required to measure all analog inputs.

Monitoring cycle time depends on the ADT7462 configuration.
Calculating the monitoring cycle time is described in more
detail in the ADC Information section.

BATT

Input Battery Protection

In addition to minimizing battery current drain, the V

BATT

measurement circuitry is specifically designed with battery
protection in mind. Internal circuitry prevents the battery from
being back-biased by the ADT7462 supply or through any other
path under normal operating conditions. In the unlikely event
of a catastrophic ADT7462 failure, the ADT7462 includes a
second level of battery protection, including a series 3 k
resistor to limit current to the battery, as recommended by UL.
Thus, it is not necessary to add a series resistor between the
battery and the V

BATT

input; the battery can be connected

directly to the V

BATT

input to improve voltage measurement

accuracy.

055

-
02

ADC

BATT

DIGITAL

CONTROL

49.5k

82.7k

4.5pF

Figure 38. Equivalent V

BATT

Input Protection Circuit

ADT7462

Rev. 0 | Page 29 of 92

ADC INFORMATION

Round Robin

Both temperature and voltage measurements are analog inputs
that are digitized using the on-board ADC. An internal
multiplexer switches between the different analog inputs and
digitizes them, in turn, in a round-robin manner. The total
conversion time depends upon how the ADT7462 is configured.
The conversion times for each measurement channel are shown
in Table 18. The complete conversion time is the sum of the time
for the voltage and temperature measurements.

For example, if the ADT7462 is configured as Easy Configuration
Option 1, the round-robin conversion time is calculated as follows:

Total Conversion Time = 1 × (Local Conversion Time) + 3 ×
(Remote Conversion Time) + 4 × (Voltage Measurement Time).

The TACH is not measured using the ADC and so is not part of
the round-robin monitoring cycle.

Table 18. Measurement Channel Conversion Times

Channel Conversion

Time

Local Temperature

9.01 ms

Remote Temperature

38.36 ms

Voltage 8.53

For each ADC temperature and voltage measurement read from
their value registers, 16 readings have actually been made
internally and the results averaged before being placed in the
value register.

Bypass Voltage Attenuators

There are up to 13 voltage measurement channels on the
ADT7462. Each of these voltage measurement channels has an
input structure (see Figure 37 for input structures for each of
the voltage channels). Because the ADC has a voltage input
range from 0 V to 2.25 V, these input circuits attenuate the
voltage input using a resistor divider network to match the
input range of the ADC. However, the user may occasionally
want to remove the attenuators and directly apply a voltage of
between 0 V and 2.25 V to the ADC. These attenuators can be
disabled by setting relevant bits in the voltage attenuator
configuration registers. This feature also allows the user to
rescale the voltage inputs using an external attenuator circuit.
However, when the attenuators are disabled, the user should
ensure that the voltage on the pin never exceeds 2.25 V.

Table 19. Voltage Attenuator Configuration Registers

Register Name

Voltage Attenuator Configuration Register 1

0x18

Voltage Attenuator Configuration Register 2

0x19

Single-Channel ADC Conversions

Setting Bit 2 of the EDO/single-channel enable register (0x16)
places the ADT7462 into single-channel mode. In this mode the
ADT7462 can be made to convert on a single voltage or
temperature channel only. The channel to be converted on is
selected by writing to Bits [7:3] of the EDO/single-channel
enable register (0x16). When the device is in single-channel
mode, the pin configuration option should not be changed.

Note that when the Pin 26 voltage, which includes the V

BATT

option, is selected in single-channel mode, this means that
voltage measurements are continuously made in the mode.
If a battery is connected to this input, then this results in an
excessive current drain on the battery. The specification of >10
years of battery life is valid only when the battery voltage is meas-
ured as part of the round robin and not in single-channel mode.

Table 20. Single-Channel Mode Options

Bits [7:3]

ADC Channel Selected

00 000

Pin 26

00 001

Remote 1 temperature

00 010

Remote 2 temperature

00 011

Remote 3 temperature

00100 Local

temperature

00 101

+12V1 voltage, Pin 7

00 110

+12V2 voltage, Pin 8

00 111

+12V3 voltage, Pin 22

01 000

+3.3V voltage, Pin 13

01 001

+2.5V/+1.8V voltage, Pin 15

01 010

+1.25V/0.9V voltage, Pin 19

01 011

+5V voltage, Pin 21

01 100

Pin 23 voltage

01 101

Pin 24 voltage

01 110

Pin 25 voltage

10 000

+1.5V1 voltage, Pin 28

10 001

+1.5V2 voltage, Pin 29

ADT7462

Rev. 0 | Page 30 of 92

DYNAMIC VID MONITORING

VID CODE

The ADT7462 can be configured to monitor up to seven VID
inputs. The VID code is output on seven lines from the CPU
to tell the power controller what input voltage it requires. The
ADT7462 can monitor the VID code and the voltage applied to
the CPU to ensure that they match within an acceptable range.
This acceptable range is programmable in the ADT7462.

The VID lines are monitored by the ADT7462, and the VID
code is stored in the VID value register (0x97), which can be
read back over the SMBus.

VID monitoring is enabled by setting Bit 7 (VIDs) of Pin
Configuration Register 1 (0x10) to 1. See Table 21 and Table 22
for information on which pin should be connected to each VID
line. When VID monitoring is enabled, all seven pins are
automatically configured as VID inputs. It is not possible to select
six pins as VID inputs and use the remaining pin as their
alternate functions.

VID Value Register (0x97)

Bit 0 = VID0 (reflects the logic state of Pin 1)

Bit 1 = VID1 (reflects the logic state of Pin 2)

Bit 2 = VID2 (reflects the logic state of Pin 3)

Bit 3 = VID3 (reflects the logic state of Pin 4)

Bit 4 = VID4 (reflects the logic state of Pin 31)

Bit 5 = VID5 (reflects the logic state of Pin 32)

Bit 6 = VID6 (reflects the logic state of Pin 28)

The ADT7462 supports both the VR10 and the VR11 specifica-
tions. The default option supports the VR10 specification.
To switch to the VR11 specification, set Bit 6 of Configuration
Register 0 (0x00) to 1. VR11 is defined as eight bits; the ADT7462
monitors only seven VID lines (see Table 21).

Table 21. VR11 VID Codes

VID Number

Pin

Voltage

VID6 28

400

VID5 32

200

VID4 31

100

VID3 4

VID2 3

VID1 2

12.5

VID0 1

6.25

VR10 requires only six VID lines (see Table 22). Pin 28 should
be connected to ground when monitoring VR10 VID codes.
VID6 reports a 0.

Table 22. VR10 VID Codes

VID Number

Pin

Voltage

VID6

Unused, connect to GND

VID5 32

12.5

VID4 31

400

VID3 4

200

VID2 3

100

VID1 2

VID0 1

DYNAMIC VID MONITORING

The ADT7462 supports dynamic VID monitoring. The purpose
of the VID code is to tell the voltage controller what voltage,
V

CCP

, should be applied to the CPU. The V

CCP

voltage applied to

the processor changes as the power requirements of the
processor change. The VID is compared with V

CCP1

only. Note

that when the VIDs are enabled, the LSB value for V

CCP1

becomes 0.0125 V (see Table 16).

The VID values can represent voltages from 0.8375 V to 1.6 V.
The VID code is sampled by the ADT7462 every 11 s and is
stored in Register 0x97. Once the VID code has been stable
(that is, does not change) for 55 s, the measured V

CCP

is then

compared with the VID code. The comparison table used is
for either the VR10 or the VR11 specification (set by Bit 6 of
Register 0x00). If the VID code and the measured V

CCP

do not

match within a certain limit, then an ALERT is generated.

The VID value decoded and the V

CCP

measurement must be

within a window controlled by the VID high and low limits.
The VID is compared with V

CCP1

only. Register 0x78 holds

the 4-bit VID high and low limits. The high limit has a range
of 0 mV to +375 mV with a resolution of 25 mV (four bits). The
low limit has a range of 0 mV to -187.5 mV with resolution of
12.5 mV (four bits). The high limit is used in a greater-than
comparison, and the low limit is used in a less-than or equal-to
comparison. Note that if both limits are set to 0x00, then
because low limit is less than or equal to comparison, an
ALERT always results. Therefore, the minimum value for low
limit is 0x01.

If the V

CCP

voltage measured and the VID code do not match to

within the programmed limit, then Status Bit 6 of the digital
status register gets set (Register 0xBE). This, in turn, can
generate an ALERT if it is not masked.

ADT7462

Rev. 0 | Page 32 of 92

STATUS AND MASK REGISTERS AND ALERT

Status Registers

Each measured temperature and voltage has an associated high
and low limit. The measured values are compared with these
programmable limits. The results of these comparisons are
stored in the status registers. A Logic 0 in the status register
represents an in-limit comparison, while a Logic 1 represents an
out-of-limit comparison.

Once a status bit is set, it remains set until the status register is
read by the SMBus master. Once read, the status bit clears if the
error condition has gone away. The status registers are duplicated
to accommodate situations where there are two SMBus masters.
If one master reads the host status registers and consequently
clears them, the second master has no way of knowing what bits
were set and what bits were cleared. The second SMBus master
can read from the duplicate BMC status registers for what status
bits were set.

Table 23 is a list of the status registers and corresponding
addresses.

Table 23. Status Registers

Register Name

Host Address

BMC Address

Thermal Status Register 1

0xB8

0xC0

Thermal Status Register 2

0xB9

0xC1

Thermal Status Register 3

0xBA

Voltage Status Register 1

0xBB

0xC3

Voltage Status register 2

0xBC

0xC4

Fan Status Register 1

0xBD

0xC5

Digital Status Register 1

0xBE

0xC6

GPIO Status Register

0xBF

ALERT Output

The ADT7462 has an SMBus ALERT output that is asserted
when one of the status bits gets set. This is to alert the master
that an out-of-limit measurement has taken place or that there
is a fault on one of the fan channels.

An ALERT is generated as a result of a status bit being set in any
of the registers.

HIGH LIMIT

TEMPERATURE

STICKY

STATUS

BIT

TEMP BACK IN LIMIT

(STATUS BIT STAYS SET)

CLEARED ON READ

(TEMP BELOW LIMIT)

SMBALERT

05569-

029

Figure 39. ALERT and Status Bit Behavior

Figure 39 shows how the ALERT output and ``sticky'' status bits
behave. Once a limit is exceeded, the corresponding status bit is
set to 1. The status bit remains set until the error condition goes
away and the status register is read. The status bits are referred
to as sticky because they remain set until read by software. This
ensures that an out-of-limit event cannot be missed, if software
is polling the device periodically. Note that the ALERT output
remains low for the entire duration that a reading is out-of-limit
and until the status register has been read.

Mask Registers

The user has the option to mask out any of the individual status
bits that generate an ALERT. This is achieved by setting the
appropriate bit in the mask registers. The ALERT output is not
asserted on the setting of a status bit if it has been masked. The
status bit itself is not affected and continues to be set when an
out-of-limit condition exists.

Table 24 is a list of the mask registers and corresponding
addresses.

Table 24. Mask Registers

Register Name

Register Address

Thermal Mask Register 1

0x30

Thermal Mask Register 2

0x31

Voltage Mask Register 1

0x32

Voltage Mask Register 2

0x33

Fan Mask Register 1

0x34

Digital Mask Register 1

0x35

GPIO Mask Register

0x36

ADT7462

Rev. 0 | Page 33 of 92

FAN CONTROL

FAN DRIVE USING PWM CONTROL

The ADT7462 uses pulse width modulation (PWM) to control
fan speed. Control relies on varying the duty cycle (or on/off
ratio) of a square wave applied to the fan to vary the fan speed.
The advantage of using PWM control is that it uses a very
simple external circuit. The specific circuit used depends upon
the type of fan.

There are three main fan types in use: 2-wire fans, 3-wire fans,
and 4-wire fans. The 2-wire fan has only power and ground
connections. The 3-wire fan has power and ground connections
and a TACH output to indicate the speed of the fan. The 4-wire
fan has power and ground connections, a TACH output, and a
PWM input. The PWM input is connected directly to the PWM
drive of the ADT7462 and is used to control the speed of the
fans.

For 2-wire and 3-wire fans, the low frequency PWM drive
signal should be selected. For 4-wire fans, the high frequency
PWM drive signal should be selected.

Using the ADT7462 with 2-Wire Fans

Figure 40 shows the most typical circuit used with a 2-wire
fan and illustrates how a 2-wire fan can be connected to the
ADT7462. The low frequency PWM mode must be selected
when using a 2-wire fan.

ADT7462

PWM

TACH

5V OR

12V FAN

Q1
NDT3055L

3.3V

10k
TYPICAL

1N4148

0.01µF

SENSE

2
TYPICAL

0
55

-
03

Figure 40. Driving a 2-Wire Fan

Using the ADT7462 with 3-Wire Fans

Figure 41 shows the most typical circuit used with a 3-wire fan.

ADT7462

TACH/AIN

PWM

12V
FAN

Q1
NDT3055L

3.3V

12V

10k

4.7k

10k

1N4148

0
31

Figure 41. Driving a 3-Wire Fan

The external circuitry required is very simple. A MOSFET, such
as the NDT3055L, is used as the pass device. The specifications
of the MOSFET depend on the maximum current required by
the fan being driven. A typical PC fan can draw a nominal
current ranging from a few hundred milliamps to over an amp
of current. Depending on the current rating of the fan, a SOT
device can be used where board space is a concern. If you drive
several fans in parallel from a single PWM output or drive
larger server fans, the MOSFET must handle the higher current
requirements. The only other stipulation is that the MOSFET
should have a gate voltage drive, V

< 3.3 V, for direct interfac-

ing to the PWM pins. V

can be greater than 3.3 V as long as

the pull-up on the gate is tied to 5 V. The MOSFET should also
have a low on resistance to ensure that there is not significant
voltage drop across the FET, which would reduce the voltage
applied across the fan and reduce the full speed of the fan.

Figure 41 uses a 10 k pull-up resistor for the TACH signal.
This assumes that the TACH signal is an open collector from
the fan. In all cases, the TACH signal from the fan must be kept
below 5 V maximum to prevent damaging the ADT7462. If in
doubt as to whether the fan used has an open-collector or
totem-pole TACH output, use one of the input signal
conditioning circuits shown in the Fan Speed Measurement
section of the data sheet.

Driving a 3-wire fan with a PWM signal makes the fan speed
measurement more difficult because the TACH signal is
chopped by the PWM drive signal. Pulse stretching is required
in this case to make accurate fan speed measurements. For
more information, see the Fan Speed Measurement section.

ADT7462

Rev. 0 | Page 34 of 92

Using the ADT7462 with 4-Wire Fans

Figure 42 shows the most typical circuit used with 4-wire fans.

ADT7462

TACH

PWM

12V, 4-WIRE FAN

3.3V OR 5V

12V 12V

4.7k

10k

TACH

PWM

69-

Figure 42. Driving a 4-Wire Fan

Because the electronics in a 4-wire fan are powered continuously,
unlike previous PWM driven/powered fans, 4-wire fans tend to
perform better than 3-wire fans, especially for high frequency
applications. It also eliminates the requirement for pulse
stretching, because the TACH signal is always available.

Driving Two Fans from Each PWM

Note that the ADT7462 has up to eight TACH inputs available
for fan speed measurement, but only four PWM drive outputs.
If all eight fans are being used in the system, two fans should be
driven in parallel from each PWM output. Figure 43 shows how
to drive two fans in parallel using the NDT3055L MOSFET.
This information is relevant for low frequency mode only
(2-wire and 3-wire fans), because the PWM and TACHs need to
be synchronized to obtain accurate fan speed measurements
using pulse stretching (see the Fan Speed Measurement with
Pulse Stretching section). In high frequency mode and when
using 4-wire fans, the TACH signal is always valid because the
fan is always powered on.

Note that because the MOSFET can handle up to 3.5 A, it is
simply a matter of connecting another fan directly in parallel
with the first. Care should be taken in designing drive circuits
with transistors and FETs to ensure that the PWM pins are not
required to source current and that they sink less than the 8 mA
maximum current specified on the data sheet.

ADT7462

PWM3

TACH3

TACH7

3.3V

TACH

Q1
NDT3055L

1N4148

5V OR
12V FAN

10k
TYPICAL

569

-
03

Figure 43. Interfacing Two Fans in Parallel to a PWM Output

Using a Single N-Channel MOSFET

ADT7462

Rev. 0 | Page 35 of 92

FAN SPEED MEASUREMENT AND CONTROL

TACH INPUTS

Pin 1, Pin 2, Pin 3, Pin 4, Pin 7, Pin 8, Pin 21, and Pin 22 are
TACH inputs intended for fan speed measurement.

Signal conditioning in the ADT7462 accommodates the slow
rise and fall times typical of fan tachometer outputs. The maxi-
mum input signal range is 0 V to 5 V, even where V

is less

than 5 V. In the event that these inputs are supplied from fan
outputs that exceed 0 V to 5 V, either resistive attenuation of the
fan signal or diode clamping must be included to keep inputs
within an acceptable range.

Figure 44 to Figure 47 show circuits for most common fan
TACH circuits.

If the fan TACH output has a resistive pull-up to V

, it can be

connected directly to the fan input, as shown in Figure 44.

12V

PULL-UP

4.7k

TYPICAL

TACH
OUTPUT

FAN SPEED

COUNTER

TACH

ADT7462

Figure 44. Fan with TACH Pull-Up to V

If the fan output has a resistive pull-up to 12 V (or other voltage
greater than 5 V), the fan output can be clamped with a Zener
diode, as shown in Figure 45. The Zener diode voltage should
be chosen so that it is greater than V

of the TACH input but

less than 5 V, allowing for the voltage tolerance of the Zener. A
value of between 3 V and 5 V is suitable.

12V

PULL-UP

4.7k

TYPICAL

TACH
OUTPUT

FAN SPEED

COUNTER

TACH

ADT7462

ZD1*

*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 × V

CC.

5569-

Figure 45. Fan with TACH Pull-Up to Voltage > 5 V (Example, 12 V),

Clamped with Zener Diode

If the fan has a strong pull-up (less than 1 k) to 12 V or a
totem-pole output, a series resistor can be added to limit the
Zener current, as shown in Figure 46. Alternatively, a resistive
attenuator can be used, as shown in Figure 47. R1 and R2
should be chosen such that

2 V < V

PULLUP

× R2/(R

PULLUP

+ R1 + R2) < 5 V

The fan inputs have an input resistance of nominally 160 k to
ground, so this should be taken into account when calculating
resistor values.

With a pull-up voltage of 12 V and a pull-up resistor of less than
1 k, suitable values for R1 and R2 would be 100 k and 47 k.
This gives a high input voltage of 3.83 V.

5V OR 12V

PULL-UP TYP

<1k OR

TOTEM POLE

TACH
OUTPUT

FAN SPEED

COUNTER

TACH

ADT7462

ZD1
ZENER*

FAN

*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 × V

CC.

10k

5569-

Figure 46. Fan with Strong TACH Pull-Up to > V

or Totem-Pole Output,

Clamped with a Zener Diode and Resistor

12V

<1k

TACH
OUTPUT

FAN SPEED

COUNTER

TACH

ADT7462

R2*

*SEE TEXT

R1*

0
5569-

037

Figure 47. Fan with Strong TACH Pull-Up to > V

or Totem-Pole Output,

Attenuated with R1/R2

FAN SPEED MEASUREMENT

The method of fan speed measurement when using 3-wire fans
differs from that used with 4-wire fans. When 3-wire fans are in
use, power is continuously applied and removed from the fan,
thereby chopping the TACH information. As a result, every time
a fan speed measurement is to be made, the fan must be switched
on for a long enough period of time that a measurement can be
made. This is called pulse stretching. With 4-wire fans, power is
always applied to the fan, so fan speed measurements can be
made continuously, and there is no need for pulse stretching.
Pulse stretching is also not necessary when driving a 3-wire fan
with a dc input. The Fan Speed Measurement Without Pulse
Stretching section and the Fan Speed Measurement with Pulse
Stretching section describe how fan speed is measured both
when pulse stretching is required and when it is not.

ADT7462

Rev. 0 | Page 36 of 92

Fan Speed Measurement Without Pulse Stretching

Fan speed is measured by the ADT7462, and the result is stored
in the fan TACH value registers. The fan counter does not count
the fan TACH output pulses directly because the fan speed can
be less than 1000 rpm, and it would take several seconds to
accumulate a reasonably large and accurate count. Instead, the
period of the fan revolution is measured by gating an on-chip
90 kHz oscillator into the input of a 16-bit counter for N periods of
the fan TACH output (see Figure 48), so the accumulated count
is actually proportional to the fan tachometer period and inversely
proportional to the fan speed.

To enable continuous measurement for 3-wire fans, set the
corresponding dc bit for the TACH input in the TACH configu-
ration register. This bit is set automatically when the HF PWM
is in use with 4-wire fans.

Fan Speed Measurement with Pulse Stretching

The method for measuring fan speed for 3-wire fans requiring
pulse stretching is similar to the method described in the Fan
Speed Measurement Without Pulse Stretching section for
continuous measurements. The main difference is that the PWM
drive must be synchronized to the TACH input so that the
ADT7462 knows that pulse stretching is taking place while the
TACH is being measured.

PWM1 is synchronized with TACH1 and TACH5.
PWM2 is synchronized with TACH2 and TACH6.
PWM3 is synchronized with TACH3 and TACH7.
PWM4 is synchronized with TACH4 and TACH8.

When pulse stretching is enabled, the ADT7462 measures fan
speed once a second. The counter then counts up from the first
to the third TACH pulse; this value is stored in the TACH value
register. The PWM drive returns to its previous programmed value.

To enable fan speed measurements four times a second, set the
FAST bit (Bit 0) of Configuration Register 2 (0x02). When the
FAST bit is set, fan TACH readings are updated every 250 ms.

CLOCK

PWM

TACH

055

69-

0
38

Figure 48. Fan Speed Measurement

Fan Speed Measurement Registers

Fan speed measurement involves a 2-register read for each
measurement. The low byte should be read first. This causes the
high byte to be frozen until both high and low byte registers
have been read, preventing erroneous TACH readings. The fan
tachometer reading registers report back the number of 11.11 s
period clocks (90 kHz oscillator) gated to the fan speed counter,
from the rising edge of the first fan TACH pulse to the rising
edge of the third fan TACH pulse (because two pulses per
revolution are being counted). Because the device is essentially
measuring the fan TACH period, the higher the count value the
slower the fan is actually running. A 16-bit fan tachometer
reading of 0xFFFF indicates either that the fan has stalled or is
running very slowly (<100 rpm).

The actual fan TACH period is being measured; therefore, an
ALERT is generated if the reading falls below a fan TACH limit.
This sets the appropriate status bit and can be used to generate
an SMBALERT. The TACH limit is an 8-bit value that is
compared with the TACH high byte of the TACH reading.

Table 25. Tachometer Value and Limit Registers

TACH

Low Byte
Value Register

High Byte
Value Register

8-Bit Limit
Register

TACH1 0x98

0x99

0x78

TACH2 0x9A

0x9B

0x79

TACH3 0x9C

0x9D

0x7A

TACH4 0x9E

0x9F

0x7B

TACH5 0xA2

0xA3

0x7C

TACH6 0xA4

0xA5

0x7D

TACH7 0xA6

0xA7

0x7E

TACH8 0xA8

0xA9

0x7F

Calculating Fan Speed

Assuming a fan with a two pulses/revolution (and two
pulses/revolution being measured), fan speed is calculated by

Fan Speed (rpm) = (freq × 60)/Fan Tachometer Reading

where:

Fan Tachometer Reading = a 16-bit fan tachometer reading.
freq = oscillator frequency, 90 kHz.

Example:

TACH1 high byte (Register 0x99) = 0x17
TACH1 low byte (Register 0x98) = 0xFF

What is the speed of Fan 1 in rpm?

Fan 1 Tachometer Reading = 0 × 17 FF = 6143 Decimal

RPM = (

× 60)/Fan 1 Tachometer Reading

RPM = (90000 × 60)/6143

Fan Speed = 879 rpm

ADT7462

Rev. 0 | Page 37 of 92

If the fan is a 6-pole fan, the count value is representative of 2/3
of a revolution. Therefore, the result of the equation above
should be divided by 1.5. Similarly, if the fan used is an
8-pole fan, then the result should be divided by 2.

Fan Spin-Up

The ADT7462 has a unique fan spin-up function. It spins the
fan at 100% PWM duty cycle until two TACH pulses are detected
on the TACH input. Once two TACH pulses have been detected,
the PWM duty cycle goes to the expected running value, for
example, 33%. The advantage of this process is that fans have
different spin-up characteristics and take different times to
overcome inertia. The ADT7462 runs the fans just fast enough
to overcome inertia and is quieter on spin-up than fans
programmed to spin up for a given spin-up time.

Fan Start-Up Timeout

To prevent false interrupts being generated as a fan spins up
(because it is below running speed), the ADT7462 includes a
fan start-up timeout function. During this time, the ADT7462
looks for two TACH pulses. If two TACH pulses are not
detected, an interrupt is generated. Using Configuration
Register 1 (0x01), Bit 4, this functionality can be changed to
spinning the fans for a programmable time instead of two
TACH pulses.

The start-up timeout for each PWM drive is programmed by
Bits [2:0] in the PWMx configuration registers.

PWM1 Configuration Register = Register 0x21

PWM2 Configuration Register = Register 0x22

PWM3 Configuration Register = Register 0x23

PWM4 Configuration Register = Register 0x24

Table 26. Fan Start-Up Timeout

Bit Start-Up

Timeout

000

No start-up timeout

001 100

010 250

011 400

100 667

101 1

sec

110 2

sec

111 4

sec

PWM LOGIC STATE

The PWM outputs can be programmed high for 100% duty
cycle (non-inverted) or low for 100% duty cycle (inverted). This
is programmed for each PWM drive in the PWMx Configuration
Registers using the INV bit (Bit 4).

0 = logic low for 100% PWM duty cycle.

1 = logic high for 100% PWM duty cycle.

Low Frequency Mode PWM Drive Frequency

The PWM drive frequency can be adjusted for the application.
The ADT7462 supports both high frequency and low frequency
PWM. High or low frequency PWM mode is selected in
Register 0x02, Bit 2. In high frequency mode, the PWM drive
frequency is always 22.5 kHz and cannot be changed. Register 0x25
and Register 0x26 configure the PWM frequency in low fre-
quency mode for PWM1 to PWM4, respectively.

PWM Drive Frequency 1 is set using Bits [4:2] of the PWM1
and PWM2 frequency register (0x25).

PWM Drive Frequency 2 is set using Bits [7:5] of the PWM1
and PWM2 frequency register (0x25).

PWM Drive Frequency 3 is set using Bits [4:2] of the PWM3
and PWM4 frequency register (0x26).

PWM Drive Frequency 4 is set using Bits [7:5] of the PWM3
and PWM4 frequency register (0x26).

Table 27. Low Frequency PWM Options

Bit Frequency

000 11

001 14.7

010 22.1

011 29.4

100 35.3

101 44.1

110 58.8

111 88.2

FAN SPEED CONTROL

The ADT7462 controls fan speed using two different modes:
automatic and manual.

In automatic fan speed control mode, fan speed is automatically
varied with temperature and without CPU intervention, once
initial parameters are set up. The advantage is that if the system
hangs, it is guaranteed that the system is protected from
overheating. The automatic fan speed control incorporates a
feature called dynamic T

MIN

calibration. This feature reduces the

design effort required to program the automatic fan speed
control loop. For more information on how to program the
automatic fan speed control loop and dynamic T

MIN

operation,

see the Programming the Automatic Fan Speed Control Loop
section.

In manual fan speed control mode, the ADT7462 allows the
duty cycle of any PWM output to be manually adjusted. This is
useful if the user wants to change fan speed in the software or
adjust PWM duty cycle output for test purposes. Bits [7:5] of
Register 0x21 to Register 0x24 (PWM configuration registers)
control the behavior of each PWM output. Once under manual
control, each PWM output can be manually updated by writing to
Register 0xAA to Register 0xAD (PWM duty cycle registers).

ADT7462

Rev. 0 | Page 38 of 92

Programming the PWM Current Duty Cycle Registers

The PWM current duty cycle registers are 8-bit registers that
allow the PWM duty cycle for each output to be set anywhere
from 0% to 100% in steps of 0.39%.

The value to be programmed into the PWM

MIN

given by

(

)

MIN

PWM

Decimal

Value

Example 1:

For a PWM duty cycle of 50%,

Value (Decimal) = 50/0.39 = 128 Decimal
Value = 128 Decimal or 0x80

Example 2:

For a PWM duty cycle of 33%,

Value (Decimal) = 33/0.39 = 85 Decimal
Value = 85 Decimal or 0x54

PWM Duty Cycle Registers

By reading the PWMx current duty cycle registers, the user can
keep track of the current duty cycle on each PWM output, even
when the fans are running in automatic fan speed control mode
or acoustic enhancement mode.

VARY PWM DUTY

CYCLE WITH 8-BIT

RESOLUTION

Figure 49. Control PWM Duty Cycle Manually with a Resolution of 0.39%

ADT7462

Rev. 0 | Page 39 of 92

PROGRAMMING THE AUTOMATIC FAN SPEED
CONTROL LOOP

Note that to more efficiently understand the automatic fan
speed control loop, use of the ADT7462 evaluation board and
software is strongly recommended while reading this section.

This section provides the system designer with an understanding
of the automatic fan control loop and provides step-by-step
guidance on effectively evaluating and selecting critical system
parameters. To optimize system characteristics, the designer
needs to carefully plan system configuration, including the
number of fans, where they are located, and what temperatures are
being measured in the particular system.

The mechanical or thermal engineer who is tasked with the
system thermal characterization should also be involved at the
beginning of the process.

Automatic Fan Control Overview

The ADT7462 can automatically control the speed of fans based
upon the measured temperature. This is done independently
from CPU intervention once initial parameters are set up.

The ADT7462 has a local temperature sensor and up to three
remote temperature channels that can be connected to a CPU
on-chip thermal diode (available on Intel Pentium class and
other CPUs/GPUs). These four temperature channels can be
used as the basis for automatic fan speed control to drive fans
using pulse-width modulation (PWM).

Automatic fan speed control reduces acoustic noise by
optimizing fan speed according to accurately measured
temperature. Reducing fan speed can also decrease system
current consumption. The automatic fan speed control mode
is very flexible, owing to the number of programmable
parameters, including T

MIN

and T

RANGE

. The T

MIN

and T

RANGE

values for a temperature channel and, therefore, for a given fan,
are critical because they define the thermal characteristics of the
system. The thermal validation of the system is one of the most
important steps in the design process, so these values should be
selected carefully.

Figure 50 gives a top-level overview of the automatic fan control
circuitry on the ADT7462. From a systems-level perspective, up
to four system temperatures can be monitored and used to
control four PWM outputs. The four PWM outputs can be used
to control up to eight fans. The ADT7462 allows the speed of
eight fans to be monitored. The Remote 1 and Remote 2
temperature channels have a thermal calibration block, allowing
the designer to individually configure the thermal characteristics of
those temperature channels. For example, the CPU fan can be
run when CPU temperature increases above 60°C and a chassis
fan can be run when the local temperature increases above
45°C. At this stage, the designer has not assigned these thermal
calibration settings to a particular fan drive (PWM) channel.
The right side of Figure 50 shows controls that are fan-specific.
The designer has individual control over parameters such as
minimum PWM duty cycle, fan speed failure thresholds, and
even ramp control of the PWM outputs. Automatic fan control,
then, ultimately allows graceful fan speed changes that are less
perceptible to the system user.

MUX

THERMAL CALIBRATION

MIN

RANGE

THERMAL CALIBRATION

100%

MIN

RANGE

THERMAL CALIBRATION

100%

MIN

RANGE

REMOTE 1

TEMP

LOCAL

TEMP

REMOTE 2

TEMP

TACHOMETER 1
MEASUREMENT

PWM

CONFIG

PWM

MIN

PWM1

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

PWM

GENERATOR

TACHOMETER 2
MEASUREMENT

PWM

CONFIG

PWM

MIN

PWM2

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

PWM

GENERATOR

TACHOMETER 3

AND 4

MEASUREMENT

PWM

CONFIG

PWM

MIN

PWM3

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

PWM

GENERATOR

100%

TACH1

TACH2

TACH3

0
40

Figure 50. Automatic Fan Control Block Diagram

ADT7462

Rev. 0 | Page 40 of 92

STEP 1--CONFIGURING THE MUX

First, the user needs to decide how many temperature channels
are being measured and how many fans need to be controlled
and monitored. Once these decisions have been made, the fans
can be assigned to particular temperature channels. Not only
can fans be assigned to individual channels, but the behavior of
the fans is also configurable. For example, fans can be run under
automatic fan control; they can be run manually (under software
control); or they can be run at the fastest speed calculated by
multiple temperature channels. The MUX is the bridge between
temperature measurement channels and the three PWM outputs.

Bits [7:5] (BHVR) of Register 0x21, Register 0x22, Register 0x23,
and Register 0x24 (PWM configuration registers) control the
behavior of the fans connected to the PWM1, PWM2, PWM3,
and PWM4 outputs. The values selected for these bits determine
how the MUX connects a temperature measurement channel to
a PWM output.

Automatic Fan Control MUX Options

Bits [7:5] (BHVR), Register 0x21, Register 0x22, Register 0x23,
and Register 0x24, control the behavior of the corresponding
PWM outputs (see Table 61).

The fastest speed calculated options pertain to controlling one
PWM output based on multiple temperature channels. The
thermal characteristics of the three temperature zones can be
set to drive a single fan. An example is the fan turning on when
the Remote 1 temperature exceeds 60°C or when the local
temperature exceeds 45°C.

STEP 2--T

MIN

SETTINGS FOR THERMAL

CALIBRATION CHANNELS

MIN

is the temperature at which the fans start to turn on under

automatic fan control. The speed at which the fan runs at T

MIN

programmed later. The T

MIN

values chosen are temperature

channel-specific; for example, 25°C for ambient channel, 30°C
for VRM temperature, and 40°C for processor temperature.

MIN

is an 8-bit value, either twos complement or Offset 64, that

can be programmed in 1°C increments. There is a T

MIN

associated with each temperature measurement channel: local,
Remote 1, Remote 2, and Remote 3. Once the T

MIN

value is

exceeded, the fan turns on and runs at the minimum PWM
duty cycle. The fan turns off once the temperature has dropped
below T

MIN

- T

HYST

MUX

REAR CHASSIS

FRONT CHASSIS

CPU FAN SINK

REMOTE 1 =

AMBIENT TEMP

LOCAL =

VRM TEMP

REMOTE 2 =

CPU TEMP

PWM1

PWM2

TACH1

TACH2

TACH3

PWM3

MUX

THERMAL CALIBRATION

MIN

RANGE

THERMAL CALIBRATION

100%

MIN

RANGE

THERMAL CALIBRATION

100%

MIN

RANGE

TACHOMETER 1
MEASUREMENT

PWM

CONFIG

PWM

MIN

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

PWM

GENERATOR

TACHOMETER 2
MEASUREMENT

PWM

CONFIG

PWM

MIN

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

PWM

GENERATOR

TACHOMETER 3

AND 4

MEASUREMENT

PWM

CONFIG

PWM

MIN

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

PWM

GENERATOR

100%

0
4
1

Figure 51. Assigning Temperature Channels to Fan Channels

ADT7462

Rev. 0 | Page 41 of 92

To overcome fan inertia, the fan is spun up until two valid
TACH rising edges are counted. See the Fan Spin-Up section for
more details. In some cases, primarily for psycho-acoustic reasons,
the fan should never switch off below T

MIN

. The corresponding

bits in Register 0x25 and Register 0x26 should be set to keep the
fans running at the PWM minimum duty cycle, if the temperature
falls below T

MIN

MIN

Registers

MIN

= 0x9A (90°C)

MIN

= 0x9A (90°C)

MIN

= 0x9A (90°C)

MIN

= 0x9A (90°C)

PWM1 and PWM2 Frequency Register (0x25)

Bit 0 (MIN1) = 0, PWM1 is off (0% PWM duty cycle) when
temperature is below T

MIN

- T

HYST

Bit 0 (MIN1) = 1. PWM1 runs at PWM1 minimum duty cycle
below T

MIN

- T

HYST

Bit 1 (MIN2) = 0. PWM2 is off (0% PWM duty cycle) when
temperature is below T

MIN

- T

HYST

Bit 1 (MIN2) = 1. PWM2 runs at PWM2 minimum duty cycle
below T

MIN

- T

HYST

PWM3 and PWM4 Frequency Register (0x26)

Bit 0 (MIN3) = 0. PWM3 is off (0% PWM duty cycle) when
temperature is below T

MIN

- T

HYST

Bit 0 (MIN3) = 1. PWM3 runs at PWM3 minimum duty cycle
below T

MIN

- T

HYST

Bit 1 (MIN4) = 0. PWM4 is off (0% PWM duty cycle) when
temperature is below T

MIN

- T

HYST

Bit 1 (MIN4) = 1. PWM4 runs at PWM4 minimum duty cycle
below T

MIN

- T

HYST

REAR CHASSIS

FRONT CHASSIS

CPU FAN SINK

LOCAL =

VRM TEMP

PWM1

PWM2

TACH1

TACH2

TACH3

PWM3

REMOTE 1 =

AMBIENT TEMP

REMOTE 2 =

CPU TEMP

MUX

THERMAL CALIBRATION

MIN

RANGE

THERMAL CALIBRATION

100%

MIN

RANGE

THERMAL CALIBRATION

100%

MIN

RANGE

TACHOMETER 1
MEASUREMENT

PWM

CONFIG

PWM

MIN

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

PWM

GENERATOR

TACHOMETER 2
MEASUREMENT

PWM

CONFIG

PWM

MIN

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

PWM

GENERATOR

TACHOMETER 3

AND 4

MEASUREMENT

PWM

CONFIG

PWM

MIN

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

PWM

GENERATOR

100%

MIN

569-

042

Figure 52. Understanding the T

MIN

Parameter

ADT7462

Rev. 0 | Page 42 of 92

STEP 3--PWM

MIN

FOR EACH PWM (FAN) OUTPUT

PWM

MIN

is the minimum PWM duty cycle at which each fan in

the system runs. It is also the start speed for each fan under
automatic fan control once the temperature rises above T

MIN

For maximum system acoustic benefit, PWM

MIN

should be as

low as possible. Depending on the fan used, the PWM

MIN

setting is usually in the 20% to 33% duty cycle range. This value
can be found through fan validation.

TEMPERATURE

MIN

100%

PWM

MIN

0
43

Figure 53. PWM

MIN

Determines Minimum PWM Duty Cycle at T

MIN

More than one PWM output can be controlled from a single
temperature measurement channel. For example, Remote 1
temperature can control PWM1 and PWM2 outputs. If two
different fans are used on PWM1 and PWM2, the fan
characteristics can be set up differently. As a result, Fan 1,
driven by PWM1, can have a different PWM

MIN

value than that

of Fan 2 connected to PWM2. Figure 54 illustrates this as
PWM1

MIN

(the front fan) is turned on at a minimum duty cycle

of 20%, while PWM2

MIN

(the rear fan) turns on at a minimum

of 40% duty cycle. Note, however, that both fans turn on at
exactly the same temperature, defined by T

MIN

TEMPERATURE

MIN

100%

PWM1

MIN

DUT

PWM2

MIN

0
44

Figure 54. Operating Two Different Fans from a Single Temperature Channel

Programming the PWM

MIN

Registers

The PWM

MIN

registers are 8-bit registers that allow the

minimum PWM duty cycle for each output to be configured
anywhere from 0% to 100%. This allows the minimum PWM
duty cycle to be set in steps of 0.39%.

The value to be programmed into the PWM

MIN

(

)

MIN

PWM

decimal

Value

Example 1

: For a minimum PWM duty cycle of 50%,

Value (decimal) = 50/0.39 = 128 (decimal)

Value = 128 (decimal) or 0x80 (hex)

Example 2:

For a minimum PWM duty cycle of 33%,

Value (decimal) = 33/0.39 = 85 (decimal)

Value = 85 (decimal) or 0x54 (hex)

PWM

MIN

Registers

Note on Fan Speed and PWM Duty Cycle

The PWM duty cycle does not directly correlate to fan speed in
rpm. Running a fan at 33% PWM duty cycle does not equate to
running the fan at 33% speed. Driving a fan at 33% PWM duty
cycle actually runs the fan at closer to 50% of its full speed. This
is because fan speed in %rpm generally relates to the square
root of PWM duty cycle. Given a PWM square wave as the
drive signal, fan speed in rpm approximates to

cycle

duty

PWM

fanspeed

STEP 4--PWM

MAX

FOR PWM (FAN) OUTPUTS

PWM

MAX

is the maximum duty cycle that each fan in the system

runs at under the automatic fan speed control loop. For
maximum system acoustic benefit, PWM

MAX

should be as low as

possible but should be capable of maintaining the processor
temperature limit at an acceptable level. If the THERM
temperature limit is exceeded, the fans are still boosted to 100%
for fail-safe cooling.

There is one PWM

MAX

limit (Register 0x2C) for all fan channels.

TEMPERATURE

MIN

100%

PWM

MIN

DUTY CY

E PWM

MAX

Figure 55. PWM

MAX

Determines Maximum PWM Duty Cycle

Below the THERM Temperature Limit

ADT7462

Rev. 0 | Page 43 of 92

Programming the PWM

MAX

Register

The PWM

MAX

maximum PWM duty cycle for the outputs to be configured
anywhere from 0% to 100%. This allows the maximum PWM
duty cycle to be set in steps of 0.39%.

The value to be programmed into the PWM

MAX

(

)

MAX

PWM

decimal

Value

Example 1:

For a maximum PWM duty cycle of 50%,

Value (decimal) - 50/0.39 = 128 (decimal)
Value = 128 (decimal) or 0x80 (hex)

Example 2:

For a maximum PWM duty cycle of 75%,

Value (decimal) = 75/0.39 = 85 (decimal)
Value = 192 (decimal) or 0xC0 (hex)

PWM

MAX

Register

See the Note on Fan Speed and PWM Duty Cycle section for
more information.

STEP 5--T

RANGE

FOR TEMPERATURE CHANNELS

RANGE

is the range of temperature over which automatic fan

control occurs once the programmed T

MIN

temperature has

been exceeded. T

RANGE

is a temperature slope, not an arbitrary

value; that is, a T

RANGE

of 40°C holds true only for PWM

MIN

33%. If PWM

MIN

is increased or decreased, the effective T

RANGE

changes.

TEMPERATURE

MIN

100%

PWM

MIN

DUT

Y CY

RANGE

Figure 56. T

RANGE

Parameter Affects Cooling Range

The T

RANGE

or fan control slope is determined by the following

procedure:

Determine the maximum operating temperature for that
channel (for example, 70°C).

Determine experimentally the fan speed (PWM duty cycle
value) that does not exceed the temperature at the worst-
case operating points. (For example, 70°C is reached when
the fans are running at 50% PWM duty cycle.)

Determine the slope of the required control loop to meet
these requirements.

Using the ADT7462 evaluation software, you can

graphically program and visualize this functionality.
Ask your local Analog Devices representative for details.

MIN

100%

33%

50%

30°C

40°C

0
47

Figure 57. Adjusting PWM

MIN

Affects T

RANGE

is implemented as a slope, which means that as PWM

MIN

is changed, T

RANGE

changes, but the actual slope remains the

same. The higher the PWM

MIN

value, the smaller the effective

RANGE

; that is, the fan reaches full speed (100%) at a lower

temperature.

MIN

100%

33%

50%

30°C

40°C

25%

10%

45°C

54°C

Figure 58. Increasing PWM

MIN

Changes Effective T

RANGE

ADT7462

Rev. 0 | Page 44 of 92

For a given T

RANGE

value, the temperature at which the fan runs

at full speed for different PWM

MIN

values can be easily

calculated by

(

)

170

RANGE

MIN

MAX

Min

Max

where:

MAX

is the temperature at which the fan runs full speed.

MIN

is the temperature at which the fan turns on.

Max DC is the maximum duty cycle (100%) = 255 decimal.
Min DC is equal to PWM

MIN

RANGE

is the PWM duty cycle vs. temperature slope.

Example 1:

Calculate T, given that T

MIN

= 30°C, T

RANGE

= 40°C,

and PWM

MIN

= 10% duty cycle = 26 (decimal).

MAX

= T

MIN

+ (Max DC - Min DC) × T

RANGE

/170

MAX

= 30°C + (100% - 10%) × 40°C/170

MAX

= 30°C + (255 - 26) × 40°C/170

MAX

= 84°C (effective T

RANGE

= 54°C)

Example 2:

Calculate T

MAX

, given that T

MIN

= 30°C, T

RANGE

40°C, and PWM

MIN

= 25% duty cycle = 64 (decimal).

MAX

= T

MIN

+ (Max DC - Min DC) × T

RANGE

/170

MAX

= 30°C + (100% - 25%) × 40°C/170

MAX

= 30°C + (255 - 64) × 40°C/170

MAX

= 75°C (effective T

RANGE

= 45°C)

Example 3:

Calculate T

MAX

, given that T

MIN

= 30°C, T

RANGE

40°C, and PWM

MIN

= 33% duty cycle = 85 (decimal).

MAX

= T

MIN

+ (Max DC - Min DC) × T

RANGE

/170

MAX

= 30°C + (100% - 33%) × 40°C/170

MAX

= 30°C + (255 - 85) × 40°C/170

MAX

= 70°C (effective T

RANGE

= 40°C)

Example 4:

Calculate T

MAX

, given that T

MIN

= 30°C, T

RANGE

40°C, and PWM

MIN

= 50% duty cycle = 128 (decimal).

MAX

= T

MIN

+ (Max DC - Min DC) × T

RANGE

/170

MAX

= 30°C + (100% - 50%) × 40°C/170

MAX

= 30°C + (255 - 128) × 40°C/170

MAX

= 60°C (effective T

RANGE

= 30°C)

Selecting a T

RANGE

Slope

The T

RANGE

value can be selected for each temperature channel:

local, Remote 1, Remote 2, and Remote 3. Bits [7:4] (T

RANGE

) of

RANGE

value for each

temperature channel (see Table 84).

Summary of T

RANGE

Function

When using the automatic fan control function, the temperature
at which the fan reaches full speed can be calculated by

RANGE

MIN

MAX

(1)

Equation 1 holds true only when PWM

MIN

is equal to 33% PWM

duty cycle.

Increasing or decreasing PWM

MIN

changes the effective T

RANGE

although the fan control still follows the same PWM duty cycle
to temperature slope. The effective T

RANGE

for different PWM

MIN

values can be calculated using Equation 2

(

)

170

RANGE

MIN

MAX

Min

Max

(2)

where (Max DC - Min DC) × T

RANGE

/170 is the effective T

RANGE

value.

Figure 59 shows PWM duty cycle vs. temperature for each
T

RANGE

setting. The lower graph shows how each T

RANGE

setting

affects fan speed vs. temperature. As can be seen from the
graph, the effect on fan speed is nonlinear.

ADT7462

Rev. 0 | Page 45 of 92

TEMPERATURE ABOVE T

MIN

100

120

SPEED

100

TEMPERATURE ABOVE T

MIN

100

120

M D

Y C

E (%

)

100

2°C

80°C

53.3°C

40°C

32°C

26.6°C

20°C

16°C

13.3°C

10°C

8°C

6.67°C

5°C

4°C

3.33°C

2.5°C

2°C

80°C

53.3°C

40°C

32°C

26.6°C

20°C

16°C

13.3°C

10°C

8°C

6.67°C

5°C

4°C

3.33°C

2.5°C

5569

-
049

Figure 59. T

RANGE

vs. Actual Fan Speed Profile

TEMPERATURE ABOVE T

MIN

100

120

(

)

100

TEMPERATURE ABOVE T

MIN

100

120

EED

(

)

100

2°C

80°C

53.3°C

40°C

32°C

26.6°C

20°C

16°C

13.3°C

10°C

8°C

6.67°C

5°C

4°C

3.33°C

2.5°C

2°C

80°C

53.3°C

40°C

32°C

26.6°C

20°C

16°C

13.3°C

10°C

8°C

6.67°C

5°C

4°C

3.33°C

2.5°C

-
0

Figure 60. T

RANGE

and % Fan Speed Slopes with PWM

MIN

= 20%

The graphs in Figure 59 assume that the fan starts from 0% PWM
duty cycle. Clearly, the minimum PWM duty cycle, PWM

MIN

needs to be factored in to see how the loop actually performs in
the system. Figure 60 shows how T

RANGE

is affected when the

PWM

MIN

value is set to 20%. It can be seen that the fan runs

about 45% fan speed when the temperature exceeds T

MIN

Example: Determining T

RANGE

for Each Temperature

Channel

The following example shows how the different T

MIN

and T

RANGE

settings can be applied to three different thermal zones. In this
example, the following T

RANGE

values apply:

RANGE

= 80°C for ambient temperature

RANGE

= 53.3°C for CPU temperature

RANGE

= 40°C for VRM temperature

This example uses the MUX configuration described in the
Step 1--Configuring the MUX section. Both CPU temperature
and VRM temperature drive the CPU fan connected to PWM1.
Ambient temperature drives the front chassis fan and rear
chassis fan connected to PWM2 and PWM3.

The front chassis fan is configured to run at PWM

MIN

= 20%.

The rear chassis fan is configured to run at PWM

MIN

= 30%.

The CPU fan is configured to run at PWM

MIN

= 10%.

Note on 4-Wire Fans

The control range for 4-wire fans is much wider than that of
2-wire or 3-wire fans. In many cases, 4-wire fans can start with
a PWM drive of as little as 20%.

ADT7462

Rev. 0 | Page 46 of 92

TEMPERATURE ABOVE T

MIN

100

DUT

(

100

TEMPERATURE ABOVE T

MIN

SPEED

X R

100

05569-

Figure 61. T

RANGE

and % Fan Speed Slopes for VRM, Ambient,

and CPU Temperature Channels

STEP 6--T

THERM

FOR TEMPERATURE CHANNELS

THERM

is the absolute maximum temperature allowed on a

temperature channel. Above this temperature, a component
such as the CPU or VRM might be operating beyond its safe
operating limit. When the measured temperature exceeds
T

THERM

, all fans are driven at 100% PWM duty cycle (full speed)

to provide critical system cooling. The fans remain running at
100% until the temperature drops below T

THERM

minus hysteresis,

where hysteresis is the number programmed into Local/Remote 1
Hysteresis Register 0x54 and Remote 2/Remote 3 Hysteresis
Register 0x55. The default hysteresis value is 4°C.

The T

THERM

limit should be considered as the maximum worst-

case operating temperature of the system. Because exceeding
any T

THERM

limit runs all fans at 100%, it has very negative

acoustic effects. Ultimately, this limit should be set up as a fail-
safe, and it must not be exceeded under normal system
operating conditions.

Note that the T

THERM

limits cannot be masked, and they affect

the fan speed no matter how the automatic fan control settings
are configured. This allows some flexibility because a T

RANGE

value can be selected based on its slope, while a hard limit (such
as 70°C), can be programmed as T

MAX

(the temperature at which

the fan reaches full speed) by setting T

THERM

to that limit (for

example, 70°C).

THERM Registers

Hysteresis Registers

Bits [7:4], local temperature hysteresis (4°C default).

Bits [3:0], Remote 1 temperature hysteresis (4°C default).

Bits [7:4], Remote 2 temperature hysteresis (4°C default).

Bits [3:0], Remote 3 temperature hysteresis (4°C default).

Because each hysteresis setting is four bits, hysteresis values are
programmable from 1°C to 15°C. It is not recommended that
hysteresis values ever be programmed to 0°C, because this
disables hysteresis. In effect, this would cause the fans to cycle
between normal speed and 100% speed, creating unsettling
acoustic noise.

ADT7462

Rev. 0 | Page 47 of 92

MIN

100%

THERM

RANGE

HYSTERESIS

556

Figure 62. How T

THERM

Relates to Automatic Fan Control

STEP 7--T

HYST

FOR TEMPERATURE CHANNELS

HYST

is the amount of extra cooling a fan provides after the

temperature measured has dropped back below T

MIN

before the

fan turns off. The premise for temperature hysteresis (T

HYST

) is

that without it, the fan would merely chatter or cycle on and off
regularly whenever the temperature hovers near the T

MIN

setting.

The T

HYST

value chosen determines the amount of time needed

for the system to cool down or heat up as the fan is turning on
and off. Values of hysteresis are programmable in the range 1°C
to 15°C. Larger values of T

HYST

prevent the fans from chattering

on and off. The T

HYST

default value is set at 4°C.

Hysteresis Register

HYST

In some applications, it is required that fans not turn off below T

MIN

but remain running at PWM

MIN

. Bits [1:0] of the PWM1, PWM2

Frequency Register (0x25) and the PWM3, PWM4 Frequency
Register (0x26) allow the fans to be turned off or to be kept
spinning below T

MIN

. If the fans are always on, the T

HYST

value has

no effect on the fan when the temperature drops below T

MIN

MIN

100%

RANGE

THERM

HYST

556

Figure 63. The T

HYST

Value Applies to Fan On/Off Hysteresis

Dynamic T

MIN

Control Mode

In addition to the automatic fan speed control mode described
in the Automatic Fan Control Overview section, the ADT7462
has a mode that extends the basic automatic fan speed control
loop. Dynamic T

MIN

control allows the ADT7462 to intelligently

adapt the system's cooling solution for best system performance
or lowest possible system acoustics, depending on user or design
requirements. Use of dynamic T

MIN

control alleviates the need

to design for worst-case conditions and significantly reduces
system design and validation time.

Designing for Worst-Case Conditions

System design must always allow for worst-case conditions.
In PC design, the worst-case conditions include, but are not
limited to, the following:

Worst-Case Altitude

A computer can be operated at different altitudes. Altitude
affects the relative air density, which alters the effectiveness of
the fan cooling solution. For example, when comparing 40°C
air temperature at 10,000 feet to 20°C air temperature at sea
level, relative air density is increased by 40%. This means that
the fan can spin 40% slower and make less noise at sea level
than at 10,000 feet while keeping the system at the same
temperature at both locations.

Worst-Case Fan

Due to manufacturing tolerances, fan speeds in rpm are
normally quoted with a tolerance of ±20%. The designer
must assume that the fan rpm can be 20% below tolerance.
This translates to reduced system airflow and elevated system
temperature. Note that fans 20% out of tolerance can negatively
impact system acoustics because they run faster and generate
more noise.

Worst-Case Chassis Airflow

The same motherboard can be used in a number of different
chassis configurations. The design of the chassis and the
physical location of fans and components determine the system's
thermal characteristics. Moreover, for a given chassis, the
addition of add-in cards, cables, or other system configuration
options can alter the system airflow and reduce the
effectiveness of the system cooling solution. The cooling
solution can also be inadvertently altered by the end user.
(For example, placing a computer against a wall can block the
air ducts and reduce system airflow.)

FAN

I/O CARDS

POOR CPU

AIRFLOW

VENTS

POWER

SUPPLY

CPU

DRIVE

BAYS

GOOD VENTING =

GOOD AIR EXCHANGE

POOR VENTING =

POOR AIR EXCHANGE

VENTS

FAN

I/O CARDS

GOOD CPU AIRFLOW

FAN

VENTS

POWER

SUPPLY

CPU

DRIVE

BAYS

5569-

054

Figure 64. Chassis Airflow Issues

ADT7462

Rev. 0 | Page 48 of 92

Worst-Case Processor Power Consumption

This data sheet maximum does not necessarily reflect the
true processor power consumption. Designing for worst-case
CPU power consumption can result in a processor becoming
overcooled (generating excess system noise).

Worst-Case Peripheral Power Consumption

The tendency is to design to data sheet maximums for
peripheral components (again overcooling the system).

Worst-Case Assembly

Every system manufactured is unique because of manufac-
turing variations. Heat sinks may be loose fitting or slightly
misaligned. Too much or too little thermal grease may be used.
Variations in application pressure for thermal interface
material can affect the efficiency of the thermal solution.
Accounting for manufacturing variations in every system
is difficult; therefore, the system must be designed for the
worst case.

SUBSTRATE

HEAT

SINK

THERMAL

INTERFACE

MATERIAL

INTEGRATED

HEAT

SPREADER

EPOXY

THERMAL INTERFACE MATERIAL

PROCESSOR

TIMS

CTIM

TIMC

JTIM

TIM

569-

055

Figure 65. Thermal Model

Although a design usually accounts for worst-case conditions in
all these cases, the actual system is almost never operated at
worst-case conditions. The alternative to designing for the
worst case is to use the dynamic T

MIN

control function.

Dynamic T

MIN

Control Overview

Dynamic T

MIN

control mode builds upon the basic automatic

fan control loop by adjusting the T

MIN

value based on system

performance and measured temperature. This is important
because, instead of designing for the worst case, the system
thermals can be defined as operating zones. The ADT7462 can
self-adjust its fan control loop to maintain either an operating
zone temperature or a system target temperature. For example,
it can be specified that ambient temperature in a system be
maintained at 50°C. If the temperature is below 50°C, the fans
might not need to run or might run very slowly. If the
temperature is higher than 50°C, the fans need to throttle up.

The challenge presented by any thermal design is finding the
right settings to suit the system's fan control solution. This can
involve designing for the worst case, followed by weeks of
system thermal characterization and, finally, fan acoustic
optimization (for psycho-acoustic reasons).

Getting the most benefit from the automatic fan control mode
involves characterizing the system to find the best T

MIN

and

RANGE

settings for the control loop and the best PWM

MIN

value

for the quietest fan speed setting. Using the ADT7462's dynamic
T

MIN

control mode, however, shortens the characterization time

and alleviates tweaking the control loop settings, because the
device can self-adjust during system operation.

Dynamic T

MIN

control mode is operated by specifying the

operating zone temperatures required for the system. Remote 1
and Remote 2 channels have dedicated operating point registers.
This allows the system thermal solution to be broken down into
distinct thermal zones. For example, CPU operating temperature
is 70°C, VRM operating temperature is 80°C, and ambient
operating temperature is 50°C. The ADT7462 dynamically
alters the control solution to maintain each zone temperature as
close as possible to its target operating point.

Figure 66 shows an overview of the parameters that affect the
operation of the dynamic T

MIN

control loop.

LOW

MIN

OPERATING

POINT

HIGH

RANGE

TEMPERATURE

THERM

0
556

056

Figure 66. Dynamic T

MIN

Control Loop

Table 28 provides a brief description of each parameter.

Table 28. T

MIN

Control Loop Parameters

Parameter Description

LOW

If the temperature drops below the T

LOW

limit,

an error flag is set in a status register and an
SMBALERT interrupt can be generated.

HIGH

If the temperature exceeds the T

HIGH

limit, an error

flag is set in a status register and an SMBALERT
interrupt can be generated.

MIN

The temperature at which the fan turns on under
automatic fan speed control.

Operating
Point

The maximum target temperature for a particular
temperature zone. The system attempts to
maintain system temperature around the
operating point by adjusting the T

MIN

parameter

of the control loop.

THERM

If the temperature exceeds this critical limit, the
fans can be run at 100% for maximum cooling.

RANGE

Programs the PWM duty cycle vs. temperature
control slope.

ADT7462

Rev. 0 | Page 49 of 92

DYNAMIC T

MIN

CONTROL PROGRAMMING

Because the dynamic T

MIN

control mode is a basic extension of

the automatic fan control mode, the automatic fan control mode
parameters should be programmed first (see Step 1--Configuring
the MUX through Step 8--Operating Points for Temperature
Channels). Then proceed with dynamic T

MIN

control mode

programming.

STEP 8--OPERATING POINTS FOR TEMPERATURE
CHANNELS

The operating point for each temperature channel is the optimal
temperature for that thermal zone. The hotter each zone is
allowed to be, the quieter the system, because the fans are not
required to run as fast. The ADT7462 increases or decreases fan
speeds as necessary to maintain the operating point temperature,
allowing for system-to-system variation and removing the need
for worst-case design. If a sensible operating point value is
chosen, any T

MIN

value can be selected in the system characteri-

zation. If the T

MIN

value is too low, the fans run sooner than

required, and the temperature is below the operating point. In
response, the ADT7462 increases T

MIN

to keep the fans off

longer and to allow the temperature zone to get closer to the
operating point. Likewise, too high a T

MIN

value causes the

operating point to be exceeded, and in turn, the ADT7462
reduces T

MIN

to turn the fans on sooner to cool the system.

Programming the Operating Point Registers

There are two operating point registers, one for the Remote 1
temperature channel and one for the Remote 2 temperature
channel. These 8-bit registers allow the operating point
temperatures to be programmed with 1°C resolution.

Operating Point Registers

Operating Point Hysteresis Register

The operating point hysteresis register sets the value below the
operating point at which T

MIN

begins to reduce.

STEP 9--HIGH AND LOW LIMITS FOR
TEMPERATURE CHANNELS

The low limit defines the temperature at which the T

MIN

value

starts to be increased, if temperature falls below this value. This
has the net effect of reducing the fan speed, allowing the system
to get hotter. An interrupt can be generated when the tempera-
ture drops below the low limit.

The high limit should be set above the operating point but
below the critical THERM point. An interrupt can be generated
when the temperature rises above the high limit.

How Dynamic T

MIN

Control Works

The basic premise is as follows:

Set the target temperature for the temperature zone, which

could be, for example, the Remote 1 thermal diode. This value
is programmed to the Remote 1 operating temperature register.

As the temperature in that zone rises toward and exceeds

the operating point temperature minus hysteresis, T

MIN

reduced, and fan speed increases.

As the temperature drops below the low limit value, T

MIN

increased, and the fan speed is reduced.

Short Cycle and Long Cycle

The ADT7462 implements two loops: a short (or decrease)
cycle and a long (or increase) cycle. The short cycle takes place
every n monitoring cycles. The long cycle takes place every 2n
monitoring cycles. The value of n is programmable for each
temperature channel. The bits are located at the following
register locations:

Dynamic T

MIN

Control Register 2 (0x0C)

Remote 1 = CYR1 = Bits [2:0]

Remote 2 = CYR2 = Bits [5:3]

Table 29. Cycle Bit Assignments

Code

Short Cycle

Long Cycle

000

8 cycles

1 sec

16 cycles

2 sec

001

16 cycles

2 sec

32 cycles

4 sec

010

32 cycles

4 sec

64 cycles

8 sec

011

64 cycles

8 sec

128 cycles

16 sec

100

128 cycles

16 sec

256 cycles

32 sec

101

256 cycles

32 sec

512 cycles

64 sec

110

512 cycles

64 sec

1024 cycles

128 sec

111

1024 cycles

128 sec

2048 cycles

256 sec

The cycle time must be chosen carefully. A long cycle time
means that T

MIN

is updated less often. If your system has very

fast temperature transients, the dynamic T

MIN

control loop is

always lagging. If you choose a cycle time that is too fast, the
full benefit of changing T

MIN

is not realized and needs to change

again on the next cycle. In effect, it is overshooting. It is necessary
to carry out some calibration to identify the most suitable
response time.

Figure 67 shows the steps taken during the short cycle.

IS T1(n) T1(n 1) = 0.5 0.75°C
IS T1(n) T1(n 1) = 1.0 1.75°C
IS T1(n) T1(n 1) > 2.0°C

IS T1(n) >

(OP1 HYS)

YES

IS T1(n) T1(n 1)

0.25°C

DO NOTHING

(SYSTEM

COOLING IS OFF

OR CONSTANT)

YES

DO NOTHING

WAIT n

MONITORING

CYCLES

PREVIOUS

TEMPERATURE

MEASUREMENT

T1 (n 1)

CURRENT

TEMPERATURE

MEASUREMENT

T1(n)

OPERATING

POINT

TEMPERATURE

OP1

DECREASE T

MIN

BY 1°C

DECREASE T

MIN

BY 2°C

DECREASE T

MIN

BY 4°C

569

-
05

Figure 67. Short Cycle Steps

ADT7462

Rev. 0 | Page 50 of 92

Figure 68 shows the steps taken during the long cycle.

WAIT 2n

MONITORING

CYCLES

IS T1(n) < LOW TEMP LIMIT

AND

MIN

< HIGH TEMP LIMIT

AND

MIN

< OP1

AND

T1(n) > T

MIN

IS T1(n) > OP1

YES

INCREASE

MIN

BY 1°C

YES

DECREASE T

MIN

BY 1°C

CURRENT

TEMPERATURE

MEASUREMENT

T1(n)

OPERATING

POINT

TEMPERATURE

OP1

DO NOT

CHANGE

569

-
0
59

Figure 68. Long Cycle Steps

The following examples illustrate some of the circumstances
that might cause T

MIN

to increase, decrease, or stay the same.

Example 1: Normal Operation--No T

MIN

Adjustment

If measured temperature never exceeds the programmed
operating point minus the hysteresis temperature, then
T

MIN

is not adjusted; that is, it remains at its current setting.

If measured temperature never drops below the low
temperature limit, T

MIN

is not adjusted.

MIN

THERM LIMIT

OPERATING

POINT

HIGH TEMP

LIMIT

LOW TEMP

LIMIT

ACTUAL

TEMP

HYSTERESIS

556

060

Figure 69. Temperature Between the Operating Point

and the Low Temperature Limit

Because neither the operating point minus the hysteresis
temperature nor the low temperature limit has been exceeded,
the T

MIN

value is not adjusted, and the fan runs at a speed

determined by the fixed T

MIN

and T

RANGE

values defined in the

automatic fan speed control mode.

Example 2: Operating Point Exceeded; T

MIN

Reduced

When the measured temperature is below the operating point
temperature minus the hysteresis, T

MIN

remains the same. Once

the temperature exceeds the operating temperature minus the
hysteresis (OP - Hyst), T

MIN

starts to decrease as illustrated in

Figure 70. This occurs during the short cycle (see Figure 67).
The rate at which T

MIN

decreases depends on the programmed

value of n. It also depends on how much the temperature has
increased between this monitoring cycle and the last monitoring
cycle; that is, if the temperature has increased by 1°C, then T

MIN

is reduced by 2°C. Decreasing T

MIN

has the effect of increasing

the fan speed, thus providing more cooling to the system.

If the temperature is slowly increasing only in the range (OP -
Hyst), that is, 0.25°C per short monitoring cycle, then T

MIN

does not decrease. This allows small changes in temperature in
the desired operating zone without changing T

MIN

. The long

cycle makes no change to T

MIN

in the temperature range (OP -

Hyst), because the temperature has not exceeded the operating
temperature.

Once the temperature exceeds the operating temperature, the
long cycle causes T

MIN

to be reduced by 1°C every long cycle

while the temperature remains above the operating temperature.
This takes place in addition to the decrease in T

MIN

that would

occur due to the short cycle. In Figure 69, because the
temperature is increasing at a rate 0.25°C per short cycle, no
reduction in T

MIN

takes place during the short cycle.

Once the temperature falls below the operating temperature,
T

MIN

stays the same. Even when the temperature starts to

increase slowly, T

MIN

stays the same, because the temperature

increases at a rate of 0.25°C per cycle.

ADT7462

Rev. 0 | Page 51 of 92

MIN

THERM

LIMIT

OPERATING

POINT

HIGH TEMP

LIMIT

LOW TEMP

LIMIT

HYSTERESIS

DECREASE HERE DUE TO

SHORT CYCLE ONLY

T1(n) T1 (n 1) = 0.5°C

OR 0.75°C = > T

MIN

DECREASES BY 1°C

EVERY SHORT CYCLE

DECREASE HERE DUE TO

LONG CYCLE ONLY

T1(n) T1 (n 1) 0.25°C

AND T1(n) > OP = > T

MIN

DECREASES BY 1°C

EVERY LONG CYCLE

NO CHANGE IN T

MIN

HERE

DUE TO ANY CYCLE BECAUSE

T1(n) T1 (n 1) 0.25°C

AND T1(n) < OP = > T

MIN

STAYS THE SAME

ACTUAL

TEMP

0
61

Figure 70. Effect of Exceeding Operating Point Minus Hysteresis Temperature

Example 3: Temperature Below Low Limit, T

MIN

Increased

When the temperature drops below the low temperature limit,
T

MIN

may increase, as shown in Figure 71. Increasing T

MIN

has

the effect of running the fan more slowly and, therefore, more
quietly. The long cycle diagram in Figure 68 shows the conditions
that need to be true for T

MIN

to increase. Here is a quick summary

of those conditions and the reasons they need to be true.

MIN

may increase, if

The measured temperature has fallen below the low

temperature limit. This means the user must choose the low
limit carefully. It should not be so low that the temperature
never falls below it, because T

MIN

would never increase and

the fans would run faster than necessary.

MIN

is below the high temperature limit. T

MIN

is never allowed

to increase above the high temperature limit. As a result, the
high limit should be sensibly chosen, because it determines
how high T

MIN

can go.

MIN

is below the operating point temperature. T

MIN

should never

be allowed to increase above the operating point temperature,
because the fans do not switch on until the temperature rises
above the operating point.

· The temperature is above T

MIN

. The dynamic T

MIN

control is

turned off below T

MIN

Figure 71 shows how T

MIN

increases when the current

temperature is above T

MIN

and below the low temperature limit,

and T

MIN

is below the high temperature limit and below the

operating point. Once the temperature rises above the low
temperature limit, T

MIN

stays the same.

MIN

OPERATING

POINT

HIGH TEMP

LIMIT

LOW TEMP

LIMIT

ACTUAL

TEMP

HYSTERESIS

THERM

LIMIT

0
62

Figure 71. Increasing T

MIN

for Quieter Operation

Example 4: Preventing T

MIN

from Reaching Full Scale

Because T

MIN

is dynamically adjusted, it is undesirable for T

MIN

to reach full scale (191°C), because the fan would never switch
on. As a result, T

MIN

is allowed to vary only within a specified

range.

· The lowest possible value for T

MIN

is -64°C .

· T

MIN

cannot exceed the high temperature limit.

· If the temperature is below T

MIN

, the fan is switched off or

is running at minimum speed, and dynamic T

MIN

control

is disabled.

ADT7462

Rev. 0 | Page 52 of 92

MIN

PREVENTED

FROM INCREASING

MIN

OPERATING

POINT

HIGH TEMP

LIMIT

LOW TEMP

LIMIT

ACTUAL

TEMP

HYSTERESIS

THERM

LIMIT

05569-

063

Figure 72. T

MIN

Adjustments Limited by High Temperature Limit

Enabling Dynamic T

MIN

Control Mode

Bits [1:0] of Dynamic T

MIN

Control Register 1 (0x0B)

enable/disable dynamic T

MIN

control on the temperature

channels (see Table 43).

Dynamic T

MIN

Control Register 1 (0x0B)

Bit (1) Remote 2 En = 1

enables dynamic T

MIN

control on the

Remote 2 temperature channel. The chosen T

MIN

value is

dynamically adjusted based on the current temperature,
operating point, and high and low limits for this zone.

Remote 2 En = 0

disables dynamic T

MIN

control. The T

MIN

value

chosen is not adjusted and the channel behaves as described in
the Automatic Fan Control Overview section.

Bit (0) Remote 1 En = 1

enables dynamic T

MIN

control on the

Remote 1 temperature channel. The chosen T

MIN

value is

dynamically adjusted based on the current temperature,
operating point, and high and low limits for this zone.

Remote 1 En = 0

disables dynamic T

MIN

control. The T

MIN

value

chosen is not adjusted, and the channel behaves as described in
the Automatic Fan Control Overview section.

STEP 10--MONITORING THERM

Using the operating point limit ensures that the dynamic T

MIN

control mode is operating in the best possible acoustic position,
while ensuring that the temperature never exceeds the
maximum operating temperature. Using the operating point
limit allows T

MIN

to be independent of system-level issues

because of its self-corrective nature. In PC design, the operating
point for the chassis is usually the worst-case internal chassis
temperature.

The optimal operating point for the processor is determined by
monitoring the thermal monitor in the Intel Pentium 4
processor. To do this, the PROCHOT output of the Pentium 4 is
connected to the THERM input of the ADT7462.

The operating point for the processor can be determined by
allowing the current temperature to be copied to the operating
point register when the PROCHOT output pulls the THERM
input low on the ADT7462. This gives the maximum
temperature at which the Pentium 4 can run before clock
modulation occurs.

Enabling the THERM Trip Point as the Operating Point

Bits [5:2] of Dynamic T

MIN

Control Register 1 (0x0B)

enable/disable THERM monitoring to program the operating
point. Table 43 details how the remote temperatures can be
copied into the operating point registers on a THERM
assertion. Setting these bits to 1 uses the remote temperature as
the operating point temperature, overwriting the programmed
operating point value in the event of a THERM assertion.
Setting these bits to 0 ignores a THERM assertion, and the
operating point register remains at the programmed value.

ENHANCING SYSTEM ACOUSTICS

Automatic fan speed control mode reacts instantaneously to
changes in temperature; that is, the PWM duty cycle responds
immediately to temperature change. Any impulses in temperature
can cause an impulse in fan noise. For psycho-acoustic reasons,
the ADT7462 can prevent the PWM output from reacting
instantaneously to temperature changes. Enhanced acoustic
mode controls the maximum change in PWM duty cycle at a
given time. The objective is to prevent the fan from cycling up
and down, annoying the user.

Acoustic Enhancement Mode Overview

Figure 73 gives a top-level overview of the automatic fan control
circuitry on the ADT7462 and shows where acoustic enhancement
fits in. Acoustic enhancement is intended as a post-design tweak
made by a system or mechanical engineer evaluating best set-
tings for the system. Having determined the optimal settings for
the thermal solution, the engineer can adjust the system acoustics.
The goal is to implement a system that is acoustically pleasing
without causing user annoyance due to fan cycling. It is
important to realize that although a system might pass an
acoustic noise requirement specification (for example, 36 dB),
if the fan is annoying, it fails the consumer test.

ADT7462

Rev. 0 | Page 53 of 92

ACOUSTIC

ENHANCEMENT

REAR CHASSIS

FRONT CHASSIS

CPU FAN SINK

LOCAL =

VRM TEMP

PWM1

PWM2

TACH1

TACH2

TACH3

PWM3

REMOTE 1 =

AMBIENT TEMP

REMOTE 2 =

CPU TEMP

MUX

THERMAL CALIBRATION

MIN

RANGE

THERMAL CALIBRATION

100%

MIN

RANGE

THERMAL CALIBRATION

100%

MIN

RANGE

TACHOMETER 1
MEASUREMENT

PWM

CONFIG

PWM

MIN

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

PWM

GENERATOR

TACHOMETER 2
MEASUREMENT

PWM

CONFIG

PWM

MIN

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

PWM

GENERATOR

TACHOMETER 3

AND 4

MEASUREMENT

PWM

CONFIG

PWM

MIN

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

PWM

GENERATOR

100%

569

-
06

Figure 73. Acoustic Enhacement Smoothes Fan Speed Variations Under Automatic Fan Speed Control

Approaches to System Acoustic Enhancement

There are two different approaches to implementing system
acoustic enhancement: temperature-centric and fan-centric.

The temperature-centric approach involves smoothing transient
temperatures as they are measured by a temperature source (for
example, Remote 1 temperature). The temperature values used
to calculate the PWM duty cycle values are smoothed, reducing
fan speed variation. However, this approach causes an inherent
delay in updating fan speed and causes the thermal characteristics
of the system to change. It also causes the system fans to stay on
longer than necessary, because the fan's reaction is merely
delayed. The user has no control over noise from different fans
driven by the same temperature source. Consider, for example,
a system in which control of a CPU cooler fan (on PWM1) and a
chassis fan (on PWM2) use Remote 1 temperature. Because the
Remote 1 temperature is smoothed, both fans are updated at
exactly the same rate. If the chassis fan is much louder than the
CPU fan, there is no way to improve its acoustics without
changing the thermal solution of the CPU cooling fan.

The fan-centric approach to system acoustic enhancement
controls the PWM duty cycle, driving the fan at a fixed rate
(for example, 6%). Each time the PWM duty cycle is updated, it
is incremented by a fixed 6%. As a result, the fan ramps
smoothly to its newly calculated speed. If the temperature starts
to drop, the PWM duty cycle immediately decreases by 6% at
every update. Therefore, the fan ramps smoothly up or down
without inherent system delay.

Consider, for example, controlling the same CPU cooler fan (on
PWM1) and chassis fan (on PWM2) using Remote 1 temperature.
The T

MIN

and T

RANGE

settings have already been defined in

automatic fan speed control mode; that is, thermal characteri-
zation of the control loop has been optimized. Now the chassis
fan is noisier than the CPU cooling fan. Using the fan-centric
approach, PWM2 can be placed into acoustic enhancement
mode independently of PWM1. The acoustics of the chassis fan
can, therefore, be adjusted without affecting the acoustic
behavior of the CPU cooling fan, even though both fans are
controlled by Remote 1 temperature. The fan-centric approach
is how acoustic enhancement works on the ADT7462.

Enabling Acoustic Enhancement for Each PWM Output

Enhance Acoustics Register 1 (0x1A)

Bit 0 = EA1_En = 1

enables acoustic enhancement on PWM1

output.

Bit 1 = EA2_En = 1

enables acoustic enhancement on PWM2

output.

Enhance Acoustics Register 2 (0x1B)

Bit 0 = EA3_En = 1 e

nables acoustic enhancement on PWM3

output.

Bit 1 = EA4_En = 1

enables acoustic enhancement on PWM4

output.

ADT7462

Rev. 0 | Page 54 of 92

Effect of Ramp Rate on Enhanced Acoustic Mode

The PWM signal driving the fan has a period, T, given by the
PWM drive frequency, f, because T = 1/f. For a given PWM
period, T, the PWM period is subdivided into 255 equal time
slots. One time slot corresponds to the smallest possible
increment in the PWM duty cycle. A PWM signal of 33% duty
cycle is, therefore, high for 1/3 × 255 time slots and low for 2/3
× 255 time slots. Therefore, a 33% PWM duty cycle corresponds
to a signal that is high for 85 time slots and low for 170 time
slots.

170

TIME SLOTS

PWM OUTPUT
(ONE PERIOD)

= 255 TIME SLOTS

PWM_OUT

33% DUTY

CYCLE

05569-

065

Figure 74. 33% PWM Duty Cycle Represented in Time Slots

The ramp rates in the enhanced acoustics mode are selectable
from 1 to 8. The ramp rates are discrete time slots. For example,
if the ramp rate is 8, then eight time slots are added to the PWM
high duty cycle each time the PWM duty cycle needs to be
increased. If the PWM duty cycle value needs to be decreased, it
is decreased by eight time slots. Figure 75 shows how the
enhanced acoustics mode algorithm operates.

READ

TEMPERATURE

CALCULATE

NEW PWM

DUTY CYCLE

IS NEW PWM

VALUE >

PREVIOUS

VALUE?

INCREMENT

PREVIOUS

PWM VALUE

BY RAMP RATE

YES

DECREMENT

PREVIOUS

PWM VALUE

BY RAMP RATE

569

-
06

Figure 75. Enhanced Acoustics Algorithm

The enhanced acoustics mode algorithm calculates a new PWM
duty cycle based on the temperature measured. If the new
PWM duty cycle value is greater than the previous PWM value,
the previous PWM duty cycle value is incremented by either 1,
2, 3, 5, 8, 12, 24, or 48 time slots, depending on the settings of
the enhance acoustics registers. If the new PWM duty cycle
value is less than the previous PWM value, the previous PWM
duty cycle is decremented by 1, 2, 3, 5, 8, 12, 24, or 48 time slots.
Each time the PWM duty cycle is incremented or decremented,
its value is stored as the previous PWM duty cycle for the next
comparison.

A ramp rate of 1 corresponds to one time slot, which is 1/255 of
the PWM period. In enhanced acoustics mode, incrementing or
decrementing by 1 changes the PWM output by 1/255 × 100%.

STEP 11--RAMP RATE FOR ACOUSTIC
ENHANCEMENT

The optimal ramp rate for acoustic enhancement can be found
through system characterization after the thermal optimization
has been finished. The effect of each ramp rate should be logged, if
possible, to determine the best setting for a given solution.

Enhanced Acoustic Register 1 (0x1A)

Bits [4:2] RR1

select the ramp rate for PWM1.

000 = 1 time slot = 35 seconds
001 = 2 time slots = 17.6 seconds
010 = 3 time slots = 11.8 seconds
011 = 5 time slots = 7 seconds
100 = 8 time slots = 4.4 seconds
101 = 12 time slots =3 seconds
110 = 24 time slots = 1.6 seconds
111 = 48 time slots = 0.8 seconds

Bits [7:5] RR2 s

elect the ramp rate for PWM2.

Enhanced Acoustic Register 2 (0x1B)

Bits [4:2] RR3 s

elects the ramp rate for PWM3.

000 = 1 time slot = 35 seconds
001 = 2 time slots = 17.6 seconds
010 = 3 time slots = 11.8 seconds
011 = 5 time slots = 7 seconds
100 = 8 time slots = 4.4 seconds
101 = 12 time slots = 3 seconds
110 = 24 time slots = 1.6 seconds
111 = 48 time slots = 0.8 seconds

Bits [7:5] RR4

select the ramp rate for PWM4.

000 = 1 time slot = 35 seconds
001 = 2 time slots = 17.6 seconds
010 = 3 time slots = 11.8 seconds
011 = 5 time slots = 7 seconds
100 = 8 time slots = 4.4 seconds
101 = 12 time slots = 3 seconds
110 = 24 time slots = 1.6 seconds
111 = 48 time slots = 0.8 seconds

ADT7462

Rev. 0 | Page 55 of 92

Another way to view the ramp rates is to measure the time it
takes for the PWM output to ramp up from 0% to 100% duty
cycle for an instantaneous change in temperature. This can be
tested by putting the ADT7462 into manual mode and changing
the PWM output from 0% to 100% PWM duty cycle. The PWM
output takes 35 seconds to reach 100% when a ramp rate of
1 time slot is selected.

Figure 76 shows remote temperature plotted against PWM duty
cycle for enhanced acoustics mode. The ramp rate is set to 48,
which corresponds to the fastest ramp rate. Assume that a new
temperature reading is available every 115 ms. With these
settings, it takes approximately 0.76 seconds to go from 33%
duty cycle to 100% duty cycle (full speed). Even though the
temperature increases very rapidly, the fan ramps up to full
speed gradually.

TIME (s)

140

0.76

120

100

120

100

TEMP

(°C)

PWM CYCLE (%)

055

69-

067

Figure 76. Enhanced Acoustics Mode with Ramp Rate = 48

Figure 77 shows how changing the ramp rate from 48 to 8
affects the control loop. The overall response of the fan is
slower. Because the ramp rate is reduced, it takes longer for the
fan to achieve full running speed. In this case, it takes
approximately 4.4 seconds for the fan to reach full speed.

TIME (s)

120

4.4

140

120

100

TEMP

(°C)

PWM DUTY CYCLE (%)

569-

068

Figure 77. Enhanced Acoustics Mode with Ramp Rate = 8

Figure 78 shows the PWM output response for a ramp rate of 2.
In this instance, the fan took about 17.6 seconds to reach full
running speed.

TIME (s)

140

17.6

120

100

120

100

TEMP

(°C)

PWM DUTY CYCLE (%)

5569-

0
69

Figure 78. Enhanced Acoustics Mode with Ramp Rate = 2

Figure 79 shows how the control loop reacts to temperature
with the slowest ramp rate. The ramp rate is set to 1, while all
other control parameters remain the same. With the slowest
ramp rate selected, it takes 35 seconds for the fan to reach full
speed.

TIME (s)

120

100

140

120

100

TEMP

(°C)

PWM DUTY CYCLE (%)

05569-

070

Figure 79. Enhanced Acoustics Mode with Ramp Rate = 1

As Figure 76 to Figure 79 show, the rate at which the fan reacts
to temperature change is dependent on the ramp rate selected in
the enhanced acoustics registers. The higher the ramp rate, the
faster the fan reaches the newly calculated fan speed.

Figure 80 shows the behavior of the PWM output as temperature
varies. As the temperature increases, the fan speed ramps up.
Small drops in temperature do not affect the ramp-up function,
because the newly calculated fan speed is still higher than the
previous PWM value. Enhanced acoustics mode allows the
PWM output to be made less sensitive to temperature
variations. This is dependent on the ramp rate selected and
programmed into the enhanced acoustics registers.

ADT7462

Rev. 0 | Page 56 of 92

PWM DUTY CYCLE (%)

TEMP

(°C)

Figure 80. How Fan Reacts to Temperature Variations

in Enhanced Acoustics Mode

Slower Ramp Rates

The ADT7462 can be programmed for much longer ramp times
by slowing the ramp rates. Each ramp rate can be slowed by a
factor of 4.

PWM1 Configuration Register (0x21)

PWM2 Configuration Register (0x22)

PWM3 Configuration Register (0x23)

PWM4 Configuration Register (0x24)

Setting Bit 3 (the SLOW bit) to 1 in the PWM1 to PWM4
registers slows the ramp rate for PWM4 by 4.

FAN FREEWHEELING TEST MODE

The fan freewheeling test mode is intended to diagnose whether
fans connected to the ADT7462 are working properly. It is
particularly useful in the situation where fans coupled in the
duct can affect the airflow of the other fan. If one fan has failed,
it may not be apparent, as moving air from other fans can cause
air to flow through the faulty fan, which in turn can cause the
faulty fan to rotate.

The fan freewheeling test is most useful in a system using
primary and redundant setup. In such a system the following
setup is recommended. The primary fans are Fan 1, Fan 2, Fan 3,
and Fan 4. The redundant fans are Fan 5, Fan 6, Fan 7, and Fan 8.
In this setup, each primary and redundant fan can be driven
separately because they are driven by different PWMs.

PWM 1

PWM 2

PWM 3

PWM 4

TACH CCT 1

TACH CCT 2

TACH CCT 3

TACH CCT 4

FAN 1

FAN 2

FAN 3

FAN 4

FAN 5

FAN 6

FAN 7

FAN 8

5569-

072

Figure 81. Fan Freewheeling Test Mode Setup

The freewheeling test procedure is as follows:

PWM1 and PWM2 go to full speed, and PWM3 and PWM4
are switched off.

After the spin-up time of PWM1 and PWM2 has elapsed,
the speed of Fan 1, Fan 2, Fan 3, and Fan 4 is measured.

Once the speed of Fan 1 and Fan 2 is measured, PWM1 is
switched off and PWM3 is spun up. After the spin-up time for
PWM3 has elapsed, the speed of Fan 5 and Fan 6 is measured.

After the speed of Fan 3 and Fan 4 is measured, PWM2 is
switched off and PWM4 is switched on. After the spin-up
time of PWM4 has elapsed, the speed of Fan 7 and Fan 8
is measured.

Once the speed of all eight fans has been measured, the TACH
and PWM configurations go back to their previous values.

a. Fans must be in continuous mode for the freewheeling

test; that is, the dc bits must be set (Register 0x08).

b. To enable the freewheeling test, set the freewheeling test

enable register (0x1E) to a non-zero value. Set Bit 0 to 1
to enable the freewheeling test for Fan 1, and set Bit 1 for
Fan 2, all the way to Bit 7 for Fan 8. The freewheeling test
enable register should be programmed after the fans
present register is programmed. If the fans present register
is programmed first, then the values in the two registers do
not match, and the ADT7462 assumes that a fan is missing.

The following registers must be programmed for the fan
freewheeling test:

Fans Present Register (0x1D)

Set Bit 0 to 1 when a fan is connected to TACH1.
Set Bit 1 to 1 when a fan is connected to TACH2.
Set Bit 2 to 1 when a fan is connected to TACH3.
Set Bit 3 to 1 when a fan is connected to TACH4.
Set Bit 4 to 1 when a fan is connected to TACH5.
Set Bit 5 to 1 when a fan is connected to TACH6.
Set Bit 6 to 1 when a fan is connected to TACH7.
Set Bit 7 to 1 when a fan is connected to TACH8.

Fan Freewheeling Test Enable Register (0x1E)

Set Bit 0 to 1 to enable the freewheeling test for Fan 1.
Set Bit 1 to 1 to enable the freewheeling test for Fan 2.
Set Bit 2 to 1 to enable the freewheeling test for Fan 3.
Set Bit 3 to 1 to enable the freewheeling test for Fan 4.
Set Bit 4 to 1 to enable the freewheeling test for Fan 5.
Set Bit 5 to 1 to enable the freewheeling test for Fan 6.
Set Bit 6 to 1 to enable the freewheeling test for Fan 7.
Set Bit 7 to 1 to enable the freewheeling test for Fan 8.

Fan Freewheeling Test Register (0x1C)

Both the fans present register (0x1D) and freewheeling test enable
register (0x1E) should be programmed before setting the
relevant bits in the freewheeling test register (0x1C). The host
fan status register (0xBD) should be read directly after completion
of the test.

ADT7462

Rev. 0 | Page 57 of 92

THERM I/O OPERATION

This section describes the operation of THERM1 and THERM2.
Pin 28 and Pin 29 can both be configured as THERM inputs or
outputs.

THERM Output

THERM is not enabled as an output by default on power-up,
but it can be enabled by setting the appropriate bits in
Register 0x0E (THERM1 configuration register) and
Register 0x0F (THERM2 configuration register). THERM1 and
THERM2 can be configured to assert whenever a specific
channel exceeds the specified THERM limit (see Table 30).

Table 30. THERM O/P Channel Select and Limits

Channel
Enable Configuration

Limit

Registers

THERM1,
Register 0x0E

THERM2,
Register 0x0F

THERM1 THERM2

Local

Bit 1 = 1

0x4C

0x50

Remote 1

Bit 2 = 1

0x4D

0x51

Remote 2

Bit 3 = 1

0x4E

0x52

Remote 3

Bit 4 = 1

0x4F

0x53

As an output, THERM is asserted low to signal that the measured
THERM temperature has exceeded preprogrammed THERM
temperature limits. The output is automatically pulled high again
when the temperature falls below the (THERM - Hysteresis) limit.
The value of hysteresis for each channel is programmable in
Register 0x54 and Register 0x55, where 1 LSB = 1°C, and the
maximum hysteresis for each channel is 15°C.

100°C

90°C

80°C

70°C

60°C

50°C

40°C

THERM

THERM LIMIT

THERM LIMITHYSTERESIS

TEMPERATURE

HIGH TEMP LIMIT

RESET BY MASTER

ALERT

05569

-
073

Figure 82. THERM Behavior

Setting the THERM boost bits, Bit 0 and Bit 1, to logic zero
(default setting) in the THERM configuration register (0x0D),
sets the fans to full speed on an internal THERM event.

THERM Input

To configure THERM as an input, the Enable_THERM1_Timer
bit (Bit 0) in the THERM1 configuration register (0x0E) and the
Enable_THERM2_Timer bit (Bit 0) in the THERM2 configuration
register (0x0F) must be set to Logic 1. The ADT7462 can then
be used to detect when the THERM pins are asserted low. The
THERM pins can be connected to a trip point temperature
sensor or to the PROCHOT output of a CPU.

With processor core voltages reducing all the time, the threshold
for the AGTL+ PROCHOT output also reduces as new
processors become available.

Because the THERM input is typically an AGTL+ input, the
thresholds can be referenced to V

CCP

. By setting Bit 4 of

Configuration Register 3 (0x03) to 1, the THERM threshold is
2/3 × V

CCP

, the correct threshold for an AGTL+ signal. The

THERM assert bits in Host Thermal Status Register 2 (0xB9)
are set to Logic 1 whenever the THERM input is asserted low.
The THERM state bits in Host Thermal Status Register 2 (0xB9)
indicate that a high-to-low transition has taken place on the
THERM pin.

THERM Timer

The ADT7462 can also measure assertion times on the THERM
inputs as a percentage of a timer window. The timer window for
the THERM1 input is programmed using Bits [4:2] of the
THERM configuration register (0x0D). The timer window for
the THERM2 input is programmed using Bits [7:5] of the THERM
configuration register (0x0D). Values of between 0.25 seconds
and 8 seconds are programmable (see Table 31).

Table 31. THERM Timer Window

Code

THERM Timer Window

000 0.25

sec

001 0.5

sec

010 1

sec

011 2

sec

100

4 sec

101

8 sec

110 8

sec

111 8

sec

ADT7462

Rev. 0 | Page 58 of 92

The assertion time as a percentage of the time window is stored
in the THERM % on-time registers. This is a cumulative sum of
the percentage of time during the THERM timer window that
THERM is asserted. The % on-time and associated timer limit
registers are listed in Table 32.

Table 32. THERM On-Time and Timer Limit Register

Channel

% On-Time Register

% Timer Limit Register

THERM1

0xAE 0x80

THERM2

0xAF 0x81

Once the measured percentage exceeds the corresponding per-
centage limit, the THERM % bit in Thermal Status Register 2
gets asserted, and an ALERT is generated (that is, if the mask bit
is not set). If the limit is set to 0x00, an ALERT is generated on
the first assertion. If the Limit is set to FFh, an ALERT is never
generated because 0xFF corresponds to the THERM input
being asserted all the time.

When THERM is configured as an input only, setting Bits [1:4]
of the THERM zone in THERM1 configuration register (0x0E)
and THERM2 configuration register (0x0F) allows Pin 7 to
operate as an I/O.

THERM % Limit Register

The THERM % limit is programmed to Register 0x80 and
Register 0x81. If the THERM is asserted for longer than the
programmed percentage limit, then an ALERT is generated.
The limit is programmed as a percentage of the chosen THERM
timer window.

Example:

The THERM timer window is eight seconds, and an ALERT
should be generated if the THERM is asserted for more than
one second.

100

Limit

The THERM % limit register is an 8 bit register.

0x00 = 0% 0xFF = 100%

Therefore, 1 LSB = 0.39%

00100000

dec

Once the time window has elapsed, if the THERM limit has
been exceeded, then an ALERT is generated.

ADT7462

Rev. 0 | Page 59 of 92

GENERAL-PURPOSE I/O PINS

The ADT7462 has eight open drain GPIO pins. GPIO1 to
GPIO4 can be configured to enable event driven outputs
(EDOs), and GPIO5 and GPIO6 can act as EDOs, if the EDO
functionality is enabled. Two other GPIOs (GPIO 7 and GPIO 8)
are standard GPIO pins that are dedicated to general-purpose
logic input/output.

Each GPIO pin has five data bits associated with it: three bits in
a GPIO configuration register (0x09 and 0x0A), one in the
GPIO status register (0xBF), and one in the GPIO mask register
(0x38).

SETTING a direction bit to 1 in a GPIO configuration register
makes the corresponding GPIO pin an output.

CLEARING the direction bit to 0 makes the corresponding
GPIO an input.

SETTING a polarity bit to 1 in a GPIO configuration register
makes the corresponding GPIO pin active high.

CLEARING the polarity bit to 0 makes the corresponding
GPIO active low.

When a GPIO pin is configured as an input, the corresponding
bit in the GPIO status registers is read only, and it is set when
the input is asserted ("asserted" can be high or low, depending
on the setting of the polarity bit).

When a GPIO pin is configured as an output, the corresponding
bit in the GPIO status registers becomes read/write. Setting this
bit then asserts the GPIO output. (Again, "asserted" can be high
or low, depending on the setting of the polarity bit.) The effect
of a GPIO status register bit on the INT output can be masked
by setting the corresponding bit in one of the GPIO mask
registers.

When the pin is configured as an output, this bit is automatically
masked to prevent the data written to the status bit from causing
an interrupt. When configured as inputs, the GPIO pins can be
connected to external interrupt sources such as temperature
sensors with digital output.

EDO CIRCUITRY

The ADT7462 has the added functionality that the assertion of
one of the four GPIOs (GPIO1 to GPIO4) can be used to latch
one of the two EDOs high or low. The ADT7462 has two EDO
event mask registers (0x37 and 0x38): one mask for each EDO.
See Table 33 for an explanation of event mask register
functionality.

The polarity of the EDOs is set in the GPIO configuration
registers (0x09 and 0x0A).

SETTING a polarity bit to 1 in one of the GPIO configuration
registers makes the corresponding GPIO pin active high.

CLEARING the polarity bit to 0 makes it active low.

GPIO1
GPIO2
GPIO3
GPIO4

LATCH

EVENT

MASK

EDO (GPIO 5)

EDO (GPIO 6)

Figure 83. EDO Circuit

Bits [7:5] of each event mask register allow the EDO output to be
driven high or low (depending on the polarity bit of the
configuration register) and latched (depending on the EDO latch
bit of the configuration register), if the ADT7462 detects an
overtemperature, an over/undervoltage, or a fan failure condition.

Table 33. EDO Control (Mask) Register 0x37 and Register 0x38

Bit 7: Over/Under Voltage

Bit 6: THERM

Bit5: Fan Fail

Bit 3

Bit 2

Bit 1

Bit 0

Behavior: What Drives and Latches Output X
(G = GPIO)

0 = Drive
Output X

G4 or G3 or G2 or G1

1 = Ignore Event

G4 or G3 or G2

0 0 1 0 G4

0 0 1 1 G4

0 1 0 0 G4

0 1 0 1 G4

0 1 1 0 G4

0 1 1 1 G4

1 0 0 0 G3

1 0 0 1 G3

1 0 1 0 G3

1 0 1 1 G3

1 1 0 0 G2

1 1 0 1 G2

1 1 1 0 G1

1 1 1 1 GPIO

events

Ignored

Output

ADT7462

Rev. 0 | Page 60 of 92

Table 33 shows that any of the four designated GPIO pins can
be used to set or reset anyone of the two EDO outputs.

Using this functionality, it is possible to have the ADT7462
drive LEDs or signals based on rules. For example, if a GPIO1
(power fail), a GPIO2 (overcurrent), or an overtemperature
condition occurs, EDO1 (power supply fault LED) can be
latched. This does not require software handling and makes the
part more autonomous.

OTHER DIGITAL INPUTS

The ADT7462 contains other specific digital inputs that can be
found on PC motherboards. These inputs can be monitored and
configured for actions to occur on their assertion.

VR_HOT inputs

Pin 25 and Pin 26 can be configured as VR_HOT inputs. These
are specific digital signals from the CPU voltage regulator that
indicate an overtemperature. On assertion of these inputs, the
relevant status bits are set in the Thermal Status Register 2
(Host Register 0xB9 or BMC Register 0xC1). Assertion of these
inputs can also be used to boost the fans to full speed, thus
providing emergency cooling in the event of VR overtemperature.
This is set using Bit 3 and Bit 4 of Configuration Register 2
(0x02). There is also an associated mask bit in Register 0x31 to
mask the assertion of these inputs from the ALERT output.

SCSI_TERM inputs

Pin 16 and Pin 20 can be configured as SCSI_TERM inputs. An
assertion on the SCSI_TERM is recorded in Bit 4 and Bit 5 of
Digital Status Register 1 (Host Register 0xBE or BMC register
0xC6). There is also an associated mask bit in Register 0x35 to
mask the assertion of these inputs from the ALERT output.

RESET I/O

The ADT7462 includes an active low reset pin (Pin 14). The
RESET pin can be both a reset input and output. RESET
monitors the V

input to the ADT7462. At power-up, RESET

is asserted (pulled low) until 180 ms after the power supply has
risen above the supply threshold. A power-on reset initializes all
registers to the default values.

180ms

RESET

Figure 84. Operation of RESET Output on Power-Up

The RESET pin can also function as a reset input. Pulling this
pin low externally resets the ADT7462. The user should wait at
least 180 ms after power-up before doing a hardware reset. The
reset pulse width should be greater than 0.8 ms to ensure that a
reset is registered.

A hardware reset differs from a power-on reset in that not all of

the registers are re-initialized to the default values. For example,
limit registers are not all restored to the default values. This can
be useful if the user needs to reset the part but does not want to
completely reprogram the device. The Register Map shows which
registers are reset. Locked registers are not restored to default
values by a hardware reset.

Note that if two ADT7462 devices are used in one system, the
RESET pins should not be connected together between devices.
Doing so would cause one device to reset the other on a power-
on reset.

Software Reset

The ADT7462 can be reset in software by setting Bit 7 of
Configuration Register 0 (0x00). The code 0x6D must be written to
Register 0x7B before setting the software reset bit. This register is
cleared to the power-on default after the software reset.

Note that not all registers are restored to their default values on
a reset. The same registers are reset by a hardware and software
reset. The Register Map section shows a complete reference of
registers that are reset.

CHASSIS INTRUSION INPUT

The chassis intrusion input is an active high input intended for
detection and signaling of unauthorized tampering with the
system. When this input goes high, the event is latched in Bit 7
of the digital status register (0xBE), and an interrupt is generated.
The bit remains set until cleared by writing a 1 to CI reset, Bit 5
of Configuration Register 3 (0x03). The CI reset bit itself is
cleared by writing a 0 to it.

The CI circuit is powered from the V

BATT

voltage channel. Pin 26

must be configured to monitor V

BATT

and a battery connected in

order to monitor CI events. CI monitoring is disabled if the
measured V

BATT

value (0x93) is less than the lower voltage limit

(0x75) of Pin 26.

The CI input detects chassis intrusion events even when the
ADT7462 is powered off (provided battery voltage is applied to
V

BATT

) but does not immediately generate an interrupt. Once a

chassis intrusion event is detected and latched, an interrupt is
generated when the system is powered on.

The actual detection of chassis intrusion is performed by an
external circuit that detects, for example, when the cover has
been removed. A wide variety of techniques can be used for the
detection. For example:

A microswitch that opens or closes when the cover is removed

A reed switch operated by a magnet affixed to the cover

A hall-effect switch operated by a magnet affixed to the cover

A phototransistor that detects light when the cover is
removed.

ADT7462

Rev. 0 | Page 61 of 92

POWER-UP SEQUENCE

The power-up sequence of the ADT7462 is as follows:

The temperature of the thermal diode connected to Pin 17
and Pin 18 (only dedicated thermal diode channel) is
monitored immediately on power-up of the ADT7462.
Ideally, the hottest zone should be connected to this channel
so protection is provided immediately on power-up.

CCP1

is also monitored immediately on power-up. V

CCP

is typically connected to a main power rail. The switching
on of the V

CCP

rail gates the fan's quiet start-up counter.

BATT

is monitored immediately on power-up before the

setup complete bit (Register 0x01, Bit 5) is set. The chassis
intrusion circuit (CI) is powered from V

BATT

. If the measured

BATT

reading is lower than the lower limit (default =

0x80), the CI circuit is turned off.

PWM1, PWM3, and PWM4 are not on dedicated pins.
Because these pins are shared with inputs, they are allowed
to float high on power-up. This means that if a fan is
connected to these pins, it spins at full speed on power-up.

PWM2 is switched off by default (because this is a
dedicated pin). If no SMBus communication takes place
within 4.6 seconds of the V

CCP

rail switching on, this PWM

drive is driven to full speed. If SMBus communication
does take place, this pin behaves as programmed.

No temperature or voltage (other than V

CCP1

and Diode 2

and V

BATT

) are monitored until the setup complete bit (Bit 5)

is set in Configuration Register 1 (0x01). This allows the
user to program the ADT7462 as required before
monitoring of all channels is enabled, thereby not
generating false ALERTs. The setup complete bit should
not be set until the device is fully configured for the
desired monitoring functions.

The following steps describe how to set up the ADT7462:

Power up the device.

Choose the best-suited easy configuration option for the
application, changing pin functions as required.

Program all appropriate limits for monitored inputs.
Program device parameters, fan control parameters, mask
bits, and anything else required for the application.

Set the complete bit. Do not set the complete bit until the
device is fully set up.

ADT7462

Rev. 0 | Page 63 of 92

Table 34. Register Map

Addr

Description

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

SW
Reset Lockable

0x00 Configuration

R/W SW

Reset

VID

#Byte #Byte #Byte

#Byte #Byte #Byte 0x20

Yes

0x01 Configuration

R/W RDY

Lock

DFS ALERT

Res Res Mon

0x81 Yes Yes

0x02 Configuration

R/W #FP

#FP

FMS VB2 VB1

PWM Res

Fast 0x40

Yes

0x03 Configuration

R/W Res

XOR

CI_R TT VID_T

SDA SCL GPIO 0x00 Yes Yes

0x07 TACH

Enable

R/W T8E

T7E

T6E T5E T4E

T3E T2E T1E 0x00 Yes Yes

0x08

TACH

Configuration R/W

Res

Res Res Res DC

4/8 DC

3/7

DC
2/6

DC
1/5

0xE0 Yes Yes

0x09

GPIO1_Bhvr

R/W

D4 P4 D3

P3 D2

P2 D1 P1 0x00 Yes Yes

0x0A

GPIO2_Bhvr

R/W

D8 P8 D7

P7 D6

P6 D5 P5 0x00 Yes Yes

0x0B T

MIN

_Cal1

R/W Res

Res

P2R2 P2R2 P1R2

P1R1 R2

0x00 Yes Yes

0x0C T

MIN

_Cal2

R/W Res

Ver

CYR2 CYR2 CYR2

CYR1 CYR1 CYR1 0x40 Yes

Yes

0x0D

THERM

Configuration

R/W

TW2

TW2 TW2 TW1 TW1

TW1 B2 B1 0x00 Yes Yes

0x0E

Conf_

THERM1

R/W Res

Res

Local T1TE 0x00

Yes

0x0F

Conf_

THERM2

R/W Res

Res

Local T2E

0x00

Yes

0x10

Pin Config 1

R/W

VID

Pin 1

Pin 2

Pin 3

Pin 4

Pin 7

0x7F

Yes

0x11

Pin Config 2

R/W

Pin 8

Pin 13

Pin 15

Pin 19

Pin 21

Pin 22

Pin 23

0xCE

Yes

0x12

Pin Config 3

R/W

Pin 24

Pin 25

Pin 26

Pin 27

Res

0x42

Yes

0x13

Pin Config 4

R/W

Pin 28

Pin 29

Pin 31

Pin 32

Res

0xFC

Yes

0x14 Easy

Config

R/W Res

Res

Res Op5 Op4

Op3 Op2 Op1 0x01 Yes Yes

0x16 EDO

Enable

R/W CS

CS CS

SC EDO2

EDO1

0x00 Yes Yes

0x18

Attenuators 1 En

R/W

Pin 22

Pin 21

Pin 19

Pin 15

Pin 13

Pin 8

Pin 7

Pin 5

0xFF

Yes

0x19

Attenuators 2 En

R/W

Res

Pin 29

Pin 28

Res

Pin 25

Pin 24

Pin 23

0x37

Yes

0x1A

Enhance

Acoustics

1 R/W

RR2

RR2 RR2 RR1 RR1

RR1 En2 En1 0x00 Yes Yes

0x1B

Enhance

Acoustics

2 R/W

RR4

RR4 RR4 RR3 RR3

RR3 En4 En3 0x00 Yes Yes

0x1C

Fan Free Wheel Test

R/W

Fan 8

Fan 7

Fan 6

Fan 5

Fan 4

Fan 3

Fan 2

Fan 1

0x00

Yes

0x1D Fans

Present

R/W F8P

F7P

F6P F5P F4P

F3P F2P F1P 0x00 Yes Yes

0x1E

Fan Free Wheel Test En

R/W

Fan 8

Fan 7

Fan 6

Fan 5

Fan 4

Fan 3

Fan 2

Fan 1

0x00

Yes

0x21 PWM1

Config

R/W Bhvr

Bhvr

Bhvr Inv Slow

Spin Spin Spin 0x11 Yes Yes

0x22 PWM2

Config

R/W Bhvr

Bhvr

Bhvr Inv Slow

Spin Spin Spin 0x31 Yes Yes

0x23 PWM3

Config

R/W Bhvr

Bhvr

Bhvr Inv Slow

Spin Spin Spin 0x51 Yes Yes

0x24 PWM4

Config

R/W Bhvr

Bhvr

Bhvr Inv Slow

Spin Spin Spin 0x71 Yes Yes

0x25

PWM1, PWM2 Freq

R/W

Min 2

Min 1

0x90

Yes

0x26

PWM3, PWM4 Freq

R/W

Min 4

Min 3

0x90

Yes

0x28

PWM1 Min

R/W

0x80

Yes

0x29

PWM2

Min

R/W

6 5 4 3

2 1 0 0x80

Yes

0x2A

PWM3

Min

R/W

6 5 4 3

2 1 0 0x80

Yes

0x2B

PWM4

Min

R/W

6 5 4 3

2 1 0 0x80

Yes

0x2C

PWM1 to PWM4 Max

R/W

0xC0

Yes

0x30

Thermal Mask 1

R/W

R3D

R2D

R1D

Local

Res

0x00

Yes

0x31

Thermal Mask 2

R/W

VRD2

VRD1

T2S T2A T2%

T1S T1A T1% 0xC0 Yes No

0x32

Voltage Mask 1

R/W

P23

+5V

P19

P15

+3.3V

+12V3 +12V2 +12V1 0x00

Yes

0x33

Voltage Mask 2

R/W

+1.5V1
(ICH)

+1.5V2
(3GIO)

P26 P25 P24

Res Res Res 0x00 Yes No

0x34

Fan Mask

R/W

Fan 8

Fan 7

Fan 6

Fan 5

Fan 4

Fan 3

Fan 2

Fan 1

0x00

Yes

0x35 Digital

Mask

R/W CI

VID

SCSI2 SCSI1

FAN2MAX

Res Res Res 0x38 Yes No

0x36

GPIO Mask

R/W

GPIO8

GPIO7 GPIO6 GPIO5 GPIO4

GPIO3 GPIO2 GPIO1 0x00

Yes

0x37

EDO Mask 1

R/W

Volt

Temp

Fan

Res GPIO4 GPIO3

GPIO2

GPIO1 0x00

Yes

0x38

EDO Mask 2

R/W

Volt

Temp

Fan

Res GPIO4 GPIO3

GPIO2

GPIO1 0x00

Yes

0x3D Device

5 4 3

2 1 0 0x62

No N/A

0x3E

Company

6 5 4 3

2 1 0 0x41

No N/A

0x3F

Revision

Number

6 5 4 3

2 1 0 0x04

No N/A

ADT7462

Rev. 0 | Page 64 of 92

Addr

Description

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

SW
Reset

Lockable

0x44 Local

Low

Temp Limit

R/W

6 5 4 3

2 1 0 0x40

No No

0x45

Remote 1/Pin +15V Low

R/W

0x40

0x46

Remote 2 Low limit

R/W

0x40

0x47 Remote

Pin 19 Low

R/W

6 5 4 3

2 1 0 0x40

No No

0x48

Local

High

R/W

6 5 4 3

2 1 0 0x95

No No

0x49 Remote1/

Pin15 High

R/W

6 5 4 3

2 1 0 0x95

No No

0x4A Remote

High Limit

R/W

6 5 4 3

2 1 0 0x95

No No

0x4B Remote

Pin 19 High

R/W

6 5 4 3

2 1 0 0x95

No No

0x4C

Local

THERM1

+1.5V2 (3GIO) High

R/W

6 5 4 3

2 1 0 0xA4

No Yes

0x4D Remote

THERM1

Limit

R/W

6 5 4 3

2 1 0 0xA4

No Yes

0x4E Remote

THERM1

Limit

R/W

6 5 4 3

2 1 0 0xA4

No Yes

0x4F Remote

THERM1

Limit

R/W

6 5 4 3

2 1 0 0xA4

No Yes

0x50

Local

THERM2

+1.5V1 (ICH) High

R/W

6 5 4 3

2 1 0 0xA4

No Yes

0x51

Remote 1

THERM2

Limit

R/W

6 5 4 3

2 1 0 0xA4

No Yes

0x52

Remote 2

THERM2

Limit

R/W

6 5 4 3

2 1 0 0xA4

No Yes

0x53

Remote 3

THERM2

Limit

R/W

6 5 4 3

2 1 0 0xA4

No Yes

0x54

Local/Remote1

Hyst R/W

LH LH LH R1H

R1H

0x44 No Yes

0x55 Remote

Remote 3 Hyst

R/W

RH2

RH2 RH2 RH2 RH3

RH3 RH3 RH3 0x44 No Yes

0x56

Local

Offset

R/W

6 5 4 3

2 1 0 0x00

No Yes

0x57

Remote

Offset

R/W

6 5 4 3

2 1 0 0x00

No Yes

0x58

Remote

Offset

R/W

6 5 4 3

2 1 0 0x00

No Yes

0x59

Remote

Offset

R/W

6 5 4 3

2 1 0 0x00

No Yes

0x5A Remote

Operating Point

R/W

6 5 4 3

2 1 0 0xA4

Yes

0x5B Remote

Operating Point

R/W

6 5 4 3

2 1 0 0xA4

Yes

0x5C Local

MIN

R/W

6 5 4 3

2 1 0 0x9A

No Yes

0x5D

Remote 1 T

MIN

R/W

6 5 4 3

2 1 0 0x9A

Yes

0x5E

Remote 2 T

MIN

R/W

6 5 4 3

2 1 0 0x9A

Yes

0x5F

Remote 3 T

MIN

R/W

6 5 4 3

2 1 0 0x9A

No Yes

0x60 Local

RANGE

/Hys

R/W Range

Range Range Range Hys

Hys

0xC4

Yes

0x61

Remote 1 T

RANGE

/Hys

R/W Range

Range Range Range Hys

Hys

0xC4

Yes

0x62

Remote 2 T

RANGE

/Hys

R/W Range

Range Range Range Hys

Hys

0xC4

Yes

0x63

Remote 3 T

RANGE

/Hys

R/W Range

Range Range Range Hys

Hys

0xC4

Yes

0x64

Operating

Point

Hyst R/W

Hys Hys Hys Hys Res

Res Res Res 0x40 Yes Yes

0x68

+3.3V

High

Limit

R/W

6 5 4 3

2 1 0 0xFF

No No

0x69

Pin 23 Voltage High Limit

R/W

0xFF

0x6A

Pin 24 Voltage High Limit

R/W

0xFF

0x6B

Pin 25 Voltage High Limit

R/W

0xFF

0x6C

Pin 26 Voltage High Limit

R/W

0xFF

0x6D

+12V1 Low Limit

R/W

0x00

0x6E

+12V2 Low Limit

R/W

0x00

0x6F

+12V3 Low Limit

R/W

0x00

0x70

+3.3V

Low

Limit

R/W

6 5 4 3

2 1 0 0x00

No No

0x71

+5V Low Limit

R/W

0x00

0x72

Pin 23 Voltage Low Limit

R/W

0x20

ADT7462

Rev. 0 | Page 65 of 92

Addr

Description

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

SW
Reset

Lockable

0x73

Pin 24 Voltage Low Limit

R/W

0x00

0x74

Pin 25 Voltage Low Limit

R/W

0x00

0x75

Pin 26 Voltage Low Limit

R/W

0x80

0x76

+1.5V1 (ICH) Low Limit

R/W

0x00

0x77

+1.5V2 (3GIO) Low Limit

R/W

0x00

0x78

TACH1

Limit/VID

R/W

6 5 4 3

2 1 0 0xFF

No Yes

0x79

TACH2

Limit

R/W

6 5 4 3

2 1 0 0xFF

No Yes

0x7A

TACH3

Limit

R/W

6 5 4 3

2 1 0 0xFF

No Yes

0x7B

TACH4

Limit

R/W

6 5 4 3

2 1 0 0xFF

Yes

0x7C TACH5/+12V1

High Limit

R/W

6 5 4 3

2 1 0 0xFF

No Yes

0x7D TACH6/+12V2

High Limit

R/W

6 5 4 3

2 1 0 0xFF

No Yes

0x7E TACH7/+5V

High Limit

R/W

6 5 4 3

2 1 0 0xFF

No Yes

0x7F TACH8/+12V3

High Limit

R/W

6 5 4 3

2 1 0 0xFF

No Yes

0x80

THERM1

Timer Limit

R/W

6 5 4 3

2 1 0 0xFF

No Yes

0x81

THERM2

Timer Limit

R/W

6 5 4 3

2 1 0 0xFF

No Yes

0x88 Local

Temp

Value, LSBs

6 5 4 3

2 1 0 0x00

No No

0x89 Local

Temp

Value, MSBs

6 5 4 3

2 1 0 0x00

No No

0x8A

Remote 1 Temp, LSBs

0x00

0x8B

Remote 1 Temp, MSBs,
Pin 15 Voltage

6 5 4 3

2 1 0 0x00

No No

0x8C Remote

Temp, LSBs

6 5 4 3

2 1 0 0x00

No No

0x8D Remote

Temp, MSBs

6 5 4 3

2 1 0 0x00

No No

0x8E Remote

Temp, LSBs

6 5 4 3

2 1 0 0x00

No No

0x8F

Remote 3 Temp, MSBs,
Pin 19 Voltage

6 5 4 3

2 1 0 0x00

No No

0x90

Pin 23 Voltage

0x00

0x91

Pin 24 Voltage

0x00

0x92

Pin 25 Voltage

0x00

0x93

Pin 26 Voltage

0x00

0x94

+1.5V1 (ICH) Voltage

0x00

0x95

+1.5V2 (3GIO) Voltage

0x00

0x96

+3.3V

Voltage

6 5 4 3

2 1 0 0x00

No No

0x97

VID

Value

6 5 4 3

2 1 0 0x00

No No

0x98

TACH1

Value,

LSBs R

6 5 4 3

2 1 0 0xFF

No No

0x99

TACH1 Value, MSBs

0xFF

0x9A

TACH2

Value,

LSBs R

6 5 4 3

2 1 0 0xFF

No No

0x9B

TACH2 Value, MSBs

0xFF

0x9C

TACH3

Value,

LSBs R

6 5 4 3

2 1 0 0xFF

No No

0x9D

TACH3 Value, MSBs

0xFF

0x9E

TACH4

Value,

LSBs R

6 5 4 3

2 1 0 0xFF

No No

0x9F

TACH4 Value, MSBs

0xFF

0xA0

Unused

6 5 4 3

2 1 0 N/A No No

0xA1

Unused

6 5 4 3

2 1 0 N/A No No

0xA2

TACH5

Value,

LSB R

6 5 4 3

2 1 0 0xFF

No No

0xA3 TACH5

MSB/+12V1

Voltage

6 5 4 3

2 1 0 0xFF

No No

0xA4

TACH6

Value,

LSB R

6 5 4 3

2 1 0 0xFF

No No

ADT7462

Rev. 0 | Page 66 of 92

Addr

Description

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

SW
Reset

Lockable

0xA5 TACH6

MSB/+12V2

Voltage

6 5 4 3

2 1 0 0xFF

No No

0xA6

TACH7

Value,

LSB R

6 5 4 3

2 1 0 0xFF

No No

0xA7 TACH7

MSB/+5V

Voltage

6 5 4 3

2 1 0 0xFF

No No

0xA8

TACH8

Value,

LSB R

6 5 4 3

2 1 0 0xFF

No No

0xA9 TACH8

MSB/+12V3

Voltage

6 5 4 3

2 1 0 0xFF

No No

0xAA

PWM1

Duty

Cycle R/W

6 5 4 3

2 1 0 0x00

No No

0xAB

PWM2

Duty

Cycle R/W

6 5 4 3

2 1 0 0x00

No No

0xAC

PWM3

Duty

Cycle R/W

6 5 4 3

2 1 0 0x00

No No

0xAD

PWM4

Duty

Cycle R/W

6 5 4 3

2 1 0 0x00

No No

0xAE

THERM1

% On-Time

6 5 4 3

2 1 0 0x00

No No

0xAF

THERM2

% On-Time

6 5 4 3

2 1 0 0x00

No No

0xB8

Thermal Status 1, Host

R3D

R2D

R1D

Local

Res

0x00

Yes

0xB9

Thermal Status 2, Host

VR2

VR1 T2S

T2A

T2% T1S

T1A

T1%

0x00

Yes No

0xBA

Thermal Status 3, Host

R3T2

R2T2

R1T2

LT2

R3T1

R2T1

R1T1

LT1

0x00

Yes

0xBB

Voltage Status 1, Host

Pin 23

+5V

Pin 19

Pin 15

+3.3V

+12V3

+12V2

+12V1

0x00

Yes

0xBC

Voltage Status 2, Host

+1.5V1
(ICH)

+1.5V2
(3GIO)

Pin 26

Pin 25

Pin 24

Res

0x00

Yes

0xBD

Fan Status, Host

Fan 8

Fan 7

Fan 6

Fan 5

Fan 4

Fan 3

Fan 2

Fan 1

0x00

Yes

0xBE

Digital Status, Host

VID

SCSI2

SCSI1

Fan 2 Max

Res

0x00

Yes

0xBF

GPIO Status, Host

R/W

GPIO8

GPIO7

GPIO6 GPIO5 GPIO4

GPIO3 GPIO2 GPIO1 0x00

Yes

0xC0

Thermal Status 1, BMC

R3D

R2D

R1D

Local

Res

0x00

Yes

0xC1

Thermal Status 2, BMC

VR2

VR1 T2S

T2A

T2% T1S

T1A

T1%

0x00

Yes No

0xC3

Voltage Status 1, BMC

Pin 23

Pin 19

Pin 15

+3.3V

+12V3

+12V2

+12V1

0x00

Yes

0xC4

Voltage Status 2, BMC

+1.5V1
(ICH)

+1.5V2
(3GIO)

Pin 26

Pin 25

Pin 24

Res

0x00

Yes

0xC5

Fan Status, BMC

Fan 8

Fan 7

Fan 6

Fan 5

Fan 4

Fan 3

Fan 2

Fan 1

0x00

Yes

0xC6

Digital Status, BMC

VID

SCSI2

SCSI1

Fan 2 Max

Res

0x0

Yes

ADT7462

Rev. 0 | Page 67 of 92

Table 35. Register 0x00 Configuration Register 0

Bit Name

R/W Description

[5:0]

#Bytes Block Read

R/W

These bits set the number of registers to be read in a Block Read. Default = 0x20.

VID Decoder

R/W

0 = VR10 Decoding Spec; 1 = VR11 Decoding Spec. Default = 0.

7 SW

Reset

R/W

Setting this bit to 1 restores all unlocked registers to their default values. Self clearing.
Write 0x6D to register 0x7B before setting this bit to get a software reset. Default = 0.

POR = 0x20, Lock = Y, SW Reset = Y.

Table 36. Register 0x01 Configuration Register 1

Bit Name

R/W Description

0 Monitor

R/W

Setting this bit to 1 enables temperature and voltage measurements. When this bit is set to 0,
temperature and voltage measurements are disabled. Default = 1.

Reserved

R/W

Reserved. Default = 0.

Reserved

R/W

Reserved. Default = 0.

ALERT Mode

R/W

This bit sets the ALERT mode in the ADT7462. 1 = comparator mode, 0 SMBALERT mode (default).

Fast Spin-Up

Disable

R/W

Setting this bit to 1 disables the fast spin-up (for 2 TACH pulses) for the fan. Instead, the fans spin up
for the programmed fan start-up timeout. Default = 0.

5 Setup

Complete R/W

Setting this bit to 1 tells the ADT7462 that setup is complete and that monitoring of all selected
channels should begin. Default = 0.

6 Lock

Write
Once

Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers become
read only and cannot be modified until the ADT7462 is powered down and powered up again. This
prevents rogue programs, such as viruses, from modifying critical system limit settings. Lockable.

RDY

This bit is set to 1 to indicate that the ADT7462 is fully powered up and ready to start monitoring.

POR = 0x81, Lock = Y, SW Reset = Y.

Table 37. Register 0x02 Configuration Register 2

Bit Name

R/W Description

0 Fast

R/W

In low frequency, PWM fan speed measurements are made once a second. Setting this bit to 1
increases the frequency of the fan speed measurements to 4 times a second. Default = 0.

Reserved

R/W

Reserved. Default = 0.

2 PWM

Mode

R/W

This bit sets the PWM frequency mode. 0 = low frequency PWM; frequency programmable
between 11 Hz and 88.2 Hz. Default = 35.3 Hz. 1 = high frequency mode, 22.5 kHz.

3 VRD1

Boost

R/W

Setting this bit to 0 causes the fans to go to full speed on assertion of VRD1. Default = 0.
When this bit is set to 1, VRD1 assertions have no effect on the fan speed.

4 VRD2

Boost

R/W

Setting this bit to 0 causes the fans to go to full speed on assertion of VRD2. Default = 0.
When this bit is set to 1, VRD2 assertions have no effect on the fan speed.

Fans Full Speed

R/W

Setting this bit to 1 drives the fans to full speed. Default = 0.

[7:6] #TACH

Pulses

R/W In low frequency mode, the ADT7462 must pulse stretch to get an accurate fan speed measurement.

The speed is always measured between the 2nd rising edge and one × TACH pulses later. This bit
determines the last TACH pulse. Therefore, if the fan speed is to be measured between the second and
fourth TACH pulse, 01 is written to these bits.

x = 1 = 00

x = 2 = 01 (default)

x = 3 = 10

x = 4 = 11

POR = 0x40, Lock = Y, SW Reset = Y.

ADT7462

Rev. 0 | Page 68 of 92

Table 38. Register 0x03 Configuration Register 3

Bit Name

R/W Description

GPIO_En

R/W

Setting this bit to 1 enables the GPIOs. Default = 0.

SCL_Timeout

R/W

1 = SCL Timeout Enabled. 0 = SCL timeout disabled = default.

SDA_Timeout

R/W

1 = SDA Timeout Enabled. 0 = SDA timeout disabled = default.

3 VID_Threshold

R/W

This bit sets the digital threshold for the VID's digital inputs. 0 =default. 1 = low thresholds
selected = 0.65 V.

THERM
_Threshold

R/W

This bit sets the digital threshold for the THERM's digital inputs. 0 =default. 1 = low thresholds
selected = 2/3 V

CCP1

(Pin 23).

CI Reset

R/W

Setting this bit to 1 resets the chassis intrusion circuit. This bit clears itself. Default = 0.

XOR Tree

R/W

Setting this bit to 1 enables the XOR tree test. Default = 0.

V_Core_Low

R/W

Setting this bit to 1 enables V_core_low. Default = 0.

POR = 0x00, Lock = Y, SW Reset = Y.

Table 39. Register 0x07 TACH Enable Register

Bit Name

R/W Description

TACH1

R/W

Setting this bit to 1 enables the TACH1 measurement. Default = 0.

TACH2

R/W

Setting this bit to 1 enables the TACH2 measurement. Default = 0.

TACH3

R/W

Setting this bit to 1 enables the TACH3 measurement. Default = 0.

TACH4

R/W

Setting this bit to 1 enables the TACH4 measurement. Default = 0.

TACH5

R/W

Setting this bit to 1 enables the TACH5 measurement. Default = 0.

TACH6

R/W

Setting this bit to 1 enables the TACH6 measurement. Default = 0.

TACH7

R/W

Setting this bit to 1 enables the TACH7 measurement. Default = 0.

TACH8

R/W

Setting this bit to 1 enables the TACH8 measurement. Default = 0.

POR = 0x00, Lock = Y, SW Reset = Y.

Table 40. Register 0x08 TACH Configuration Register

Bit Name R/W

Description

0 DC1/5 R/W

Setting this bit to 1 enables continuous measurements on TACH1 and TACH5 in low frequency PWM mode.
Default = 0.

1 DC2/6 R/W

Setting this bit to 1 enables continuous measurements on TACH2 and TACH6 in low frequency PWM mode.
Default = 0.

2 DC3/7 R/W

Setting this bit to 1 enables continuous measurements on TACH3 and TACH7 in low frequency PWM mode.
Default = 0.

3 DC4/8 R/W

Setting this bit to 1 enables continuous measurements on TACH4 and TACH8 in low frequency PWM mode.
Default = 0.

[4:7]

RES

Reserved for future use.

POR = 0xE0, Lock = Y, SW Reset = Y.

Table 41. Register 0x09 GPIO Configuration Register 1

Bit Name

R/W Description

GPIO1_P

R/W

This bit sets the polarity of GPIO1. 0 = default = active low. 1= active high.

GPIO1_D

R/W

This bit sets the direction of GPIO1. 0 = default = input. 1= output.

GPIO2_P

R/W

This bit sets the polarity of GPIO2. 0 = default = active low. 1= active high.

GPIO2_D

R/W

This bit sets the direction of GPIO2. 0 = default = input. 1= output.

GPIO3_P

R/W

This bit sets the polarity of GPIO3. 0 = default = active low. 1= active high.

GPIO3_D

R/W

This bit sets the direction of GPIO3. 0 = default = input. 1= output.

GPIO4_P

R/W

This bit sets the polarity of GPIO4. 0 = default = active low. 1= active high.

GPIO4_D

R/W

This bit sets the direction of GPIO4. 0 = default = input. 1= output.

POR = 0x00, Lock = Y, SW Reset = Y.

ADT7462

Rev. 0 | Page 69 of 92

Table 42. Register 0x0A GPIO Configuration Register 2

Bit Name

R/W Description

GPIO5_P

R/W

This bit sets the polarity of GPIO5. 0 = default = active low. 1= active high.

GPIO5_D

R/W

This bits sets the direction of GPIO5. 0 = default = input. 1= output.

GPIO6_P

R/W

This bit sets the polarity of GPIO6. 0 = default = active low. 1= active high.

GPIO6_D

R/W

This bits sets the direction of GPIO6. 0 = default = input. 1= output.

GPIO7_P

R/W

This bit sets the polarity of GPIO7. 0 = default = active low. 1= active high.

GPIO7_D

R/W

This bits sets the direction of GPIO7. 0 = default = input. 1= output.

GPIO8_P

R/W

This bit sets the polarity of GPIO8. 0 = default = active low. 1= active high.

GPIO8_D

R/W

This bits sets the direction of GPIO8. 0 = default = input. 1= output.

POR = 0x00, Lock = Y, SW Reset = Y.

Table 43. Register 0x0B Dynamic T

MIN

Control Register 1

Bit Name

R/W Description

Remote 1 En

R/W

Setting this bit to 1 enables dynamic T

MIN

control for the Remote 1 channel. Default = 0.

Remote 2 En

R/W

Setting this bit to 1 enables dynamic T

MIN

control for the Remote 2 channel. Default = 0.

2 PH1_TR1 R/W

PH1_TR1 = 1 copies the Remote 1 current temperature to the Remote 1 operating point register
if THERM1 gets asserted externally. This happens only if the current temperature is less than the
value in the operating point register. The operating point contains the temperature at which THERM1
is asserted. PH1_TR1 = 0 (default) ignores any THERM1 assertions on the THERM1 pin. The Remote 1
operating point register reflects its programmed value.

3 PH1_TR2 R/W

PH1_RT2 = 1 copies the Remote 2 current temperature to the Remote 2 operating point register
if THERM1 gets asserted externally. This happens only if the current temperature is less than the value
in the operating point register. The operating point contains the temperature at which THERM1
is asserted. PH1_TR1 = 0 (default) ignores any THERM1 assertions on the THERM1 pin. The Remote 2
Operating Point Register reflects its programmed value.

4 PH2_TR1 R/W

PH2_TR1 = 1 copies the Remote 1 current temperature to the Remote 1 operating point register if
THERM2 gets asserted externally. This happens only if the current temperature is less than the value in
the operating point register. The operating point contains the temperature at which THERM2 is asserted.
PH2_TR1 = 0 (default) ignores any THERM2 assertions on the THERM2 pin. The Remote 1 operating point
register reflects its programmed value.

5 PH2_RT2 R/W

PH2_RT2 = 1 copies the Remote 2 current temperature to the Remote 2 operating point register if
THERM2 gets asserted externally. This happens only if the current temperature is less than the value in
the operating point register. The operating point contains the temperature at which THERM2 is asserted.
PH2_RT2 = 0 (default) ignores any THERM2 assertions on the THERM2 pin. The Remote 2 operating point
register reflects its programmed value.

[7:6]

Reserved

R/W

Reserved for future use.

POR = 0x00, Lock = Y, SW Reset = Y.

ADT7462

Rev. 0 | Page 70 of 92

Table 44. Register 0x0C Dynamic T

MIN

Control Register 2

Bit Name

R/W

Description

[2:0] CYR1

R/W

Three-bit Remote 1 cycle value. These three bits define the delay time between making subsequent T

MIN

adjustments in the control loop for the Remote 1 temperature channel, in terms of number of monitoring
cycles. The system has associated thermal time constants that need to be found to optimize the response
of fans and the control loop.

Bits

Decrease cycle

Increase cycle

000

8 cycles (1 sec)

16 cycles (2 sec)

001

16 cycles (2 sec)

32 cycles (4 sec)

010

32 cycles (4 sec)

64 cycles (8 sec)

011

64 cycles (8 sec)

128 cycles (16 sec)

100

128 cycles (16 sec)

256 cycles (32 sec)

101

256 cycles (32 sec)

512 cycles (64 sec)

110

512 cycles (64 sec)

1024 cycles (128 sec)

111

1024 cycles (128 sec)

2048 cycles (256 sec)

[5:3] CYR2

R/W

Three-bit Remote 2 cycle value. These three bits define the delay time between making subsequent T

MIN

adjustments in the control loop for the Remote 2 temperature channel, in terms of number of monitoring
cycles. The system has associated thermal time constants that need to be found to optimize the response
of fans and the control loop.

Bits

Decrease cycle

Increase Cycle

000

8 cycles (1 sec)

16 cycles (2 sec)

001

16 cycles (2 sec)

32 cycles (4 sec)

010

32 cycles (4 sec)

64 cycles (8 sec)

011

64 cycles (8 sec)

128 cycles (32 sec)

100

128 cycles (16 sec)

256 cycles (32 sec)

101

256 cycles (32 sec)

1024 cycles (128 sec)

110

512 cycles (64 sec)

1024 cycles (128 sec)

111

1024 cycles (128 sec)

2048 cycles (256 sec)

Control
Loop Select

R/W

This bit allows the user to select between two control loops. 0 makes the control loop backwards-compatible
with ADT7463 and ADT7468. 1 = ADT7462 control loop (default).

Reserved

Reserved for future use.

POR = 0x40, Lock = Y, SW Reset = Y.

ADT7462

Rev. 0 | Page 71 of 92

Table 45. Register 0x0D THERM Configuration Register

Bit Name

R/W

Description

0 Boost

R/W

Setting this bit to 0 causes the fans to go to full speed on assertion of THERM1 as an output. Setting
this bit to 1 means that the fan speed is not affected when the THERM1 temperature limit is exceeded.
Default = 0.

1 Boost

R/W

Setting this bit to 0 causes the fans to go to full speed on assertion of THERM2 as an output. Setting
this bit to 1 means that the fan speed is not affected when the THERM2 temperature limit is exceeded.
Default = 0.

[4:2]

THERM1 Timer
Window

R/W

These bits set the timer window for measuring THERM1 assertions.

000 = 0.25 sec

001 = 0.5 sec

010 = 1 sec

011 = 2 sec

100 = 4 sec

101 = 8 sec

110 = 8 sec

111 = 8 sec

[7:5]

THERM2 Timer
Window

R/W

These bits set the timer window for measuring THERM2 assertions.

000 = 0.25 sec

001 = 0.5 sec

010 = 1 sec

011 = 2 sec

100 = 4 sec

101 = 8 sec

110 = 8 sec

111 = 8 sec

POR = 0x00, Lock = Y, SW Reset = Y.

Table 46. Register 0x0E THERM1 Configuration Register

Bit Name

R/W

Description

Enable THERM1 Timer

R/W

Enables the THERM1 timer circuit. Default = 0.

THERM1_Local

R/W

Setting the bit to 1 means that the THERM1 pin is asserted low as an output whenever
the local temperature exceeds the Local THERM1 temperature limit. Default = 0.

THERM1_Remote 1

R/W

Setting the bit to 1 means that the THERM1 pin is asserted low as an output whenever
the Remote 1 temperature exceeds the Remote 1 THERM1 temperature Limit. Default = 0.

THERM1_Remote 2

R/W

Setting the bit to 1 means that the THERM1 pin is asserted low as an output whenever
the Remote 2 temperature exceeds the Remote 2 THERM1 temperature Limit. Default = 0.

THERM1_Remote 3

R/W

Setting the bit to 1 means that the THERM1 pin is asserted low as an output whenever
the Remote 3 temperature exceeds the Remote 3 THERM1 temperature limit. Default = 0.

[7:5]

Reserved

Reserved for future use.

POR = 0x00, Lock = Y, SW Reset = Y.

ADT7462

Rev. 0 | Page 72 of 92

Table 47. Register 0x0F THERM2 Configuration Register

Bit Name

R/W

Description

Enable THERM2 Timer

R/W

Enables the THERM2 timer circuit. Default = 0

THERM2_Local

R/W

Setting the bit to 1 means that the THERM2 pin is asserted low as an output whenever
the local temperature exceeds the local THERM2 temperature limit. Default = 0.

THERM2_Remote 1

R/W

Setting the bit to 1 means that the THERM2 pin is asserted low as an output whenever
the Remote 1 temperature exceeds the Remote 1 THERM2 temperature limit. Default = 0.

THERM2_Remote 2

R/W

Setting the bit to 1 means that the THERM2 pin is asserted low as an output whenever
the Remote 2 temperature exceeds the Remote 2 THERM2 temperature limit. Default = 0.

THERM2_Remote 3

R/W

Setting the bit to 1 means that the THERM2 pin is asserted low as an output whenever
the Remote 3 temperature exceeds the Remote 3 THERM2 temperature limit. Default = 0.

[7:5]

Reserved

Reserved for future use.

POR = 0x00, Lock = Y, SW Reset = Y.

Table 48. Register 0x10 Pin Configuration Register 1

Bit Name

R/W

Description

Pin 7

R/W

0 = +12V1, 1 = TACH5 input. Default =1.

Pin 4

R/W

0 = GPIO4; 1= TACH4 input (that is if the VIDs are not selected). Default = 1.

Pin 3

R/W

0 = GPIO3; 1= TACH3 input (that is if the VIDs are not selected). Default = 1.

Pin 2

R/W

0 = GPIO2; 1= TACH2 input (that is if the VIDs are not selected). Default = 1.

Pin 1

R/W

0 = GPIO1; 1= TACH1 input (that is if the VIDs are not selected). Default = 1.

5 Diode

R/W

1 enables the D3+ and D3- inputs on Pin 19 and Pin 20. 0 enables the voltage measurement
input and SCSI_Term input. Default = 1.

6 Diode

R/W

1 enables the D1+ and D1- inputs on Pin 15 and Pin 16. 0 enables the voltage measurement
input and SCSI_Term input. Default = 1.

VIDs

R/W

Setting this bit to 1 enables the VIDs on Pin 1 to Pin 4, Pin 28, Pin 31, and Pin 32. Default = 0.

POR = 0x7F, Lock = Y, SW Reset = Y.

Table 49. Register 0x11 Pin Configuration Register 2

Bit Name

R/W

Description

[1:0]

Pin 23

R/W

00 = V

CCP1

selected.

01 = +2.5V.

10 = +1.8V (default).

11 = +1.5V.

Pin 22

R/W

0 = +12V3; 1 = TACH8. Default = 1.

Pin 21

R/W

0 = +5V; 1 = TACH7. Default = 1.

Pin 19

R/W

0 = 1.25V; 1 = +0.9V (that is, if RT3 is not selected). Default = 0.

Pin 15

R/W

0 = +2.5V, 1 = +1.8V (that is, if RT1 is not selected) . Default = 0.

Pin 13

R/W

0 = +3.3V; 1 = PWM4. Default = 1.

Pin 8

R/W

0 = +12V2; 1 = TACH6. Default = 1.

POR = 0xCE, Lock = Y, SW Reset = Y.

ADT7462

Rev. 0 | Page 73 of 92

Table 50. Register 0x12 Pin Configuration Register 3

Bit Name

R/W

Description

Res

Reserved for future use

1 Pin

R/W

0 = FAN2MAX; 1 = chassis intrusion (default)

[3:2]

Pin 26

R/W

00 = V

BATT

selected (default)

01 = +1.2V2 (FSB_V

)

10 = VR_Hot 2

11 = VR_Hot 2

[5:4]

Pin 25

R/W

00 = +3.3V selected (default)

01 = +1.2V1 (G

BIT

)

10 = VR_Hot 1

11 = VR_Hot 1

[7:6]

Pin 24

R/W

00 = V

CCP2

selected

01 = +2.5V (default)

10 = +1.8V

11 = +1.5V

POR = 0x42, Lock = Y, SW Reset = Y.

Table 51. Register 0x13 Pin Configuration Register 4

Bit Name

R/W

Description

[1:0] RES

Reserved.

Pin 32

R/W

0 = GPIO6; 1 = PWM2 (Pin 32 is VID 5 if VIDs are selected). Default = 1.

Pin 31

R/W

0 = GPIO5; 1 = PWM1 (Pin 31 is VID4 if VIDs are selected). Default = 1.

[5:4]

Pin 29
(Pin 28, +1.5V Monitoring

)

R/W

00 = GPIO8.
01 = +1.5V (measured on Pin 28).

10 = THERM2.

11 = THERM2 (default).

(Pin 29 is VID6 if VIDs are selected.)

[7:6] Pin

(Pin 29, +1.5V monitoring

)

R/W

00 = GPIO7.
01 = +1.5V (measured on Pin 29).

10 = THERM1.

11 = THERM1 (default).

POR = 0xFC, Lock = Y, SW Reset = Y.

+1.5V can be monitored on Pin 28 and Pin 29 only when both are configured as +1.5V inputs. This means that +1.5V is measured on both pins or on neither.

+1.5V monitoring cannot be combined with another function on the other pin. For example, if Pin 29 is configured as +1.5V, then THERM1 cannot be selected on
Pin 28, because they share the same selection bits.

Table 52. Register 0x14 Easy Configuration Options

Bit Name

R/W

Description

Easy Option 1 Select

R/W

Setting this bit to 1 enables Easy Option 1.

Easy Option 2 Select

R/W

Setting this bit to 1 enables Easy Option 2.

Easy Option 3 Select

R/W

Setting this bit to 1 enables Easy Option 3.

Easy Option 4 Select

R/W

Setting this bit to 1 enables Easy Option 4.

Easy Option 5 Select

R/W

Setting this bit to 1 enables Easy Option 5.

[7:5]

Reserved

Reserved for future use.

POR = 0x01, Lock = Y, SW Reset = Y.

ADT7462

Rev. 0 | Page 74 of 92

Table 53. Register 0x16 EDO/Single-Channel Enable

Bit Name

R/W

Description

EDO_En1

R/W

Enable EDO on GPIO5. Default = 0.

EDO_En2

R/W

Enable EDO on GPIO6. Default = 0.

Single-Channel
Mode Select

R/W

Setting this bit to 1 places the ADT7462 in single-channel mode. This means that it converts on
one channel only. The channel it converts on is set using the channel select bits in this register.
Default = 0.

[7:3]

Channel Select

R/W

These bits are used to set the single channel that the ADT7462 measures in single-channel mode.

0000 0 = Pin 26 (default)

0000 1 = Remote 1 temperature

0001 0 = Remote 2 temperature

0001 1 = Remote 3 temperature

00100 = local temperature

0010 1 = +12V1

0011 0 = +12V2

0011 1 = +12V3

0100 0 = +3.3V

0100 1 = Pin 15 voltage

0101 0 = Pin 19 voltage

0101 1 = +5V

0110 0 = Pin 23 voltage

0110 1 = Pin 24 voltage

0111 0 = Pin 25 voltage

1000 0 = +1.5V2 (ICH) voltage

1000 1 = +1.5V1 (3GIO) voltage

POR = 0x00, Lock = Y, SW Reset = Y.

Table 54. Register 0x18 Voltage Attenuator Configuration 1

Bit Name

R/W

Description

Res

Reserved for future use.

Attenuator Pin 7

R/W

Setting this bit to 0 removes the attenuators for Pin 7. Default = 1 = attenuators enabled.

Attenuator Pin 8

R/W

Setting this bit to 0 removes the attenuators for Pin 8. Default = 1 = attenuators enabled.

Attenuator Pin 13

R/W

Setting this bit to 0 removes the attenuators for Pin13. Default = 1 = attenuators enabled.

Attenuator Pin 15

R/W

Setting this bit to 0 removes the attenuators for Pin 15. Default = 1 = attenuators enabled.

Attenuator Pin 19

R/W

Setting this bit to 0 removes the attenuators for Pin 19. Default = 1 = attenuators enabled.

Attenuator Pin 21

R/W

Setting this bit to 0 removes the attenuators for Pin 21. Default = 1 = attenuators enabled.

Attenuator Pin 22

R/W

Setting this bit to 0 removes the attenuators for Pin 22. Default = 1 = attenuators enabled.

POR = 0xFF, Lock = Y, SW Reset = Y.

Table 55. Register 0x19 Voltage Attenuator Configuration 2

Bit Name

R/W

Description

Attenuator Pin 23

R/W

Setting this bit to 0 removes the attenuators for Pin 23. Default = 1 = attenuators enabled.

Attenuator Pin 24

R/W

Setting this bit to 0 removes the attenuators for Pin 24. Default = 1 = attenuators enabled.

Attenuator Pin 25

R/W

Setting this bit to 0 removes the attenuators for Pin 25. Default = 1 = attenuators enabled.

Unused

R/W

Default = 0.

Attenuator Pin 28

R/W

Setting this bit to 0 removes the attenuators for Pin 28. Default = 1 = attenuators enabled.

Attenuator Pin 29

R/W

Setting this bit to 0 removes the attenuators for Pin 29. Default = 1 = attenuators enabled.

[7:6]

Reserved

R/W

Reserved for future use. Default = 00.

POR = 0x37, Lock = Y, SW Reset = Y.

ADT7462

Rev. 0 | Page 75 of 92

Table 56. Register 0x1A Enhance Acoustics Register 1

Bit Name

R/W

Description

EA1_En

R/W

Setting this bit to 1 enables the enhance acoustics mode for PWM1; 0 disables it. Default = 0.

EA2_En

R/W

Setting this bit to 1 enables the enhance acoustics mode for PWM2; 0 disables it. Default = 0.

[4:2]

Ramp Rate 1

R/W

These bits set the ramp rate for the enhance acoustics mode for PWM1. Default = 000.

Time Slot Increase

Time for 33% to 100%

000 = 1

35 sec

001 = 2

17.6 sec

010 = 3

11.8 sec

011 = 5

7 sec

100 = 8

4.4 sec

101 = 12

3 sec

110 = 24

1.6 sec

111 = 48

0.8 sec

[7:5]

Ramp Rate 2

R/W

These bits set the ramp rate for the enhance acoustics mode for PWM2. Default = 000.

Time Slot Increase

Time for 33% to 100%

000 = 1

35 sec

001 = 2

17.6 sec

010 = 3

11.8 sec

011 = 5

7 sec

100 = 8

4.4 sec

101 = 12

3 sec

110 = 24

1.6 sec

111 = 48

0.8 sec

POR = 0x00, Lock = Y, SW Reset = Y.

Table 57. Register 0x1B Enhance Acoustics Register 2

Bit Name

R/W

Description

EA3_En

R/W

Setting this bit to 1 enables the enhance acoustics mode for PWM3; 0 disables it. Default = 0.

EA4_En

R/W

Setting this bit to 1 enables the enhance acoustics mode for PWM4; 0 disables it. Default = 0.

[4:2]

Ramp Rate 3

R/W

These bits set the ramp rate for the enhance acoustics mode for PWM3. Default = 000.

Time Slot Increase

Time for 33% to 100%

000 = 1

35 sec

001 = 2

17.6 sec

010 = 3

11.8 sec

011 = 5

7 sec

100 = 8

4.4 sec

101 = 12

3 sec

110 = 24

1.6 sec

111 = 48

0.8 sec

[7:5]

Ramp Rate 4

R/W

These bits set the ramp rate for the enhance acoustics mode for PWM4. Default = 000.

Time Slot Increase

Time for 33% to 100%

000 = 1

35 sec

001 = 2

17.6 sec

010 = 3

11.8 sec

011 = 5

7 sec

100 = 8

4.4 sec

101 = 12

3 sec

110 = 24

1.6 sec

111 = 48

0.8 sec

POR = 0x00, Lock = Y, SW Reset = Y.

ADT7462

Rev. 0 | Page 76 of 92

Table 58. Register 0x1C Fan Freewheeling Test

Bit Name

R/W

Description

Test Fan 1

R/W

Fan freewheeling test bit for Fan 1. This bit self clears once the test is complete.

Test Fan 2

R/W

Fan freewheeling test bit for Fan 2. This bit self clears once the test is complete.

Test Fan 3

R/W

Fan freewheeling test bit for Fan 3. This bit self clears once the test is complete.

Test Fan 4

R/W

Fan freewheeling test bit for Fan 4. This bit self clears once the test is complete.

Test Fan 5

R/W

Fan freewheeling test bit for Fan 5. This bit self clears once the test is complete.

Test Fan 6

R/W

Fan freewheeling test bit for Fan 6. This bit self clears once the test is complete.

Test Fan 7

R/W

Fan freewheeling test bit for Fan 7. This bit self clears once the test is complete.

Test Fan 8

R/W

Fan freewheeling test bit for Fan 8. This bit self clears once the test is complete.

POR = 0x00, Lock = Y, SW Reset = Y.

Table 59. Register 0x1D Fans Present

Bit Name

R/W

Description

Fan 1 Present

R/W

Set this bit to 1 when Fan 1 is present.

Fan 2 Present

R/W

Set this bit to 1 when Fan 2 is present.

Fan 3 Present

R/W

Set this bit to 1 when Fan 3 is present.

Fan 4 Present

R/W

Set this bit to 1 when Fan 4 is present.

Fan 5 Present

R/W

Set this bit to 1 when Fan 5 is present.

Fan 6 Present

R/W

Set this bit to 1 when Fan 6 is present.

Fan 7 Present

R/W

Set this bit to 1 when Fan 7 is present.

Fan 8 Present

R/W

Set this bit to 1 when Fan 8 is present.

POR = 0x00, Lock = Y, SW Reset = Y.

Table 60. Register 0x1E Fan Freewheeling Test Enable

Bit Name

R/W

Description

Test Fan 1

R/W

Setting this bit to 1 enables the fan freewheeling test for Fan 1.

Test Fan 2

R/W

Setting this bit to 1 enables the fan freewheeling test for Fan 2.

Test Fan 3

R/W

Setting this bit to 1 enables the fan freewheeling test for Fan 3.

Test Fan 4

R/W

Setting this bit to 1 enables the fan freewheeling test for Fan 4.

Test Fan 5

R/W

Setting this bit to 1 enables the fan freewheeling test for Fan 5.

Test Fan 6

R/W

Setting this bit to 1 enables the fan freewheeling test for Fan 6.

Test Fan 7

R/W

Setting this bit to 1 enables the fan freewheeling test for Fan 7.

Test Fan 8

R/W

Setting this bit to 1 enables the fan freewheeling test for Fan 8.

POR = 0x00, Lock = Y, SW Reset = Y.

ADT7462

Rev. 0 | Page 77 of 92

Table 61. PWM Configuration Registers

Description

Power On
Default

0x21

R/W

PWM1 Configuration Register

0x11

0x22

R/W

PWM2 Configuration Register

0x31

0x23

R/W

PWM3 Configuration Register

0x51

0x24

R/W

PWM4 Configuration Register

0x71

Bit Name

R/W

Description

[2:0] Spin-Up

Timeout

R/W

These bits set the duration of the fan start-up timeout and the
timeout for the fan freewheeling test.

000 = no start-up timeout

001 = 100 ms

010 = 250 ms

011 = 400 ms

100 = 667 ms

101 = 1 sec

110 = 2 sec

111 = 32 sec

3 SLOW

R/W

Setting this bit to 1 makes the ramp rate of the enhance
acoustics mode 4 times longer.

INV

R/W

Setting this bit to 0, the PWM outputs are active high
Setting this bit to 1, the PWM outputs are active low.

[7:5] BHVR

R/W

These bits determine which temperature channel controls the
fans in the automatic fan speed control loop.

000 = local temperature

001 = Remote 1 temperature

010 = Remote 2 temperature

011 = Remote 3 temperature

100 = off

101 = maximum fan speed calculated by the local and Remote 3
temperature channels.

110 = maximum fan speed calculated by all 4 channels.

111 = manual mode.

Lock = Y, SW Reset = Y.

ADT7462

Rev. 0 | Page 78 of 92

Table 62. Register 0x25 PWM1, PWM2 Frequency

Bit Name R/W

Description

0 Min

1 R/W

When the ADT7462 is in automatic fan control mode, this bit defines whether PWM1 is off (0% duty cycle) or
at minimum PWM1 duty cycle when the controlling temperature is below its T

MIN

- hysteresis value.

0 = 0% duty cycle below T

MIN

- hysteresis (default); 1 = minimum PWM1 duty cycle below T

MIN

- hysteresis.

1 Min

2 R/W

When the ADT7462 is in automatic fan control mode, this bit defines whether PWM2 is off (0% duty cycle) or
at minimum PWM2 duty cycle when the controlling temperature is below its T

MIN

- hysteresis value.

0 = 0% duty cycle below T

MIN

- hysteresis (default); 1 = minimum PWM2 duty cycle below T

MIN

- hysteresis.

[4:2]

Low Freq 1

R/W

These bits set the frequency of PWM1 when configured in low frequency mode.

000 = 11 Hz

001 = 14.7 Hz

010 = 22.1 Hz

011 = 29.4 Hz

100 = 35.3 Hz (default)

101 = 44.1 Hz

110 = 58.8 Hz

111 = 88.2 Hz

[7:5]

Low Freq 2

R/W

These bits set the frequency of PWM2 when configured in low frequency mode.

000 = 11 Hz

001 = 14.7 Hz

010 = 22.1 Hz

011 = 29.4 Hz

100 = 35.3 Hz (default)

101 = 44.1 Hz

110 = 58.8 Hz

111 = 88.2 Hz

POR = 0x90, Lock = Y, SW Reset = Y.

Table 63. Register 0x26 PWM3, PWM4 Frequency

Bit Name R/W

Description

0 Min

3 R/W

When the ADT7462 is in automatic fan control mode, this bit defines whether PWM3 is off (0% duty cycle) or
at minimum PWM3 duty cycle when the controlling temperature is below its T

MIN

- hysteresis value.

0 = 0% duty cycle below T

MIN

- hysteresis (default); 1 = minimum PWM3 duty cycle below T

MIN

- hysteresis.

1 Min

4 R/W

When the ADT7462 is in automatic fan control mode, this bit defines whether PWM4 is off (0% duty cycle)
or at minimum PWM4 duty cycle when the controlling temperature is below its T

MIN

- hysteresis value.

0 = 0% duty cycle below T

MIN

- hysteresis (default); 1 = minimum PWM4 duty cycle below T

MIN

- hysteresis.

[4:2]

Low Freq 3

R/W

These bits set the frequency of PWM3 when configured in low frequency mode 000 = 11 Hz.

001 = 14.7 Hz

010 = 22.1 Hz

011 = 29.4 Hz

100 = 35.3 Hz (default)

101 = 44.1 Hz

110 = 58.8 Hz

111 = 88.2 Hz

[7:5]

Low Freq 4

R/W

These bits set the frequency of PWM4 when configured in low frequency mode.

000 = 11 Hz

001 = 14.7 Hz

010 = 22.1 Hz

011 = 29.4 Hz

100 = 35.3 Hz (default)

101 = 44.1 Hz

110 = 58.8 Hz

111 = 88.2 Hz

POR = 0x90, Lock = Y, SW Reset = Y.

ADT7462

Rev. 0 | Page 79 of 92

Table 64. Minimum PWMx Duty Cycle

Register Address

R/W

Description

POR Default

0x28

R/W

Minimum PWM1 duty cycle

0x80

0x29

R/W

Minimum PWM2 duty cycle

0x80

0x2A

R/W

Minimum PWM3 duty cycle

0x80

0x2B

R/W

Minimum PWM4 duty cycle

0x80

Lock = Y, SW Reset = Y.

Table 65. Register 0x2C Maximum PWM Duty Cycle

Bit Name

R/W Description

[7:0]

Maximum PWM Duty Cycle

R/W

This register sets the maximum % duty cycle output in automatic fan speed
control mode for all four PWM outputs.

POR = 0xC0, Lock = Y, SW Reset = Y.

Table 66. Register 0x30 Thermal Mask Register 1

Bit Name

R/W

Description

Reserved

R/W

Reserved for future use.

1 Local

Temp

R/W A 1 masks ALERTs for an out-of-limit condition on the local temperature channel.

2 Remote

Temp

R/W A 1 masks ALERTs for an out-of-limit condition on the Remote 1 temperature channel.

3 Remote

Temp

R/W A 1 masks ALERTs for an out-of-limit condition on the Remote 2 temperature channel.

4 Remote

Temp

R/W A 1 masks ALERTs for an out-of-limit condition on the Remote 3 temperature channel.

Diode 1 Error

R/W

A 1 masks ALERTs for an open or short condition on the Remote 1 channel.

Diode 2 Error

R/W

A 1 masks ALERTs for an open or short condition on the Remote 2 channel.

Diode 3 Error

R/W

A 1 masks ALERTs for an open or short condition on the Remote 3 channel.

POR = 0x00, Lock = N, SW Reset = Y.

Table 67. Register 0x31 Thermal Mask Register 2

Bit Name

R/W Description

THERM1 %

R/W

A 1 masks ALERTs for the corresponding interrupt status bit. Default = 0.

THERM1 Assert

R/W

A 1 masks ALERTs for the corresponding interrupt status bit. Default = 0.

THERM1 State

R/W

A 1 masks ALERTs for the corresponding interrupt status bit. Default = 0.

THERM2 %

R/W

A 1 masks ALERTs for the corresponding interrupt status bit. Default = 0.

THERM2 Assert

R/W

A 1 masks ALERTs for the corresponding interrupt status bit. Default = 0.

THERM2 State

R/W

A 1 masks ALERTs for the corresponding interrupt status bit. Default = 0.

6 VRD1_Assert

R/W A 1 masks ALERTs for the corresponding interrupt status bit. Default = 1.

7 VRD2_Assert

R/W A 1 masks ALERTs for the corresponding interrupt status bit. Default = 1.

POR = 0xC0, Lock = N, SW Reset = Y.

ADT7462

Rev. 0 | Page 80 of 92

Table 68. Register 0x32 Voltage Mask Register 1

Bit Name

R/W

Description

0 +12V1

R/W

A 1 masks ALERTs for the corresponding interrupt status bit.

1 +12V2

R/W

A 1 masks ALERTs for the corresponding interrupt status bit.

2 +12V3

R/W

A 1 masks ALERTs for the corresponding interrupt status bit.

3 +3.3V

R/W

A 1 masks ALERTs for the corresponding interrupt status bit.

4 Pin

Voltage

R/W

A 1 masks ALERTs for the corresponding interrupt status bit.

5 Pin

Voltage

R/W

A 1 masks ALERTs for the corresponding interrupt status bit.

6 +5V

R/W

A 1 masks ALERTs for the corresponding interrupt status bit.

7 Pin

Voltage

R/W

A 1 masks ALERTs for the corresponding interrupt status bit.

POR = 0x00, Lock = N, SW Reset = Y.

Table 69. Register 0x33 Voltage Mask Register 2

Bit Name

R/W

Description

[2:0]

Reserved

R/W

Reserved for future use.

3 Pin

Voltage

R/W A 1 masks ALERTs for the corresponding interrupt status bit.

4 Pin

Voltage

R/W A 1 masks ALERTs for the corresponding interrupt status bit.

5 Pin

Voltage

R/W A 1 masks ALERTs for the corresponding interrupt status bit.

6 +1.5V2

(3GIO)

R/W A 1 masks ALERTs for the corresponding interrupt status bit.

7 +1.5V1

(ICH)

R/W A 1 masks ALERTs for the corresponding interrupt status bit.

POR = 0x00, Lock = N, SW Reset = Y.

Table 70. Register 0x34 Fan Mask Register 1

Bit Name

R/W

Description

Fan 1 Fault

R/W

A 1 masks ALERTS for the corresponding interrupt status bit.

Fan 2 Fault

R/W

A 1 masks ALERTS for the corresponding interrupt status bit.

Fan 3 Fault

R/W

A 1 masks ALERTS for the corresponding interrupt status bit.

Fan 4 Fault

R/W

A 1 masks ALERTS for the corresponding interrupt status bit.

Fan 5 Fault

R/W

A 1 masks ALERTS for the corresponding interrupt status bit.

Fan 6 Fault

R/W

A 1 masks ALERTS for the corresponding interrupt status bit.

Fan 7 Fault

R/W

A 1 masks ALERTS for the corresponding interrupt status bit.

Fan 8 Fault

R/W

A 1 masks ALERTS for the corresponding interrupt status bit.

POR = 0x00, Lock = N, SW Reset = Y.

Table 71. Register 0x35 Digital Mask Register 1

Bit Name

R/W

Description

[2:0]

Reserved

Reserved for future use.

FAN2MAX

R/W

A 1 masks ALERTs for the corresponding interrupt status bit. Default = 1.

4 SCSI_Term1

R/W

A 1 masks ALERTs for the corresponding interrupt status bit. Default = 1.

5 SCSI_Term2

R/W

A 1 masks ALERTs for the corresponding interrupt status bit. Default = 1.

6 VID

Comparison

R/W

A 1 masks ALERTs for the corresponding interrupt status bit. Default = 0.

7 Chassis

Intrusion R/W

A 1 masks ALERTs for the corresponding interrupt status bit. Default = 0.

POR = 0x38, Lock = N, SW Reset = Y.

ADT7462

Rev. 0 | Page 81 of 92

Table 72. Register 0x36 GPIO Mask Register

Bit Name

R/W Description

0 GPIO1 R/W A 1 masks ALERTs for the corresponding interrupt status bit.

1 GPIO2 R/W A 1 masks ALERTs for the corresponding interrupt status bit.

2 GPIO3 R/W A 1 masks ALERTs for the corresponding interrupt status bit.

3 GPIO4 R/W A 1 masks ALERTs for the corresponding interrupt status bit.

4 GPIO5 R/W A 1 masks ALERTs for the corresponding interrupt status bit.

5 GPIO6 R/W A 1 masks ALERTs for the corresponding interrupt status bit.

6 GPIO7 R/W A 1 masks ALERTs for the corresponding interrupt status bit.

7 GPIO8 R/W A 1 masks ALERTs for the corresponding interrupt status bit.

POR = 0x00, Lock = N, SW Reset = Y.

Table 73. Register 0x37 EDO 1 Mask Register

Bit Name

R/W Description

GPIO1

R/W

A 1 masks GPIO1 from causing an EDO1 assertion.

GPIO2

R/W

A 1 masks GPIO2 from causing an EDO1 assertion.

GPIO3

R/W

A 1 masks GPIO3 from causing an EDO1 assertion.

GPIO4

R/W

A 1 masks GPIO4 from causing an EDO1 assertion.

4 Unused

R/W Unused.

Fan

R/W

A 1 masks a fan fail condition from causing an EDO1 assertion.

6 Temp

R/W A 1 masks a THERM condition from causing an EDO1 assertion.

Volt

R/W

A 1 masks a voltage exceed limit condition from causing an EDO1 assertion.

POR = 0x00, Lock = N, SW Reset = Y.

Table 74. Register 0x38 EDO 2 Mask Register

Bit Name

R/W Description

GPIO1

R/W

A 1 masks GPIO1 from causing an EDO2 assertion.

GPIO2

R/W

A 1 masks GPIO2 from causing an EDO2 assertion.

GPIO3

R/W

A 1 masks GPIO3 from causing an EDO2 assertion.

GPIO4

R/W

A 1 masks GPIO4 from causing an EDO2 assertion.

4 Unused

R/W Unused.

Fan

R/W

A 1 masks a fan fail condition from causing an EDO2 assertion.

6 Temp

R/W A 1 masks a THERM condition from causing an EDO2 assertion.

Volt

R/W

A 1 masks a voltage exceed limit condition from causing an EDO2 assertion.

POR = 0x00, Lock = N, SW Reset = Y.

Table 75. Register 0x3D Device ID Register

Bit Name

R/W

Description

[7:0]

Device ID

This register contains the device ID (0x62) for the ADT7462.

POR = 0x62.

Table 76. Register 0x3E Company ID Register

Bit Name

R/W

Description

[7:0]

Company ID

This register contains the company ID (0x41) for the ADT7462.

POR = 0x41.

ADT7462

Rev. 0 | Page 82 of 92

Table 77. Register 0x3F Revision Register

Bit Name

R/W

Description

[7:0]

Revision ID

This register contains the revision ID (0x03) for the ADT7462.

POR = 0x04.

Table 78. Temperature Limit Registers

Register Address

R/W

Description

Lockable

POR Default

0x44

R/W

Local low temperature limit

0x40

0x45

R/W

Remote 1 low temperature/Pin 15 voltage low limit

0x40

0x46

R/W

Remote 2 low temperature limit

0x40

0x47

R/W

Remote 3 low temperature/Pin 19 voltage low limit

0x40

0x48

R/W

Local high temperature limit

0x95

0x49

R/W

Remote 1 high temperature/Pin 15 voltage high limit

0x95

0x4A

R/W

Remote 2 high temperature limit

0x95

0x4B

R/W

Remote 3 high temperature/Pin 19 voltage high limit

0x95

0x4C R/W

Local THERM1 temperature limit/+1.5V1 (ICH) voltage high limit

Yes 0xA4

0x4D R/W

Remote 1 THERM1 temperature limit

Yes 0xA4

0x4E R/W

Remote 2THERM1 temperature limit

Yes 0xA4

0x4F R/W

Remote 3 THERM1 temperature limit

Yes 0xA4

0x50 R/W

Local THERM2 temperature limit/+1.5V2 (3GIO) voltage high limit

Yes 0xA4

0x51 R/W

Remote 1 THERM2 temperature limit

Yes 0xA4

0x52 R/W

Remote 2 THERM2 temperature limit

Yes 0xA4

0x53 R/W

Remote 3 THERM2 temperature limit

Yes 0xA4

SW Reset = N.

Table 79. Register 0x54 Local/Remote 1 Hysteresis

Bit Name

R/W

Description

[3:0]

Remote 1 Hystereis

R/W

These four bits set the Remote 1 THERM hysteresis value, 1 LSB = 1°C

[7:4] Local

Hysteresis

R/W

These four bits set the local THERM hysteresis value, 1 LSB = 1°C

0000 = 0°C

0001 = 1°C

0010 = 2°C

0011 = 3°C

0100 = 4°C (default)

0101 = 5°C

0110 = 6°C

0111 = 7°C

1000 = 8°C

1001 = 9°C

1010 = 10°C

1011 = 11°C

1100 = 12°C

1101 = 13°C

1110 = 14°C

1111 = 15°C

POR = 0x44, Lock = Y, SW Reset = N.

ADT7462

Rev. 0 | Page 83 of 92

Table 80. Register 0x55 Remote 2/Remote 3 Hysteresis

Bit Name

R/W

Description

[3:0]

Remote 3 Hysteresis

R/W

These four bits set the Remote 3 THERM hysteresis value,1 LSB = 1°C

[7:4]

Remote 2 Hysteresis

R/W

These four bits set the Remote 2 THERM hysteresis value,1 LSB = 1°C

0000 = 0°C

0001 = 1°C

0010 = 2°C

0011 = 3°C

0100 = 4°C (default)

0101 = 5°C

0110 = 6°C

0111 = 7°C

1000 = 8°C

1001 = 9°C

1010 = 10°C

1011 = 11°C

1100 = 12°C

1101 = 13°C

1110 = 14°C

1111 = 15°C

POR = 0x44, Lock = Y, SW Reset = N.

Table 81. Offset Registers

Register Address

R/W

Description

POR Default

0x56

R/W

Local offset, resolution = 0.5°C

0x00

0x57

R/W

Remote 1 offset, resolution = 0.5°C

0x00

0x58

R/W

Remote 2 offset, resolution = 0.5°C

0x00

0x59

R/W

Remote 3 offset, resolution = 0.5°C

0x00

Lock = Y, SW Reset = N.

Table 82. Operating Point Registers

Register Address

R/W

Description

POR Default

0x5A

R/W

Remote 1 operating point

0xA4

0x5B

R/W

Remote 2 operating point

0xA4

Lock = N, SW Reset = Y.

Table 83. Timing Registers

Register Address

R/W

Description

POR Default

0x5C R/W

Local

MIN

0x9A

0x5D R/W

Remote

MIN

0x9A

0x5E R/W

Remote

MIN

0x9A

0x5F R/W

Remote

MIN

0x9A

Lock = Y, SW Reset = Y.

ADT7462

Rev. 0 | Page 84 of 92

Table 84. T

RANGE

/Hysteresis Registers

R/W Description POR

Default

0x60 R/W

Local T

RANGE

Hysteresis

0xC4

0x61 R/W

Remote T

RANGE

Hysteresis

0xC4

0x62 R/W

Remote
T

RANGE

Hysteresis

0xC4

0x63 R/W

Remote
T

RANGE

Hysteresis

0xC4

Bit

Name

R/W

Description

[3:0]

Hysteresis

R/W

These four bits set the hysteresis in the automatic fan speed control loop and
in the dynamic T

MIN

control loop, 1 LSB = 1°C.

0000 = 0°C

0001 = 1°C

0010 = 2°C

0011 = 3°C

0100 = 4°C (default)

0101 = 5°C

0110 = 6°C

0111 = 7°C

1000 = 8°C

1001 = 9°C

1010 = 10°C

1011 = 11°C

1100 = 12°C

1101 = 13°C

1110 = 14°C

1111 = 15°C

[7:4]

RANGE

e R/W These four bits set the T

RANGE

value, that is, the slope or rate of change of fan speed

with respect to temperature in the automatic fan speed control loop.

0000 = 2°C

0001 = 2.5°C

0010 = 3.3°C

0011 = 4°C

0100 = 5°C

0101 = 6.7°C

0110 = 8°C

0111 = 10°C

1000 = 13.3°C

1001 = 16°C

1010 = 20°C

1011 = 26.7°C

1100 = 32°C (default)

1101 = 40°C

1110 = 53.3°C

1111 = 80°C

Lock = Y, SW Reset = Y.

ADT7462

Rev. 0 | Page 85 of 92

Table 85. Register 0x64 Operating Point Hysteresis

Bit Name

R/W

Description

[3:0]

Reserved

Reserved for future use.

[7:4]

Operating Point Hysteresis

R/W

These four bits set the operating point hysteresis for the dynamic T

MIN

control loop, 1 LSB = 1°C.

0000 = 0°C

0001 = 1°C

0010 = 2°C

0011 = 3°C

0100 = 4°C (default)

0101 = 5°C

0110 = 6°C

0111 = 7°C

1000 = 8°C

1001 = 9°C

1010 = 10°C

1011 = 11°C

1100 = 12°C

1101 = 13°C

1110 = 14°C

1111 = 15°C

POR = 0x40, Lock = Y, SW Reset = Y.

Table 86. Voltage Limit Registers

Register Address

R/W

Description

POR Default

0x68

R/W

+3.3V high limit

0xFF

0x69

R/W

Pin 23 voltage high limit

0xFF

0x6A

R/W

Pin 24 voltage high limit

0xFF

0x6B

R/W

Pin 25 voltage high limit

0xFF

0x6C

R/W

Pin 26 voltage high limit

0xFF

0x6D

R/W

+12V1 voltage low limit

0x00

0x6E

R/W

+12V2 voltage low limit

0x00

0x6F

R/W

+12V3 voltage low limit

0x00

0x70

R/W

+3.3V low limit

0x00

0x71

R/W

+5V low limit

0x00

0x72

R/W

Pin 23 voltage low limit

0x20

0x73

R/W

Pin 24 voltage low limit

0x00

0x74

R/W

Pin 25 voltage low limit

0x00

0x75

R/W

Pin 26 voltage low limit

0x80

0x76

R/W

+1.5V1 (ICH) voltage low limit

0x00

0x77

R/W

+1.5V2 (3GIO) voltage low limit

0x00

Lock = N, SW Reset = N.

ADT7462

Rev. 0 | Page 86 of 92

Table 87. TACH Limit Registers

Register Address

R/W

Description

POR Default

0x78

R/W

TACH1 limit/VID limit

0xFF

0x79 R/W

TACH2

limit

0xFF

0x7A R/W

TACH3

limit

0xFF

0x7B R/W

TACH4

limit

0xFF

0x7C

R/W

TACH5 limit/+12V1 voltage high limit

0xFF

0x7D

R/W

TACH6 limit/+12V2 voltage high limit

0xFF

0x7E

R/W

TACH7 limit/+5V voltage high limit

0xFF

0x7F

R/W

TACH8 limit/+12V3 voltage high limit

0xFF

Lock = Y, SW Reset = N.

Table 88. THERM Timer Limit

Register Address

R/W

Description

POR Default

0x80 R/W

THERM1 % Limit

0xFF

0x81 R/W

THERM2 % Limit

0xFF

Lock = Y, SW Reset = N.

Table 89. Temperature Value Registers

Register Address

R/W

Description

0x88

Bit [7:6] Local temperature value, LSBs

0x89

Local temperature value, MSBs

0x8A

Bit [7:6] Remote 1 temperature value, LSBs

0x8B

Remote 1 temperature value, MSBs/Pin 15 Voltage

0x8C

Bit [7:6] Remote 2 temperature value, LSBs

0x8D

Remote 2 temperature value, MSBs

0x8E

Bit [7:6] Remote 3 temperature value, LSBs

0x8F

Remote 3 temperature value, MSBs/Pin 19 voltage

Lock = N, SW Reset = N.

Table 90. Voltage Value Registers

Register Address

R/W

Description

0x90

Pin 23 voltage value

0x91

Pin 24 voltage value

0x92

Pin 25 voltage value

0x93

Pin 26 voltage value

0x94

+1.5V1 (ICH) voltage value

0x95

+1.5V2 (3GIO) voltage value

0x96

+3.3V voltage value

Lock = N, SW Reset = N.

Table 91. VID Value Register

Register Address

R/W

Description

0x97

This register reports the state of the 7 VID inputs.

Lock = N, SW Reset = N.

ADT7462

Rev. 0 | Page 87 of 92

Table 92. TACH Value Registers

Register Address

R/W

Description

0x98 R

TACH1,

LSB

0x99 R

TACH1,

MSB

0x9A R

TACH2,

LSB

0x9B R

TACH2,

MSB

0x9C R

TACH3,

LSB

0x9D R

TACH3,

MSB

0x9E R

TACH4,

LSB

0x9F R

TACH4,

MSB

0xA2 R

TACH5,

LSB

0xA3

TACH5, MSB/+12V1 voltage value register

0xA4 R

TACH6,

LSB

0xA5

TACH6, MSB/+12V2 voltage value register

0xA6 R

TACH7,

LSB

0xA7

TACH7, MSB/+5V voltage value register

0xA8 R

TACH8,

LSB

0xA9

TACH8, MSB/+12V3 voltage value register

Lock = N, SW Reset = N.

Table 93. Current PWM Duty Cycle Registers

Register Address

R/W

Description

0xAA

R/W

PWM1 current duty cycle

0xAB

R/W

PWM2 current duty cycle

0xAC

R/W

PWM3 current duty cycle

0xAD

R/W

PWM4 current duty cycle

Lock = N, SW Reset = N.

Table 94. THERM Timer Value Registers

Register Address

R/W

Description

POR Default

0xAE R

THERM1 timer % on-time value

0x00

0xAF R

THERM2 timer % on-time value

0x00

Lock = N, SW Reset = N.

Table 95. Register 0x0B8 Host Thermal Status Register 1

Register 0x0CO BMC Thermal Status Register 1

Bit Name

R/W

Description

Reserved

Reserved for future use.

Local Temp

A 1 indicates that a local temperature limit has been tripped.

Remote 1 Temp

A 1 indicates that a Remote 1 temperature limit has been tripped.

Remote 2 Temp

A 1 indicates that a Remote 2 temperature limit has been tripped.

Remote 3 Temp

A 1 indicates that a Remote 3 temperature limit has been tripped.

Diode 1 Error

A 1 indicates that a Remote 1 diode error, either an open or a short, has occurred.

Diode 2 Error

A 1 indicates that a Remote 2 diode error, either an open or a short, has occurred.

Diode 3 Error

A 1 indicates that a Remote 3 diode error, either an open or a short, has occurred.

POR = 0x00, Lock = N, SW Reset = Y.

ADT7462

Rev. 0 | Page 88 of 92

Table 96. Register 0xB9 Host Thermal Status Register 2

Register 0xC1 BMC Thermal Status Register 2

Bit Name

R/W Description

THERM1 %

A 1 indicates that THERM1 has been asserted for longer than the programmed THERM1 timer limit.

THERM1 Assert

A 1 indicates that THERM1 is asserted.

THERM1 State

A 1 indicates that a transition from high to low has taken place on the THERM1 pin.

THERM2 %

A 1 indicates that THERM2 has been asserted for longer than the programmed THERM2 timer limit.

THERM2 Assert

A 1 indicates that THERM2 is asserted.

THERM2 State

A 1 indicates that a transition from high to low has taken place on the THERM2 pin.

VRD1_Assert

A 1 indicates that VRD1 is asserted.

VRD2_Assert

A 1 indicates that VRD2 is asserted.

POR = 0x00, Lock = N, SW Reset = Y.

Table 97. Register 0xBA Thermal Status Register 3

Bit Name

R/W

Description

Local THERM1

A 1 indicates that the local THERM1 limit has been exceeded.

Remote 1 THERM1

A 1 indicates that the Remote 1 THERM1 limit has been exceeded.

Remote 2 THERM1

A 1 indicates that the Remote 2 THERM1 limit has been exceeded.

Remote 3 THERM1

A 1 indicates that the Remote 3 THERM1 limit has been exceeded.

Local THERM2

A 1 indicates that the Local THERM2 limit has been exceeded.

Remote 1 THERM2

A 1 indicates that the Remote 1 THERM2 limit has been exceeded.

Remote 2 THERM2

A 1 indicates that the Remote 2 THERM2 limit has been exceeded.

Remote 3 THERM2

A 1 indicates that the Remote 3 THERM2 limit has been exceeded.

POR = 0x00, Lock = N, SW Reset = Y.

Table 98. Register 0xBB Host Voltage Register 1

Register 0xC3 BMC Voltage Register 1

Bit Name

R/W

Description

+12V1

A 1 indicates that a +12V1 voltage limit has been tripped.

+12V2

A 1 indicates that a +12V2 voltage limit has been tripped.

+12V3

A 1 indicates that a +12V3 voltage limit has been tripped.

+3.3V

A 1 indicates that a +3.3V voltage limit has been tripped.

Pin 15 Voltage

A 1 indicates that a Pin 15 voltage limit has been tripped.

Pin 19 Voltage

A 1 indicates that a Pin 19 voltage limit has been tripped.

+5V

A 1 indicates that a +5V voltage limit has been tripped.

Pin 23 Voltage

A 1 indicates that a Pin 23 voltage limit has been tripped.

POR = 0x00, Lock = N, SW Reset = Y.

ADT7462

Rev. 0 | Page 89 of 92

Table 99. Register 0xBC Host Voltage Status Register 2

Register 0xC4 BMC Voltage Status Register 2

Bit Name

R/W

Description

[2:0]

Reserved

Reserved for future use.

Pin 24 Voltage

A 1 indicates that a Pin 24 voltage limit has been tripped.

Pin 25 Voltage

A 1 indicates that a Pin 25 voltage limit has been tripped.

Pin 26 Voltage

A 1 indicates that a Pin 26 voltage limit has been tripped.

+1.5V2 (3GIO)

A 1 indicates that a +1.5V2 (3GIO) voltage limit has been tripped.

+1.5V1 (ICH)

A 1 indicates that a +1.5V1 (ICH) voltage limit has been tripped.

POR = 0x00, Lock = N, SW Reset = Y.

Table 100. Register 0xBD Host Fan Status Register 1

Register 0xC5 BMC Fan Status Register 1

Bit Name

R/W

Description

Fan 1 Fault

A 1 indicates a Fan 1 fault.

Fan 2 Fault

A 1 indicates a Fan 2 fault.

Fan 3 Fault

A 1 indicates a Fan 3 fault.

Fan 4 Fault

A 1 indicates a Fan 4 fault.

Fan 5 Fault

A 1 indicates a Fan 5 fault.

Fan 6 Fault

A 1 indicates a Fan 6 fault.

Fan 7 Fault

A 1 indicates a Fan 7 fault.

Fan 8 Fault

A 1 indicates a Fan 8 fault.

POR = 0x00, Lock = N, SW Reset = Y.

Table 101. Register 0xBE Host Digital Status Register 1

Register 0xC6 BMC Digital Status Register 1

Bit Name

R/W

Description

[2:0]

Reserved

Reserved for future use.

FAN2MAX

A 1 indicates that the FAN2MAX has been asserted as an input.

SCSI_Term1

A 1 indicates that the SCSI_Term1 digital input has been asserted.

SCSI_Term2

A 1 indicates that the SCSI_Term2 digital input has been asserted.

VID Comparison

A 1 indicates a VID comparison fault.

Chassis Intrusion

A 1 indicates that the chassis intrusion digital input has been asserted.

POR = 0x00, Lock = N, SW Reset = Y.

Table 102. Register 0xBF GPIO Status Register

Bit Name

R/W

Description

GPIO1

R/W

A 1 indicates that GPIO1 is asserted.

GPIO2

R/W

A 1 indicates that GPIO2 is asserted.

GPIO3

R/W

A 1 indicates that GPIO3 is asserted.

GPIO4

R/W

A 1 indicates that GPIO4 is asserted.

GPIO5

R/W

A 1 indicates that GPIO5 is asserted.

GPIO6

R/W

A 1 indicates that GPIO6 is asserted.

GPIO7

R/W

A 1 indicates that GPIO7 is asserted.

GPIO8

R/W

A 1 indicates that GPIO8 is asserted.

POR = 0x00, Lock = N, SW Reset = Y.

ADT7462

Rev. 0 | Page 90 of 92

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

0.30
0.23
0.18

0.20 REF

0.80 MAX
0.65 TYP

0.05 MAX
0.02 NOM

12° MAX

1.00
0.85
0.80

SEATING

PLANE

COPLANARITY

0.08

0.50
0.40
0.30

3.50 REF

0.50

BSC

PIN 1

INDICATOR

TOP

VIEW

5.00

BSC SQ

4.75

BSC SQ

3.25
3.10 SQ
2.95

PIN 1

INDICATOR

0.60 MAX

0.25 MIN

EXPOSED

PAD

(BOTTOM VIEW)

Figure 86. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

ADT7462ACPZ-500RL7

-40°C to +125°C

32-Lead LFCSP_VQ

CP-32-2

ADT7462ACPZ-REEL

-40°C to +125°C

32-Lead LFCSP_VQ

CP-32-2

ADT7462ACPZ -REEL7

-40°C to +125°C

32-Lead LFCSP_VQ

CP-32-2

EVAL-ADT7462EB

Evaluation

Board

Z = Pb-free part.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADT7462ACPZ-REEL

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADT7462ACPZ-REEL