Document Outline
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- FUNCTIONAL BLOCK DIAGRAM
- SPECIFICATIONS
- ELECTRICAL SPECIFICATIONS, 5 V OPERATION
- ELECTRICAL SPECIFICATIONS, 3.3 V OPERATION
- ELECTRICAL SPECIFICATIONS, MIXED 5 V/3 V or 3 V/5 V OPERATION
- PACKAGE CHARACTERISTICS
- REGULATORY INFORMATION
- INSULATION AND SAFETY-RELATED SPECIFICATIONS
- DIN EN 60747-5-2 (VDE 0884 Part 2) INSULATION CHARACTERISTICS
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- PIN CONFIGURATION
- ORDERING GUIDE
- Typical Performance Characteristics
- APPLICATION INFORMATION
- PC Board Layout
- Propagation Delay-Related Parameters
- Method of Operation, DC Correctness, and Magnetic Field Immunity
- OUTLINE DIMENSIONS
- Revision History
REV. E
a
ADuM1100
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
2003 Analog Devices, Inc. All rights reserved.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
iCoupler
Digital Isolator
FEATURES
High Data Rate: DC to 100 Mbps (NRZ)
Compatible with 3.3 V and 5.0 V Operation/
Level Translation
125 C Max Operating Temperature
Low Power Operation
5 V Operation
1.0 mA Max @ 1 Mbps
4.5 mA Max @ 25 Mbps
16.8 mA Max @ 100 Mbps
3.3 V Operation
0.4 mA Max @ 1 Mbps
3.5 mA Max @ 25 Mbps
7.1 mA Max @ 50 Mbps
8-Lead SOIC Package (lead-free version available)
High Common-Mode Transient Immunity: >25 kV/ s
Safety and Regulatory Information
UL Recognized
2500 V rms for 1 Minute per UL 1577
CSA Component Acceptance Notice No. 5A
VDE Certificate of Conformity
DIN EN 60747-5-2 (VDE 0884 Part 2): 200301
DIN EN 60950 (VDE 0805): 200112; EN 60950: 2000
V
IORM
= 560 V
PEAK
APPLICATIONS
Digital Fieldbus Isolation
Opto-Isolator Replacement
Computer-Peripheral Interface
Microprocessor System Interface
General Instrumentation and Data Acquisition
Applications
GENERAL DESCRIPTION
The ADuM1100 is a digital isolator based on Analog Devices'
iCoupler technology. Combining high speed CMOS and mono-
lithic air core transformer technology, this isolation component
provides outstanding performance characteristics superior to
alternatives such as optocoupler devices.
Configured as a pin compatible replacement for existing high speed
optocouplers, the ADuM1100 supports data rates as high as
25 Mbps and 100 Mbps.
The ADuM1100 operates with either voltage supply ranging from
3.0 V to 5.5 V, boasts a propagation delay of <18 ns and edge
asymmetry of <2 ns, and is compatible with temperatures up to
125
C. It operates at very low power, less than 0.9 mA of quiescent
current (sum of both sides), and a dynamic current of less than
160
A per Mbps of data rate. Unlike other optocoupler alter-
natives, the ADuM1100 provides dc correctness with a patented
refresh feature that continuously updates the output signal.
The ADuM1100 is offered in three grades. The ADuM1100AR
and ADuM1100BR can operate up to a maximum temperature
of 105
C and support data rates up to 25 Mbps and 100 Mbps,
respectively. The ADuM1100UR can operate up to a maximum
temperature of 125
C and supports data rates up to 100 Mbps.
FUNCTIONAL BLOCK DIAGRAM
WATCHDOG
E
N
C
O
D
E
D
E
C
O
D
E
UPDATE
V
DD1
V
I
(DATA IN)
V
DD1
GND
1
V
DD2
GND
2
V
O
(DATA OUT)
GND
2
ADuM1100
FOR PRINCIPLES OF OPERATION, SEE METHOD OF OPERATION,
DC CORRECTNESS, AND MAGNETIC FIELD IMMUNITY SECTION.
REV. E
2
ADuM1100SPECIFICATIONS
ELECTRICAL SPECIFICATIONS, 5 V OPERATION
1
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current
I
DD1(Q)
0.3
0.8
mA
V
I
= 0 V or V
DD1
Output Supply Current
I
DD2(Q)
0.01
0.06
mA
V
I
= 0 V or V
DD1
Input Supply Current (25 Mbps)
I
DD1(25)
2.2
3.5
mA
12.5 MHz Logic Signal Frequency
(See TPC 1)
Output Supply Current
2
(25 Mbps)
I
DD2(25)
0.5
1.0
mA
12.5 MHz Logic Signal Frequency
(See TPC 2)
Input Supply Current (100 Mbps)
I
DD1(100)
9.0
14
mA
50 MHz Logic Signal Frequency,
(See TPC 1)
ADuM1100BR/ADuM1100UR Only
Output Supply Current
2
(100 Mbps)
I
DD2(100)
2.0
2.8
mA
50 MHz Logic Signal Frequency,
(See TPC 2)
ADuM1100BR/ADuM1100UR Only
Input Current
I
I
10
+0.01 +10
A
0
V
IN
V
DD1
Logic High Output Voltage
V
OH
V
DD2
0.1 5.0
V
I
O
= 20
A, V
I
= V
IH
V
DD2
0.8 4.6
V
I
O
= 4 mA, V
I
= V
IH
Logic Low Output Voltage
V
OL
0.0
0.1
V
I
O
= 20
A, V
I
= V
IL
0.03
0.1
V
I
O
= 400
A, V
I
= V
IL
0.3
0.8
V
I
O
= 4 mA, V
I
= V
IL
SWITCHING SPECIFICATIONS
For ADuM1100AR
Minimum Pulse Width
3
PW
40
ns
C
L
= 15 pF, CMOS Signal Levels
Maximum Data Rate
4
25
Mbps
C
L
= 15 pF, CMOS Signal Levels
For ADuM1100BR/ADuM1100UR
Minimum Pulse Width
3
PW
6.7
10
ns
C
L
= 15 pF, CMOS Signal Levels
Maximum Data Rate
4
100
150
Mbps
C
L
= 15 pF, CMOS Signal Levels
For All Grades
Propagation Delay Time
t
PHL
10.5
18
ns
C
L
= 15 pF, CMOS Signal Levels
to Logic Low Output
5, 6
(See TPC 3)
Propagation Delay Time
t
PLH
10.5
18
ns
C
L
= 15 pF, CMOS Signal Levels
to Logic High Output
5, 6
(See TPC 3)
Pulse Width Distortion |t
PLH
t
PHL
|
6
PWD
0.5
2
ns
C
L
= 15 pF, CMOS Signal Levels
Change versus Temperature
7
3
ps/
C
C
L
= 15 pF, CMOS Signal Levels
Propagation Delay Skew
t
PSK1
8
ns
C
L
= 15 pF, CMOS Signal Levels
(Equal Temperature)
6, 8
Propagation Delay Skew
t
PSK2
6
ns
C
L
= 15 pF, CMOS Signal Levels
(Equal Temperature, Supplies)
6, 8
Output Rise/Fall Time
t
R
, t
F
3
ns
C
L
= 15 pF, CMOS Signal Levels
Common-Mode Transient Immunity
|CM
L
|,
25
35
kV/
s
V
I
= 0 or V
DD1
, V
CM
= 1000 V,
at Logic Low/High Output
9
|CM
H
|
Transient Magnitude = 800 V
Input Dynamic Power
C
PD1
35
pF
Dissipation Capacitance
10
Output Dynamic Power
C
PD2
8
pF
Dissipation Capacitance
10
See Notes on page 5.
Specifications subject to change without notice.
(4.5 V
V
DD1
5.5 V, 4.5 V V
DD2
5.5 V. All min/max
specifications apply over the entire recommended operation
range, unless otherwise noted. All typical specifications are at T
A
= 25 C, V
DD1
= V
DD2
= 5 V.)
REV. E
3
ADuM1100
ELECTRICAL SPECIFICATIONS, 3.3 V OPERATION
1
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current
I
DD1(Q)
0.1
0.3
mA
V
I
= 0 V or V
DD1
Output Supply Current
I
DD2(Q)
0.005 0.04
mA
V
I
= 0 V or V
DD1
Input Supply Current (25 Mbps)
I
DD1(25)
2.0
2.8
mA
12.5 MHz Logic Signal Frequency
(See TPC 1)
Output Supply Current
2
(25 Mbps)
I
DD2(25)
0.3
0.7
mA
12.5 MHz Logic Signal Frequency
(See TPC 2)
Input Supply Current (50 Mbps)
I
DD1(50)
4.0
6.0
mA
25 MHz Logic Signal Frequency,
(See TPC 1)
ADuM1100BR/ADuM1100UR Only
Output Supply Current
2
(50 Mbps)
I
DD2(50)
1.2
1.6
mA
25 MHz Logic Signal Frequency,
(See TPC 2)
ADuM1100BR/ADuM1100UR Only
Input Current
I
I
10
+0.01 +10
A
0
V
IN
V
DD1
Logic High Output Voltage
V
OH
V
DD2
0.1 3.3
V
I
O
= 20
A, V
I
= V
IH
V
DD2
0.5 3.0
V
I
O
= 2.5 mA, V
I
= V
IH
Logic Low Output Voltage
V
OL
0.0
0.1
V
I
O
= 20
A, V
I
= V
IL
0.04
0.1
V
I
O
= 400
A, V
I
= V
IL
0.3
0.4
V
I
O
= 2.5 mA, V
I
= V
IL
SWITCHING SPECIFICATIONS
For ADuM1100AR
Minimum Pulse Width
3
PW
40
ns
C
L
= 15 pF, CMOS Signal Levels
Maximum Data Rate
4
25
Mbps
C
L
= 15 pF, CMOS Signal Levels
For ADuM1100BR/ADuM1100UR
Minimum Pulse Width
3
PW
10
20
ns
C
L
= 15 pF, CMOS Signal Levels
Maximum Data Rate
4
50
100
Mbps
C
L
= 15 pF, CMOS Signal Levels
For All Grades
Propagation Delay Time to
t
PHL
14.5
28
ns
C
L
= 15 pF, CMOS Signal Levels
Logic Low Output
5, 6
(See TPC 4)
Propagation Delay Time to
t
PLH
15.0
28
ns
C
L
= 15 pF, CMOS Signal Levels
Logic High Output
5, 6
(See TPC 4)
Pulse Width Distortion |t
PLH
t
PHL
|
6
PWD
0.5
3
ns
C
L
= 15 pF, CMOS Signal Levels
Change versus Temperature
7
10
ps/
C
C
L
= 15 pF, CMOS Signal Levels
Propagation Delay Skew
t
PSK1
15
ns
C
L
= 15 pF, CMOS Signal Levels
(Equal Temperature)
6, 8
Propagation Delay Skew
t
PSK2
12
ns
C
L
= 15 pF, CMOS Signal Levels
(Equal Temperature, Supplies)
6, 8
Output Rise/Fall Time
t
R
, t
F
3
ns
C
L
= 15 pF, CMOS Signal Levels
Common-Mode Transient Immunity
|CM
L
|,
25
35
kV/
s
V
I
= 0 or V
DD1
, V
CM
= 1000 V,
at Logic Low/High Output
9
|CM
H
|
Transient Magnitude = 800 V
Input Dynamic Power Dissipation
C
PD1
47
pF
Capacitance
10
Output Dynamic Power Dissipation
C
PD2
14
pF
Capacitance
10
See Notes on page 5.
Specifications subject to change without notice.
(3.0 V
V
DD1
3.6 V, 3.0 V V
DD2
3.6 V. All min/max
specifications apply over the entire recommended operation
range, unless otherwise noted. All typical specifications are at T
A
= 25 C, V
DD1
= V
DD2
= 3.3 V.)
REV. E
ADuM1100
4
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current, Quiescent
I
DDI(Q)
5 V/3 V Operation
0.3
0.8
mA
3 V/5 V Operation
0.1
0.3
mA
Output Supply Current, Quiescent
I
DDO(Q)
5 V/3 V Operation
0.005
0.04
mA
3 V/5 V Operation
0.01
0.06
mA
Input Supply Current, 25 Mbps
I
DDI(25)
5 V/3 V Operation
2.2
3.5
mA
12.5 MHz Logic Signal Frequency
3 V/5 V Operation
2.0
2.8
mA
12.5 MHz Logic Signal Frequency
Output Supply Current, 25 Mbps
I
DDO(25)
5 V/3 V Operation
0.3
0.7
mA
12.5 MHz Logic Signal Frequency
3 V/5 V Operation
0.5
1.0
mA
12.5 MHz Logic Signal Frequency
Input Supply Current, 50 Mbps
I
DDI(50)
5 V/3 V Operation
4.5
7.0
mA
25 MHz Logic Signal Frequency
3 V/5 V Operation
4.0
6.0
mA
25 MHz Logic Signal Frequency
Output Supply Current, 50 Mbps
I
DDO(50)
5 V/3 V Operation
1.2
1.6
mA
25 MHz Logic Signal Frequency
3 V/5 V Operation
1.0
1.5
mA
25 MHz Logic Signal Frequency
Input Currents
I
IA
10
+0.01
+10
A
0
V
IA
, V
IB
, V
IC
, V
ID
V
DD1
or V
DD2
Logic High Output Voltage,
V
OH
V
DD2
0.1 3.3
V
I
O
= 20
A, V
I
= V
IH
5 V/3 V Operation
V
DD2
0.5 3.0
V
I
O
= 2.5 mA, V
I
= V
IH
Logic Low Output Voltage,
V
OL
0.0
0.1
V
I
O
= 20
A, V
I
= V
IL
5 V/3 V Operation
0.04
0.1
V
I
O
= 400
A, V
I
= V
IL
0.3
0.4
V
I
O
= 2.5 mA, V
I
= V
IL
Logic High Output Voltage,
V
OH
V
DD2
0.1 5.0
V
I
O
= 20
A, V
I
= V
IH
3 V/5 V Operation
V
DD2
0.8 4.6
V
I
O
= 4 mA, V
I
= V
IH
Logic Low Output Voltage,
V
OL
0.0
0.1
V
I
O
= 20
A, V
I
= V
IL
3 V/5 V Operation
0.03
0.1
V
I
O
= 400
A, V
I
= V
IL
0.3
0.8
V
I
O
= 4 mA, V
I
= V
IL
SWITCHING SPECIFICATIONS
For ADuM1100AR
Minimum Pulse Width
3
PW
40
ns
C
L
= 15 pF, CMOS Signal Levels
Maximum Data Rate
4
25
Mbps C
L
= 15 pF, CMOS Signal Levels
For ADuM1100BR/ADuM1100UR
Minimum Pulse Width
3
PW
20
ns
C
L
= 15 pF, CMOS Signal Levels
Maximum Data Rate
4
50
Mbps C
L
= 15 pF, CMOS Signal Levels
For All Grades
Propagation Delay Time to Logic
t
PHL,
t
PLH
Low/High Output
5, 6
5 V/3 V Operation (See TPC 5)
13
21
ns
C
L
= 15 pF, CMOS Signal Levels
3 V/5 V Operation (See TPC 6)
16
26
ns
C
L
= 15 pF, CMOS Signal Levels
Pulse Width Distortion, |t
PLH
t
PHL
|
6
PWD
5 V/3 V Operation
0.5
2
ns
C
L
= 15 pF, CMOS Signal Levels
3 V/5 V Operation
0.5
3
ns
C
L
= 15 pF, CMOS Signal Levels
Change versus Temperature
5 V/3 V Operation
3
ps/C
C
L
= 15 pF, CMOS Signal Levels
3 V/5 V Operation
10
ps/C
C
L
= 15 pF, CMOS Signal Levels
Propagation Delay Skew
t
PSK1
(Equal Temperature)
6, 8
5 V/3 V Operation
12
ns
C
L
= 15 pF, CMOS Signal Levels
3 V/5 V Operation
15
ns
C
L
= 15 pF, CMOS Signal Levels
ELECTRICAL SPECIFICATIONS, MIXED 5 V/3 V or 3 V/5 V OPERATION
1
(5 V/3 V operation: 4.5 V
V
DD1
5.5 V, 3.0 V V
DD2
3.6 V.
3 V/5 V operation: 3.0 V
V
DD1
3.6 V, 4.5 V V
DD2
5.5 V. All min/max specifications apply over the entire recommended operation range,
unless otherwise noted. All typical specifications are at T
A
= 25 C, V
DD1
= 3.3 V, V
DD2
= 5 V or V
DD1
= 5 V, V
DD2
= 3.3 V.)
REV. E
5
ADuM1100
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
SWITCHING SPECIFICATIONS (continued)
Propagation Delay Skew
t
PSK2
(Equal Temperature, Supplies)
6, 8
5 V/3 V Operation
9
ns
C
L
= 15 pF, CMOS Signal Levels
3 V/5 V Operation
12
ns
C
L
= 15 pF, CMOS Signal Levels
Output Rise/Fall Time (10% to 90%)
t
R
, t
f
3
ns
C
L
= 15 pF, CMOS Signal Levels
Common-Mode Transient Immunity at
Logic Low/High Output
8
|CM
L
|,
25
35
kV/
s V
I
= 0 or V
DD1
, V
CM
= 1000 V,
|CM
H
|
Transient Magnitude = 800 V
Input Dynamic Power Dissipation Capacitance
10
C
PD1
5 V/3 V Operation
35
pF
3 V/5 V Operation
47
pF
Output Dynamic Power Dissipation Capacitance
10
C
PD2
5 V/3 V Operation
8
pF
3 V/5 V Operation
14
pF
NOTES
1
All voltages are relative to their respective ground.
2
Output supply current values are with no output load present. The supply current drawn at a given signal frequency when an output load is present is given by
I
DD2(L)
= I
DD2
+ V
DD2
f C
L
, where I
DD2
is the unloaded output supply current, f is the input signal frequency, and C
L
is the output load capacitance.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
t
PHL
is measured from the 50% level of the falling edge of the V
I
signal to the 50% level of the falling edge of the V
O
signal. t
PLH
is measured from the 50% level of
the rising edge of the V
I
signal to the 50% level of the rising edge of the V
O
signal.
6
Since the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width distortion
may be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters section and Figures 3 to 7 for information on the impact of given input
rise/fall times on these parameters.
7
Pulse width distortion change versus temperature is the absolute value of the change in pulse width distortion for a 1
C change in operating temperature.
8
t
PSK1
is the magnitude of the worst-case difference in t
PHL
and/or t
PLH
that will be measured between units at the same operating temperature and output load within
the recommended operating conditions. t
PSK2
is the magnitude of the worst-case difference in t
PHL
and/or t
PLH
that will be measured between units at the same operating
temperature, supply voltages, and output load within the recommended operating conditions.
9
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CM
L
is the maximum common-mode voltage slew
rate that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the
range over which the common-mode is slewed.
10
The dynamic power dissipation capacitance is given by
C
PDi
= (I
DDi(100)
I
DDi(Q)
)/(V
DDi
f), where i = 1 or 2 and f is the input signal frequency.
The supply current consumptions at a given frequency and output load are calculated as
I
DD1
= C
PD1
V
DD1
f + I
DD1(Q)
; I
DD2(L)
= (C
PD2
+ C
L
)
V
DD2
f + I
DD2(Q)
, where C
L
is the output load capacitance.
Specifications subject to change without notice.
PACKAGE CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
Resistance (Input-Output)
1
R
IO
10
12
Capacitance (Input-Output)
1
C
IO
1
pF
f = 1 MHz
Input Capacitance
2
C
I
4.0
pF
Input IC Junction-to-Case
JCI
46
C/W
Thermocouple Located at Center
Thermal Resistance
Underside of Package
Output IC Junction-to-Case
JCO
41
C/W
Thermal Resistance
Package Power Dissipation
P
PD
240
mW
NOTES
1
Device considered a 2-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together.
2
Input capacitance is measured at Pin 2 (V
I
).
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