REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

CMOS

80 MHz, Triple 8-Bit Video DAC

ADV101*

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700

Fax: 617/326-8703

FUNCTIONAL BLOCK DIAGRAM

REF WHITE

PIXEL

INPUT

PORT

IOR

IOG

IOB

CLOCK

SYNC

ADV101

REF

GND

BLANK

ADJUST

SYNC

REFERENCE
AMPLIFIER

COMP

RED

REGISTER

BLUE

REGISTER

CONTROL

REGISTER

GREEN

REGISTER

DAC

SYNC

CONTROL

DAC

FEATURES
80 MHz Pipelined Operation
Triple 8-Bit D/A Converters
RS-343A/RS-170 Compatible Outputs
TTL Compatible Inputs
+5 V CMOS Monolithic Construction
40-Pin DIP or 44-Pin PLCC Package
Plug-In Replacement for BT101
Power Dissipation: 400 mW

APPLICATIONS
High Resolution Color Graphics
CAE/CAD/CAM Applications
Image Processing
Instrumentation
Video Signal Reconstruction
Desktop Publishing

SPEED GRADES
80 MHz
50 MHz
30 MHz

GENERAL DESCRIPTION

The ADV101 is a digital-to-analog video converter on a single
monolithic chip. The part is specifically designed for high reso-
lution color graphics and video systems. It consists of three,
high speed, 8-bit, video D/A converters (RGB); a standard TTL
input interface and high impedance, analog output, current
sources.

The ADV101 has three separate, 8-bit, pixel input ports, one
each for red, green and blue video data. Additional video input
controls on the part include sync, blank and reference white. A
single +5 V supply, an external 1.23 V reference and pixel clock
input are all that are required to make the part operational.

The ADV101 is capable of generating RGB video output sig-
nals, which are compatible with RS-343A and RS-170 video
standards, without requiring external buffering.

The ADV101 is fabricated in a +5 V CMOS process. Its mono-
lithic CMOS construction ensures greater functionality with low
power dissipation. The part is packaged in both a 0.6", 40-pin
plastic DIP and a 44-pin plastic leaded (J-lead) chip carrier,
PLCC.

*ADV is a registered trademark of Analog Devices Inc.

PRODUCT HIGHLIGHTS

1. Fast video refresh rate, 80 MHz.

2. Compatible with a wide variety of high resolution color

graphics video systems.

3. Guaranteed monotonic with a maximum differential nonlin-

earity of

0.5 LSB. Integral nonlinearity is guaranteed to be

a maximum of

1 LSB.

REV. B

ADV101SPECIFICATIONS

= +5 V 5%; V

REF

= +1.235 V; R

= 37.5

, C

= 10 pF; R

SET

= 560

. I

SYNC

connected to IOG. All Specifications T

MIN

to T

MAX

unless otherwise noted.)

Parameter

All Versions Units

Test Conditions/Comments

STATIC PERFORMANCE

Resolution (Each DAC)

Bits

Accuracy (Each DAC)

Integral Nonlinearity, INL

LSB max

Differential Nonlinearity, DNL

0.5

LSB max

Guaranteed Monotonic

Gray Scale Error

% Gray Scale max

Max Gray Scale Current: IOG = (V

REF

* 12,082/R

SET

) mA

Max Gray Scale Current:

IOR, IOB = (V

REF

* 8,627/R

SET

) mA

Coding

Binary

DIGITAL INPUTS

Input High Voltage, V

INH

V min

Input Low Voltage, V

INL

0.8

V max

Input Current, I

A max

= 0.4 V or 2.4 V

Input Capacitance, C

pF max

ANALOG OUTPUTS

Gray Scale Current Range

mA min

mA max

Output Current

White Level Relative to Blank

17.69

mA min

Typically 19.05 mA

20.40

mA max

White Level Relative to Black

16.74

mA min

Typically 17.62 mA

18.50

mA max

Black Level Relative to Blank

0.95

mA min

Typically 1.44 mA

1.90

mA max

Blank Level on IOR, IOB

A min

Typically 5

A max

Blank Level on IOG

6.29

mA min

Typically 7.62 mA

9.5

mA max

Sync Level on IOG

A min

Typically 5

A max

LSB Size

69.1

A typ

DAC to DAC Matching

% typ

Output Compliance, V

V min

+1.4

V max

Output Impedance, R

OUT

100

typ

Output Capacitance, C

OUT

pF max

OUT

= 0 mA

VOLTAGE REFERENCE

Voltage Reference Range, V

REF

1.14/1.26

V min/V max

REF

= 1.235 V for Specified Performance

Input Current, I

VREF

+10

A typ

POWER REQUIREMENTS

V nom

125

mA max

Typically 80 mA: 80 MHz Parts

100

mA max

Typically 70 mA: 50 MHz & 35 MHz Parts

Power Supply Rejection Ratio

0.5

%/% max

Typically 0.12%/%: f = 1 kHz, COMP = 0.1

Power Dissipation

625

mW max

Typically 400 mW: 80 MHz Parts

500

mW max

Typically 350 mW: 50 MHz & 30 MHz Parts

DYNAMIC PERFORMANCE

Glitch Impulse

2, 3

pV secs typ

DAC Noise

2, 3, 4

200

pV secs typ

Analog Output Skew

ns max

Typically 1 ns

NOTES

Temperature Range (T

MIN

to T

MAX

); 0

C to +70

Sample tested at +25

C to ensure compliance.

TTL input values are 0 to 3 volts, with input rise/fall times

3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and

outputs. See timing notes in Figure 1.

This includes effects due to clock and data feedthrough as well as RGB analog crosstalk.

Specifications subject to change without notice.

ADV101

REV. B

Parameter

80 MHz Version

50 MHz Version

30 MHz Version

Units

Conditions/Comments

MAX

MHz max

Clock Rate

ns min

Data & Control Setup Time

ns min

Data & Control Hold Time

12.5

33.3

ns min

Clock Cycle Time

ns min

Clock Pulse Width High Time

ns min

Clock Pulse Width Low Time

ns max

Analog Output Delay

ns typ

ns max

Analog Output Rise/Fall Time

ns typ

Analog Output Transition Time

NOTES

TTL input values are 0 to 3 volts, with input rise/fall times

3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and out-

puts. See timing notes in Figure 1.

Temperature range (T

MIN

to T

MAX

): 0

C to +70

Sample tested at +25

C to ensure compliance.

Specifications subject to change without notice.

TIMING CHARACTERISTICS

= +5 V 5%; V

REF

= +1.235 V; R

= 37.5

, C

= 10 pF; R

SET

= 560 .

SYNC

connected to IOG. All Specifications T

MIN

to T

MAX

unless otherwise noted.)

CLOCK

DATA

ANALOG OUTPUTS

(IOR, IOG, IOB, I

SYNC

)

DIGITAL INPUTS

(R0R7, G0G7, B0B7;

SYNC, BLANK,

REF WHITE)

NOTES
1. OUTPUT DELAY (

) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF

CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION.
2. TRANSITION TIME (

) MEASURED FROM THE 50% POINT OF FULL-SCALE

TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE.
3. OUTPUT RISE/FALL TIME (

) MEASURED BETWEEN THE 10% AND 90% POINTS

OF FULL TRANSITION.

Figure 1. Video Input/Output Timing

ADV101

REV. B

WARNING!

ESD SENSITIVE DEVICE

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV101 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

PIN CONFIGURATIONS

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Min

Typ

Max

Units

Power Supply

4.75

5.00

5.25

Volts

Ambient Operating

Temperature

+70

Output Load

37.5

Reference Voltage

REF

1.14

1.235 1.26

Volts

ORDERING GUIDE

Package

Speed

Option

80 MHz

50 MHz

30 MHz

Plastic DIP

(N-40A)

ADV101KN80 ADV101KN50 ADV101KN30

PLCC

(P-44A)

ADV101KP80

ADV101KP50

ADV101KP30

NOTES

All devices are specified for 0

C to +70

C operation.

N = Plastic DIP; P = Plastic Leaded Chip Carrier.

PLCC: Plastic Leaded Chip Carrier (J-lead).

ABSOLUTE MAXIMUM RATINGS

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V

Voltage on Any Digital Pin . . . . GND 0.5 V to V

+ 0.5 V

Ambient Operating Temperature (T

) . . . . . . . . 0

C to +70

Storage Temperature (T

) . . . . . . . . . . . . . . 65

C to +150

Junction Temperature (T

) . . . . . . . . . . . . . . . . . . . . +150

Soldering Temperature (10 secs) . . . . . . . . . . . . . . . . . . 300

Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . . . 220

IOR, IOB, IOG, I

SYNC

to GND

. . . . . . . . . . . . . . 0 V to V

NOTES

Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

Analog output short circuit to any power supply or common can be of an indefinite
duration.

DIP

REF WHITE

COMP

REF

FS ADJUST

GND

SYNC

IOG

IOR

IOB

GND

SYNC

BLANK

GND

CLOCK

TOP VIEW

(NOT TO SCALE)

ADV101

PLCC

ADV101

TOP VIEW

(Not to Scale)

BLANK

SYNC

CLOCK

REF WHITE

COMP

FS ADJUST

GND

IOG

IOR

IOB

GND

REF

SYNC

ADV101

REV. B

PIN FUNCTION DESCRIPTION

Pin
Mnemonic

Function

BLANK

Composite blank control input (TTL compatible). A logic zero on this control input drives the analog outputs,
IOR, IOB and IOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK. While
BLANK

is a logical zero, the R0R7, G0G7, R0R7 and REF WHITE pixel and control inputs are ignored.

SYNC

Composite sync control input (TTL compatible). A logical zero on the SYNC input; switches off a 40 IRE cur-
rent source on the I

SYNC

output. SYNC does not override any other control or data input, therefore, it should

only be asserted during the blanking interval. SYNC is latched on the rising edge of CLOCK.

CLOCK

Clock input (TTL compatible). The rising edge of CLOCK latches the R0R7, G0G7, B0B7, SYNC,
BLANK

and REF WHITE pixel and control inputs. It is typically the pixel clock rate of the video system.

CLOCK should be driven by a dedicated TTL buffer.

REF WHITE

Reference white control input (TTL compatible). A logical one on this input forces the IOR, IOG and IOB out-
puts to the white level, regardless of the pixel input data (R0R7, G0G7 and B0B7) REF WHITE is latched
on the rising edge of clock.

R0R7,

Red, green and blue pixel data inputs (TTL compatible). Pixel data is latched on the rising edge of CLOCK. R0,

G0G7,

G0 and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the regular

B0B7

PCB power or ground plane.

IOR, IOG, IOB

Red, green and blue current outputs. These high impedance current sources are capable of directly driving a
doubly terminated 75

coaxial cable. All three current outputs should have similar output loads whether or not

they are all being used.

SYNC

Sync current output. This high impedance current source can be directly connected to the IOG output. This al-
lows sync information to be encoded onto the green channel. I

SYNC

does not output any current while SYNC is

at logical zero. The amount of current output at I

SYNC

while SYNC is at logical one is given by:

SYNC

(mA) = 3,455

REF

(V)/R

SET

(

)

If sync information is not required on the green channel, I

SYNC

should be connected to AGND.

FS ADJUST

Full-scale adjust control. A resistor (R

SET

) connected between this pin and GND, controls the magnitude of the

full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current.
The relationship between R

SET

and the full-scale output current on IOG (assuming I

SYNC

is connected to IOG)

is given by:

SET

(

) = 12,082

REF

(V)/IOG (mA)

The relationship between R

SET

and the full-scale output current on IOR and IOB is given by:

IOR, IOB (mA) = 8,628

REF

(V)/ R

SET

(

)

COMP

Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1

F ceramic capacitor

must be connected between COMP and V

REF

Voltage reference input. An external 1.2 V voltage reference must be connected to this pin. The use of an exter-
nal resistor divider network is not recommended. A 0.1

F decoupling ceramic capacitor should be connected

between V

REF

and V

Analog power supply (5 V

5%). All V

pins on the ADV101 must be connected.

GND

Ground. All GND pins must be connected.

ADV101

REV. B

TERMINOLOGY

Blanking Level
The level separating the SYNC portion from the video portion
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level which will shut off the pic-
ture tube, resulting in the blackest possible picture.

Color Video (RGB)

This usually refers to the technique of combining the three pri-
mary colors of red, green and blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs are
required, one for each color.

Sync Signal (SYNC)

The position of the composite video signal which synchronizes
the scanning process.

Gray Scale

The discrete levels of video signal between reference black and
reference white levels. An 8-bit DAC contains 256 different lev-
els, while a 6-bit DAC contains 64.

Raster Scan

The most basic method of sweeping a CRT one line at a time to
generate and display images.

Reference Black Level

The maximum negative polarity amplitude of the video signal.

Reference White Level

The maximum positive polarity amplitude of the video signal.

Sync Level

The peak level of the SYNC signal.

Video Signal

That portion of the composite video signal which varies in gray
scale levels between reference white and reference black. Also re-
ferred to as the picture signal, this is the portion which may be
visually observed.

CIRCUIT DESCRIPTION AND OPERATION

The ADV101 contains three 8-bit D/A converters, with three
input channels, each containing an 8-bit register. Also inte-
grated on board the part is a reference amplifier and CRT con-
trol functions BLANK, SYNC and REF WHITE.

Digital Inputs

24-bits of pixel data (color information) R0R7, G0G7 and
B0B7 are latched into the device on the rising edge of each
clock cycle. This data is presented to the three 8-bit DACs and
is then converted to three analog (RGB) output waveforms.
(See Figure 2.)

Three other digital control signals are latched to the analog
video outputs in a similar fashion. BLANK, SYNC and REF
WHITE are each latched on the rising edge of CLOCK to
maintain synchronization with the pixel data stream.

The BLANK and SYNC functions allow for the encoding of
these video synchronization signals onto the RGB video output.
This is done by adding appropriately weighted current sources
to the analog outputs, as determined by the logic levels on the
BLANK

and SYNC digital inputs. Figure 3 shows the analog

output, RGB video waveform of the ADV101. The influence of
SYNC

and BLANK on the analog video waveform is illustrated.

The REF WHITE control input drives the RGB video outputs
to the white level. This function could be used to overlay a cur-
sor or crosshair onto the RGB video output.

Table I details the resultant effect on the analog outputs of
BLANK

, SYNC and REF WHITE.

All these digital inputs are specified to accept TTL logic levels

Clock Input

The CLOCK input of the ADV101 is typically the pixel clock
rate of the system. It is also known as the dot rate. The dot rate
and hence the required CLOCK frequency, will be determined
by the on-screen resolution, according to the following equation.

Dot Rate = (Horiz Res)

(Vert Res)

(Refresh Rate)/

Dot Rate =

(Retrace Factor)

Horiz Res

= Number of pixels/line

Vert Res

= Number of lines/frame

Refresh Rate

= Horizontal Scan Rate. This is the rate at

which the screen must be refreshed, typi-
cally 60 Hz for a noninterlaced system or
30 Hz for an interlaced system.

Retrace Factor

= Total blank time factor. This takes into ac-

count that the display is blanked for a certain
fraction of the total duration of each frame
(e.g., 0.8).

CLOCK

DATA

ANALOG OUTPUTS

(IOR, IOG, IOB, I )

SYNC

DIGITAL INPUTS

(R0R7, G0G7, B0B7;

SYNC, BLANK,

REFWHITE)

Figure 2. Video Data Input/Output

ADV101

REV. B

If we, therefore, have a graphics system with a 1024

1024

resolution, a noninterlaced 60 Hz refresh rate and a retrace fac-
tor of 0.8, then:

Dot Rate

= 1024

1024

60/0.8

Dot Rate

= 78.6 MHz

Video Synchronization and Control

The ADV101 has a single composite video sync (SYNC) input
control. Many graphics processors and CRT controllers have
the ability of generating horizontal sync (HSYNC), vertical sync
(VSYNC) and composite SYNC.

In a graphics system which does not automatically generate a
composite SYNC signal, the inclusion of some additional logic
circuitry will enable the generation of a composite SYNC signal.

The I

SYNC

current output is typically connected directly to the

IOG output, thus encoding video synchronization information
onto the green video channel. If it is not required to encode sync
information onto the ADV101, the SYNC input should be tied
to logic low and I

SYNC

should be connected to analog GND.

Reference Input

An external 1.23 V voltage reference is required to drive the
ADV101. The AD589 from Analog Devices is an ideal choice of
reference. It is a two-terminal, low cost, temperature compen-
sated bandgap voltage reference which provides a fixed 1.23 V
output voltage for input currents between 50

A and 5 mA. Fig-

ure 4 shows a typical reference circuit connection diagram. The
voltage reference gets its current drive from the ADV101's V

through an external 1 k

resistor to the V

REF

pin. A 0.1

F ce-

ramic capacitor is required between the COMP and V

. This is

necessary so as to provide compensation for the internal refer-
ence amplifier.

The required CLOCK frequency is thus 78.6 MHz.

All video data and control inputs are latched into the ADV101
on the rising edge of CLOCK, as previously described in the
"Digital Inputs" section. It is recommended that the CLOCK
input to the ADV101 be driven by a TTL buffer (e.g., 74F244).

Table I. Video Output Truth Table

IOG

IOR, IOB

REF

DAC

Description

(mA)

WHITE

SYNC

BLANK

Input Data

WHITE LEVEL

26.67

19.05

xxH

WHITE LEVEL

26.67

19.05

FFH

VIDEO

video + 9.05

video + 1.44

data

VIDEO to BLANK

video + 1.44

data

BLACK LEVEL

9.05

1.44

00H

BLACK to BLANK

1.44

00H

BLANK LEVEL

7.62

xxH

SYNC LEVEL

xxH

NOTE

Typical with full-scale IOG = 26.67 mA. V

REF

= 1.235 V, R

SET

= 560

, I

SYNC

connected to IOG.

92.5 IRE

7.5 IRE

40 IRE

WHITE LEVEL

BLACK LEVEL

BLANK LEVEL

SYNC LEVEL

19.05 0.714 26.67 1.000

1.44 0.054 9.05 0.340

0 0 7.62 0.286

mA V mA V

RED, BLUE GREEN

NOTES

1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75

LOAD.

2. V = 1.235V, R = 560

, I CONNECTED TO IOG.

REF

SET

SYNC

3. RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.

Figure 3. RGB Video Output Waveform

ADV101

REV. B

A resistance R

SET

connected between FS ADJUST and GND

determines the amplitude of the output video level according to
the following equations:

IOG (mA) = 12,082

REF

(V)/R

SET

(

) (1)

IOR, IOB (mA) = 8,628

REF

(V)/R

SET

(

) (2)

If SYNC is not being encoded onto the green channel, then
Equation 1 will be similar to Equation 2.

Using a variable value of R

SET

, as shown in Figure 4, allows for

accurate adjustment of the analog output video levels. Use of a
fixed 560

SET

resistor yields the analog output levels as

quoted in the specification page. These values also correspond
to the RS-343A video waveform values as shown in Figure 3.

TO DACs

ADV101*

REF

GND

FS ADJUST

SET

560

500

100

*ADDITIONAL CIRCUITRY, INCLUDING
DECOUPLING COMPONENTS,
EXCLUDED FOR CLARITY

ANALOG POWER PLANE

COMP

0.1

AD589

(1.235V
VOLTAGE
REFERENCE)

4mA

REF

Figure 4. Reference Circuit

D/A Converters

The ADV101 contains three matched 8-bit D/A converters. The
DACs are designed using an advanced, high speed, segmented
architecture. The bit currents corresponding to each digital in-
put are routed to either the analog output (bit = "1") or GND
(bit = "0") by a sophisticated decoding scheme. As all this cir-
cuitry is on one monolithic device, matching between the three
DACs is optimized. As well as matching, the use of identical
current sources in a monolithic design guarantees monotonicity
and low glitch. The onboard operational amplifier stabilizes the
full-scale output current against temperature and power supply
variations.

Analog Outputs

The ADV101 has three analog outputs, corresponding to the
red, green and blue video signals. A fourth analog output
(I

SYNC

) can be used if it is required to encode video synchroni-

zation information onto the green signal. In this case, I

SYNC

connected to IOG. (See "Video Synchronization and Control"
section.)

The red, green and blue analog outputs of the ADV101 are high
impedance current sources. Each one of these three RGB cur-
rent outputs is capable of directly driving a 37.5

load, such as

a doubly terminated 75

coaxial cable. Figure 5a shows the

DACs

IOR, IOG, IOB

Z = 75

(CABLE)

Z = 75

(SOURCE

TERMINATION)

Z = 75

(MONITOR)

TERMINATION REPEATED THREE TIMES
FOR RED, GREEN AND BLUE DACs

Figure 5a. Analog Output Termination for RS-343A

DACs

IOR, IOG, IOB

Z = 75

(CABLE)

Z = 150

(SOURCE

TERMINATION)

Z = 75

(MONITOR)

TERMINATION REPEATED THREE TIMES
FOR RED, GREEN AND BLUE DACs

Figure 5b. Analog Output Termination for RS-170

required configuration for each of the three RGB outputs con-
nected into a doubly terminated 75

load. This arrangement

will develop RS-343A video output voltage levels across a 75

monitor.

A suggested method of driving RS-170 video levels into a 75

monitor is shown in Figure 5b. The output current levels of the
DACs remain unchanged, but the source termination resistance,
Z

, on each of the three DACs is increased from 75

to 150

More detailed information regarding load terminations for vari-
ous output configurations, including RS-343A and RS-170, is
available in an application note entitled "Video Formats &
Required Load Terminations" available from Analog Devices,
publication number E1228-15-1/89.

Figure 3 shows the video waveforms associated with the three
RGB outputs driving the doubly terminated 75

load of Figure

5a. As well as the gray scale levels, black level to white level, the
diagram also shows the contributions of SYNC and BLANK.
These control inputs add appropriately weighted currents to the
analog outputs, producing the specific output level requirements
for video applications. Table I details how the SYNC and
BLANK

inputs modify the output levels.

Gray Scale Operation

The ADV101 can be used for stand-alone, gray scale (mono-
chrome) or composite video applications (i.e., only one channel
used for video information). Any one of the three channels, red,
green or blue can be used to input the digital video data. The
two unused video data channels should be tied to logical zero.

ADV101

REV. B

The unused analog outputs should be terminated with the same
load as that for the used channel. In other words, if the red
channel is used and IOR is terminated with a doubly termi-
nated 75

load (37.5

), IOB and IOG should be terminated

with 37.5

resistors. (See Figure 6.)

GND

ADV101

VIDEO

INPUT

DOUBLY
TERMINATED
75

LOAD

IOR

IOG

IOB

37.5

Figure 6. Input and Output Connections for Stand-Alone
Gray Scale or Composite Video

Video Output Buffers

The ADV101 is specified to drive transmission line loads, which
is what most monitors are rated as. The analog output configu-
rations to drive such loads are described in the Analog Interface
section and illustrated in Figure 5. However, in some applica-
tions it may be required to drive long "transmission line" cable
lengths. Cable lengths greater than 10 meters can attenuate and
distort high frequency analog output pulses. The inclusion of
output buffers will compensate for some cable distortion. Buff-
ers with large full power bandwidths and gains between 2 and 4
will be required. These buffers will also need to be able to sup-
ply sufficient current over the complete output voltage swing.
Analog Devices produces a range of suitable op amps for such
applications. These include the AD84X series of monolithic op
amps. In very high frequency applications (80 MHz), the
AD9617 is recommended. More information on line driver buff-
ering circuits is given in the relevant op amp data sheets.

Use of buffer amplifiers also allows implementation of other
video standards besides RS-343A and RS-170. Altering the gain
components of the buffer circuit will result in any desired video
level.

DACs

Z = 75

(CABLE)

Z = 75

(SOURCE

TERMINATION)

AD848

0.1

IOR, IOG, IOB

Z = 75

(MONITOR)

GAIN (G) = 1 +

Figure 7. AD848 As an Output Buffer

ADV101

REV. B

PC BOARD LAYOUT CONSIDERATIONS

The ADV101 is optimally designed for lowest noise perfor-
mance, both radiated and conducted noise. To complement the
excellent noise performance of the ADV101, it is imperative
that great care be given to the PC board layout. Figure 8 shows
a recommended connection diagram for the ADV101.

The layout should be optimized for lowest noise on the
ADV101 power and ground lines. This can be achieved by
shielding the digital inputs and providing good decoupling. The
lead length between groups of V

and GND pins should by

minimized so as to minimize inductive ringing.

Ground Planes

The ADV101, and associated analog circuitry, should have a
separate ground plane referred to as the analog ground plane.
This ground plane should connect to the regular PCB ground
plane at a single point through a ferrite bead, as illustrated in
Figure 8. This bead should be located as close as possible
(within 3 inches) to the ADV101.

The analog ground plane should encompass all ADV101
ground pins, voltage reference circuitry, power supply bypass
circuitry, the analog output traces and any output amplifiers.

The regular PCB ground plane area should encompass all the
digital signal traces, excluding the ground pins, leading up to
the ADV101.

GND

FS ADJUST

IOR

IOG

IOB

GROUND

ADV101

C5
0.1

Z1 (AD589)

C1
33

C2
10

COMP

C6
0.1

ANALOG POWER PLANE

REF

L2 (FERRITE BEAD)

CLOCK

REF WHITE

SYNC

BLANK

RGB
VIDEO
OUTPUT

VIDEO

DATA

INPUTS

VIDEO

CONTROL

INPUTS

ANALOG GROUND PLANE

SET

560

L1 (FERRITE BEAD)

C4
0.1

C3
0.1

5V (V

)

R4
1k

SYNC

DESCRIPTION
33

F TANTALUM CAPACITOR

0.1

F CERAMIC CAPACITOR

FERRITE BEAD
75

1% METAL FILM RESISTOR

560

1% METAL FILM RESISTOR

1.235V VOLTAGE REFERENCE

VENDOR PART NUMBER

FAIR-RITE 27430011 OR MURATA BL01/02/03
DALE CMF-55C
DALE CMF-55C
DALE CMF-55C
ANALOG DEVICES AD589JH

COMPONENT

C1
C2

C3, C4, C5, C6

L1, L2

R1, R2, R3

SET

Figure 8. Typical Connection Diagram and Component List

ADV101

REV. B

Power Planes

The PC board layout should have two distinct power planes,
one for analog circuitry and one for digital circuitry. The analog
power plane should encompass the ADV101 (V

) and all asso-

ciated analog circuitry. This power plane should be connected
to the regular PCB power plane (V

) at a single point through

a ferrite bead, as illustrated in Figure 8. This bead should be lo-
cated within three inches of the ADV101.

The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV101 power pins, voltage reference circuitry and
any output amplifiers.

The PCB power and ground planes should not overlay portions
of the analog power plane. Keeping the PCB power and ground
planes from overlaying the analog power plane will contribute to
a reduction in plane-to-plane noise coupling.

Supply Decoupling
Noise on the analog power plane can be further reduced by the
use of multiple decoupling capacitors. (See Figure 8.)

Optimum performance is achieved by the use of 0.1

F ceramic

capacitors. Each of the two groups of V

should be individually

decoupled to ground. This should be done by placing the ca-
pacitors as close as possible to the device with the capacitor
leads as short as possible, thus minimizing lead inductance.

It is important to note that while the ADV101 contains circuitry
to reject power supply noise, this rejection decreases with fre-
quency. If a high frequency switching power supply is used, the
designer should pay close attention to reducing power supply
noise. A dc power supply filter (Murata BNX002) will provide
EMI suppression between the switching power supply and the
main PCB. Alternatively, consideration could be given to using
a three-terminal voltage regulator.

Digital Signal Interconnect

The digital signal lines to the ADV101 should be isolated as
much as possible from the analog outputs and other analog cir-
cuitry. Digital signal lines should not overlay the analog power
plane.

Due to the high clock rates used, long clock lines to the
ADV101 should be avoided so as to minimize noise pickup.

Any active pull-up termination resistors for the digital inputs
should be connected to the regular PCB power plane (V

), and

not the analog power plane.

Analog Signal Interconnect

The ADV101 should be located as close as possible to the out-
put connectors thus minimizing noise pickup and reflections
due to impedance mismatch.

The video output signals should overlay the ground plane, and
not the analog power plane, thereby maximizing the high fre-
quency power supply rejection.

For optimum performance, the analog outputs should each have
a source termination resistance to ground of 75

(doubly

terminated 75

configuration). This termination resistance

should be as close as possible to the ADV101 so as to minimize
reflections.

Additional information on PCB design is available in an applica-
tion note entitled "Design and Layout of a Video Graphics Sys-
tem for Reduced EMI." This application note is available from
Analog Devices, publication number E13091510/89.

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