REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
DAC8412/DAC8413
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2000
Quad, 12-Bit DAC
Voltage Output with Readback
FUNCTIONAL BLOCK DIAGRAM
V
REFH
V
OUTA
V
DD
V
OUTB
V
OUTC
V
OUTD
V
REFL
V
SS
V
LOGIC
DGND
DATA
I/O
A0
A1
R/
W
CS
RESET
LDAC
12
I/O
PORT
CONTROL
LOGIC
INPUT
REG
A
OUTPUT
REG
A
DAC
A
INPUT
REG
B
INPUT
REG
D
INPUT
REG
C
OUTPUT
REG
B
OUTPUT
REG
C
OUTPUT
REG
D
DAC
B
DAC
C
DAC
D
FEATURES
+5 V to 15 V Operation
Unipolar or Bipolar Operation
True Voltage Output
Double-Buffered Inputs
Reset to Min (DAC8413) or Center Scale (DAC8412)
Fast Bus Access Time
Readback
APPLICATIONS
Automatic Test Equipment
Digitally Controlled Calibration
Servo Controls
Process Control Equipment
GENERAL DESCRIPTION
The DAC8412 and DAC8413 are quad, 12-bit voltage output
DACs with readback capability. Built using a complementary
BiCMOS process, these monolithic DACs offer the user very
high package density.
Output voltage swing is set by the two reference inputs V
REFH
and V
REFL
. By setting the V
REFL
input to 0 V and V
REFH
to a
positive voltage, the DAC will provide a unipolar positive output
range. A similar configuration with V
REFH
at 0 V and V
REFL
at
a negative voltage will provide a unipolar negative output range.
Bipolar outputs are configured by connecting both V
REFH
and
V
REFL
to nonzero voltages. This method of setting output voltage
range has advantages over other bipolar offsetting methods because
it is not dependent on internal and external resistors with different
temperature coefficients.
Digital controls allow the user to load or read back data from any
DAC, load any DAC and transfer data to all DACs at one time.
An active low
RESET loads all DAC output registers to mid-
scale for the DAC8412 and zero scale for the DAC8413.
The DAC8412/DAC8413 are available in 28-lead plastic DIP,
PLCC and LCC packages. They can be operated from a wide
variety of supply and reference voltages with supplies ranging
from single +5 V to
15 V, and references from +2.5 V to 10 V.
Power dissipation is less than 330 mW with
15 V supplies and
only 60 mW with a +5 V supply.
For MIL-STD-883 applications, contact your local ADI sales
office for the DAC8412/DAC8413/883 data sheet which specifies
operation over the 55
C to +125C temperature range. All
883 parts are also available on Standard Military Drawings
5962-91 76401MXA through 76404M3A.
DIGITAL INPUT CODE Decimal
0.500
0.125
0
4096
512
LINEARITY ERROR LSB
1024
1536
2046
2548
2560
3072
0.375
0.125
0.250
0.375
0.500
0.250
0
V
DD
= +15V
V
SS
= 15V
V
REFH
= +10V
V
REFL
= 10V
T
A
= 55 C, +25 C, +125 C
+125 C
55 C
+25 C
Figure 1. INL vs. Code Over Temperature
2
REV. D
DAC8412/DAC8413SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Integral Nonlinearity Error
INL
E Grade
0.25
0.5
LSB
INL
F Grade
1
LSB
Differential Nonlinearity Error
DNL
Monotonic Over Temperature
1
LSB
Min-Scale Error
V
ZSE
R
L
= 2 k
2
LSB
Full-Scale Error
V
FSE
R
L
= 2 k
2
LSB
Min-Scale Tempco
TCV
ZSE
R
L
= 2 k
15
ppm/
C
Full-Scale Tempco
TCV
FSE
R
L
= 2 k
20
ppm/
C
Linearity Matching
Adjacent DAC Matching
1
LSB
REFERENCE
Positive Reference Input Voltage Range
Note 2
V
REFL
+ 2.5
V
DD
2.5
V
Negative Reference Input Voltage Range
Note 2
10
V
REFH
2.5 V
Reference High Input Current
I
REFH
2.75
+1.5
+2.75
mA
Reference Low Input Current
I
REFL
0
+2
+2.75
mA
Large Signal Bandwidth
BW
3 dB, V
REFH
= 0 V to +10 V p-p
160
kHz
AMPLIFIER CHARACTERISTICS
Output Current
I
OUT
R
L
= 2 k
, C
L
= 100 pF
5
+5
mA
Settling Time
t
S
to 0.01%, 10 V Step, R
L
= 1 k
10
s
Slew Rate
SR
10% to 90%
2.2
V/
s
Analog Crosstalk
72
dB
LOGIC CHARACTERISTICS
Logic Input High Voltage
V
INH
T
A
= +25
C
2.4
V
Logic Input Low Voltage
V
INL
T
A
= +25
C
0.8
V
Logic Output High Voltage
V
OH
I
OH
= +0.4 mA
2.4
V
Logic Output Low Voltage
V
OL
I
OL
= 1.6 mA
0.4
V
Logic Input Current
I
IN
1
A
Input Capacitance
C
IN
8
pF
Digital Feedthrough
3
V
REFH
= +2.5 V, V
REFL
= 0 V
5
nV-s
LOGIC TIMING CHARACTERISTICS
3
Note 4
Chip Select Write Pulsewidth
t
WCS
80
ns
Write Setup
t
WS
t
WCS
= 80 ns
0
ns
Write Hold
t
WH
t
WCS
= 80 ns
0
ns
Address Setup
t
AS
0
ns
Address Hold
t
AH
0
ns
Load Setup
t
LS
70
ns
Load Hold
t
LH
30
ns
Write Data Setup
t
WDS
t
WCS
= 80 ns
20
ns
Write Data Hold
t
WDH
t
WCS
= 80 ns
0
ns
Load Data Pulsewidth
t
LDW
170
ns
Reset Pulsewidth
t
RESET
140
ns
Chip Select Read Pulsewidth
t
RCS
130
ns
Read Data Hold
t
RDH
t
RCS
= 130 ns
0
ns
Read Data Setup
t
RDS
t
RCS
= 130 ns
0
ns
Data to Hi Z
t
DZ
C
L
= 10 pF
200
ns
Chip Select to Data
t
CSD
C
L
= 100 pF
160
ns
SUPPLY CHARACTERISTICS
Power Supply Sensitivity
PSS
14.25 V
V
DD
15.75 V
150
ppm/V
Positive Supply Current
I
DD
V
REFH
= +2.5 V
8.5
12
mA
Negative Supply Current
I
SS
10
6.5
mA
Power Dissipation
P
DISS
330
mW
NOTES
1
All supplies can be varied
5%, and operation is guaranteed. Device is tested with nominal supplies.
2
Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
3
All parameters are guaranteed by design.
4
All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
Specifications subject to change without notice.
(@ V
DD
= +15.0 V, V
SS
= 15.0 V, V
LOGIC
= +5.0 V, V
REFH
= +10.0 V, V
REFL
= 10.0 V,
40 C
T
A
+85 C unless otherwise noted. See Note 1 for supply variations.)
3
REV. D
DAC8412/DAC8413
(@ V
DD
= V
LOGIC
= +5.0 V 5%, V
SS
= 0.0 V, V
REFH
= +2.5 V, V
REFL
= 0.0 V, and V
SS
= 5.0 V 5%,
V
REFL
= 2.5 V, 40 C
T
A
+85 C unless otherwise noted. See Note 1 for supply variations.)
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Integral Nonlinearity Error
INL
E Grade
1/2
1
LSB
INL
F Grade
2
LSB
INL
V
SS
= 0.0 V; E Grade
2
2
LSB
INL
V
SS
= 0.0 V; F Grade
2
4
LSB
Differential Nonlinearity Error
DNL
Monotonic Over Temperature
1
LSB
Min-Scale Error
V
ZSE
V
SS
= 5.0 V
4
LSB
Full-Scale Error
V
FSE
V
SS
= 5.0 V
4
LSB
Min-Scale Error
V
ZSE
V
SS
= 0.0 V
8
LSB
Full-Scale Error
V
FSE
V
SS
= 0.0 V
8
LSB
Min-Scale Tempco
TCV
ZSE
100
ppm/
C
Full-Scale Tempco
TCV
FSE
100
ppm/
C
Linearity Matching
Adjacent DAC Matching
1
LSB
REFERENCE
Positive Reference Input Voltage Range
Note 3
V
REFL
+ 2.5
V
DD
2.5
V
Negative Reference Input Voltage Range
V
SS
= 0.0 V
0
V
REFH
2.5 V
V
SS
= 5.0 V
2.5
V
REFH
2.5 V
Reference High Input Current
I
REFH
Code 000H
1.0
+1.0
mA
Large Signal Bandwidth
BW
3 dB, V
REFH
= 0 V to 2.5 V p-p
450
kHz
AMPLIFIER CHARACTERISTICS
Output Current
I
OUT
R
L
= 2 k
, C
L
= 100 pF
1.25
+1.25
mA
Settling Time
t
S
to 0.01%, 2.5 V Step, R
L
= 1 k
7
s
Slew Rate
SR
10% to 90%
2.2
V/
s
LOGIC CHARACTERISTICS
Logic Input High Voltage
V
INH
T
A
= +25
C
2.4
V
Logic Input Low Voltage
V
INL
T
A
= +25
C
0.8
V
Logic Output High Voltage
V
OH
I
OH
= +0.4 mA
2.4
V
Logic Output Low Voltage
V
OL
I
OL
= 1.6 mA
0.45
V
Logic Input Current
I
IN
1
A
Input Capacitance
C
IN
8
pF
LOGIC TIMING CHARACTERISTICS
4
Note 5
Chip Select Write Pulsewidth
t
WCS
150
ns
Write Setup
t
WS
t
WCS
= 150 ns
0
ns
Write Hold
t
WH
t
WCS
= 150 ns
0
ns
Address Setup
t
AS
0
ns
Address Hold
t
AH
0
ns
Load Setup
t
LS
70
ns
Load Hold
t
LH
50
ns
Write Data Setup
t
WDS
t
WCS
= 150 ns
20
ns
Write Data Hold
t
WDH
t
WCS
= 150 ns
0
ns
Load Data Pulsewidth
t
LDW
180
ns
Reset Pulsewidth
t
RESET
150
ns
Chip Select Read Pulsewidth
t
RCS
170
ns
Read Data Hold
t
RDH
t
RCS
= 170 ns
20
ns
Read Data Setup
t
RDS
t
RCS
= 170 ns
0
ns
Data to Hi Z
t
DZ
C
L
= 10 pF
200
ns
Chip Select to Data
t
CSD
C
L
= 100 pF
320
ns
SUPPLY CHARACTERISTICS
Power Supply Sensitivity
PSS
100
ppm/V
Positive Supply Current
I
DD
7
12
mA
Negative Supply Current
I
SS
V
SS
= 5.0 V
10
mA
Power Dissipation
P
DISS
V
SS
= 0 V
60
mW
V
SS
= 5 V
110
mW
NOTES
1
All supplies can be varied
5%, and operation is guaranteed. Device is tested with V
DD
= +4.75 V.
2
For single supply operation only (V
REFL
= 0.0 V, V
SS
= 0.0 V): Due to internal offset errors, INL and DNL are measured beginning at code 2 (002
H
).
3
Operation
is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
4
All parameters are guaranteed by design.
5
All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
Specifications subject to change without notice.
DAC8412/DAC8413
4
REV. D
CS
R/
W
A0/A1
DATA
OUT
DATA
VALID
t
DZ
HI-Z
HI
-Z
t
RCS
t
RDS
t
RDH
t
AS
t
AH
t
CSD
Figure 2. Data Output (Read Timing)
CS
R/
W
A0/A1
DATA
IN
t
WCS
RESET
t
WS
t
WH
t
AH
t
AS
t
LS
t
WDS
t
WDH
t
LDW
t
RESET
LDAC
t
LH
Figure 3. Data WRITE (Input and Output Registers) Timing
CS
R/
W
ADDRESS
LDAC
DATA
IN
80ns
t
WS
t
AS
t
LS
t
WDS
DATA1
VALID
DATA2
VALID
DATA3
VALID
DATA4
VALID
t
WDH
t
LH
t
WH
ADDRESS
ONE
ADDRESS
TWO
ADDRESS
THREE
ADDRESS
FOUR
Figure 4. Single Buffer Mode
CS
R/
W
ADDRESS
LDAC
DATA
IN
80ns
t
WS
t
AS
t
LS
t
WDS
DATA1
VALID
DATA2
VALID
DATA3
VALID
DATA4
VALID
t
WDH
t
LH
t
WH
ADDRESS
ONE
ADDRESS
TWO
ADDRESS
THREE
ADDRESS
FOUR
t
LDW
Figure 5. Double Buffer Mode
C1
C1
D1
C2
C1
D1
D1
R2
R1
R2
N/C
N/C C2
C2
R3
R3
N/C
N/C
C2
V
DD
V
REFH
V
REFL
+
+
+
R4
R4
R6
R1
DGND
V
SS
D1
C1
+
V
REFH
V
OUTB
V
OUTA
V
SS
DGND
RESET
LDAC
V
REFL
V
OUTC
V
OUTD
V
DD
V
LOGIC
CS
A0
A1
R/
W
DB11
DB10
DB9
DB8
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
*
V
DD
=
+15V,
V
SS
=
15V,
V
REFH
=
+10V,
V
REFL
=
0V
R1
=
10 ,
R2
=
100 ,
R3
=
5k ,
R4
= 10k , R5 = 100k ,
R6 = 47 FOR LCC, R6 = 100 FOR DIP
C1 = 4.7 F (ONCE PER PORT), C2 = 0.01 F (EACH DEVICE)
D1 = 1N4001 OR EQUIVALENT (ONCE PER PORT)
ONCE
PER
PORT
R5
R3
Figure 6. Burn-In Diagram
DAC8412/DAC8413
5
REV. D
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
(
T
A
= +25
C unless otherwise noted)
V
SS
to V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, +33.0 V
V
SS
to V
LOGIC
. . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, +33.0 V
V
LOGIC
to DGND . . . . . . . . . . . . . . . . . . . . . . 0.3 V, +7.0 V
V
SS
to V
REFL
. . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, +V
SS
2.0 V
V
REFH
to V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . +2.0 V, +33.0 V
V
REFH
to V
REFL
. . . . . . . . . . . . . . . . . . . . . . . . +2.0 V, V
SS
V
DD
Current into Any Pin 4 . . . . . . . . . . . . . . . . . . . . . . . .
15 mA
Digital Input Voltage to DGND . . . . . 0.3 V, V
LOGIC
+0.3 V
Digital Output Voltage to DGND . . . . . . . . . . 0.3 V, +7.0 V
Operating Temperature Range
ET, FT, EP, FP, FPC . . . . . . . . . . . . . . . . 40
C to +85C
AT, BT, BTC . . . . . . . . . . . . . . . . . . . . . 55
C to +125C
Dice Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150
C
Storage Temperature . . . . . . . . . . . . . . . . . . 65
C to +150C
Power Dissipation Package . . . . . . . . . . . . . . . . . . . 1000 mW
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300
C
CAUTION
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only; functional operation at or above this specification is not implied.
Exposure to the above maximum rating conditions for extended periods may affect
device reliability.
2. Digital inputs and outputs are protected, however, permanent damage may occur on unprotected units
from high-energy electrostatic fields. Keep units in conductive foam or packaging at all times until
ready to use. Use proper antistatic handling procedures.
3. Remove power before inserting or removing units from their sockets.
4. Analog outputs are protected from short circuit to ground or either supply.
Thermal Resistance
Package Type
JA
*
JC
Units
28-Lead Plastic DIP (P)
48
22
C/W
28-Lead Hermetic Leadless Chip Carrier (TC) 70
28
C/W
28-Lead Plastic Leaded Chip Carrier (PC)
63
25
C/W
*
JA
is specified for worst-case mounting conditions, i. e.,
JA
is specified for device
in socket.
ORDERING INFORMATION
1, 2
INL
Military
3
Temperature
Extended Industrial
3
Temperature
Package
Package
(LSB)
55 C to +125 C
40 C to +85 C
Description
Option
1
DAC8412FPC
PLCC
P-28A
1.5
DAC8412BTC/883
LCC
E-28A
0.5
DAC8412EP
Plastic DIP
N-28
1
DAC8412FP
Plastic DIP
N-28
1
DAC8413FPC
PLCC
P-28A
1.5
DAC8413BTC/883
LCC
E-28A
0.5
DAC8413EP
Plastic DIP
N-28
1
DAC8413FP
Plastic DIP
N-28
NOTES
1
Die Size 0.225
0.165 inches, 37,125 sq. mils (5.715 4.191 mm, 23.95 sq. mm). Substrate should be connected to V
DD
; Transistor Count = 2595.
2
Burn-in is available on extended industrial temperature range parts in cerdip.
3
A complete /883 data sheet is available. For availability and burn-in information, contact your local sales office.
DAC8412/DAC8413
6
REV. D
PIN CONFIGURATIONS
Plastic DIP
V
REFH
V
OUTB
V
OUTA
V
SS
DGND
RESET
LDAC
DB0
(LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB10
DB9
DB8
DB7
DB11
(MSB)
R/
W
A1
A0
CS
V
LOGIC
V
DD
V
OUTD
V
OUTC
V
REFL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DAC8412
DAC8413
TOP VIEW
(NOT TO SCALE)
PLCC
5
6
7
8
9
10
11
DGND
RESET
LDAC
DB0
(LSB)
DB1
DB2
DB3
25
24
23
22
21
20
19
V
DD
V
LOGIC
CS
A0
A1
R/
W
DB11
(MSB)
4
3
2
1
28 27 26
V
SS
V
OUTA
V
OUTB
V
REFH
V
REFL
V
OUTC
V
OUTD
12 13 14 15 16 17
18
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DAC8412PC
DAC8413PC
TOP
VIEW
(NOT
TO
SCALE)
LCC
5
6
7
8
9
10
11
25
24
23
22
21
20
19
4
3
2
1
28 27 26
V
DD
V
LOGIC
CS
A0
A1
R/
W
DB11
(MSB)
DGND
RESET
LDAC
DB0
(LSB)
DB1
DB2
DB3
12 13 14 15 16 17
18
DB4
DB5
DB6
DB7
DB8
DB9
DB10
V
SS
V
OUTA
V
OUTB
V
REFH
V
REFL
V
OUTC
V
OUTD
DAC8412TC
DAC8413TC
TOP
VIEW
(NOT
TO
SCALE)
PIN FUNCTION DESCRIPTIONS
Pin
Name
Description
1
V
REFH
High-Side DAC Reference Input
2
V
OUTB
DAC B Output
3
V
OUTA
DAC A Output
4
V
SS
Lower-Rail Power Supply
5
DGND
Digital Ground
6
RESET
Reset Input and Output Registers to all 0s,
Enabled at Active Low
7
LDAC
Load Data to DAC, Enabled at Active Low
8
DB0
Data Bit 0, LSB
9
DB1
Data Bit 1
10
DB2
Data Bit 2
11
DB3
Data Bit 3
12
DB4
Data Bit 4
13
DB5
Data Bit 5
14
DB6
Data Bit 6
15
DB7
Data Bit 7
16
DB8
Data Bit 8
17
DB9
Data Bit 9
18
DB10
Data Bit 10
19
DB11
Data Bit 11, MSB
20
R/
W
Active Low to Write Data to DAC. Active
High to Readback Previous Data at Data Bit
Pins with V
LOGIC
Connected to +5 V
21
A1
Address Bit 1
22
A0
Address Bit 0
23
CS
Chip Select, Enabled at Active Low
24
V
LOGIC
Voltage Supply for Readback Function. Can
be Open Circuit If Not Used
25
V
DD
Upper-Rail Power Supply
26
V
OUTD
DAC D Output
27
V
OUTC
DAC C Output
28
V
REFL
Low-Side DAC Reference Input
DAC8412/DAC8413
7
REV. D
Typical Performance Characteristics
+1
1
6
0
11
10
9
8
7
MAXIMUM LINEARITY ERROR
LSB
V
REFH
Volts
12
V
DD
=
+15V
V
SS
=
15V
V
REFL
=
10.0V
T
A
=
+25 C
Figure 7. DNL vs. V
REFH
MAXIMUM
LINEARITY
ERROR
LSB
V
REFH
Volts
+1
1
0
1
2
3
V
DD
=
+5V
V
SS
=
0V
V
REFL
=
0V
T
A
=
+25 C
Figure 10. INL vs. V
REFH
150
75
75
0
0.2
0.6
0.4
0.2
0
FULL-SCALE ERROR
LSB
TEMPERATURE C
DAC A
DAC D
DAC B
DAC C
V
DD
=
+15V
V
SS
=
15V
V
REFH
=
+10V
V
REFL
=
10V
Figure 13. Full-Scale Error vs.
Temperature
MAXIMUM
LINEARITY
ERROR
LSB
V
REFH
Volts
0
2
1
+2
+1
3
2
1
V
DD
= +5V
V
SS
= 0V
V
REFL
= 0V
T
A
= +25 C
Figure 8. DNL vs. V
REFH
FULL-SCALE ERROR
LSB
0.4
0.6
1000
0.4
0
0
0.2
0.2
600
400
800
200
T = HOURS OF OPERATION AT +125 C
X
X+3
X3
V
DD
=
+15V
V
SS
=
15V
V
REFH
=
+10V
V
REFL
=
10V
Figure 11. Full-Scale Error vs.
Time Accelerated by Burn-In
0.3
0.5
150
0.3
75
0.1
0.1
75
0
ZERO-SCALE ERROR
LSB
TEMPERATURE C
DAC A
DAC D
DAC C
DAC B
V
DD
=
+15V
V
SS
=
15V
V
REFH
=
+10V
V
REFL
=
10V
Figure 14. Zero-Scale Error vs.
Temperature
MAXIMUM LINEARITY ERROR
LSB
V
REFH
Volts
0.3
0.1
0.2
10
8
6
12
V
DD
= +15V
V
SS
= 15V
V
REFL
= 0V
T
A
= +25 C
Figure 9. INL vs. V
REFH
ZERO-SCALE ERROR
LSB
0.3
0.7
1000
0.5
0
0.1
0.3
0.1
600
400
800
200
T = HOURS OF OPERATION AT +125 C
X
X+3
V
DD
=
+15V
V
SS
=
15V
V
REFH
=
+10V
V
REFL
=
10V
X3
Figure 12. Zero-Scale Error vs.
Time Accelerated by Burn-In
DAC8412/DAC8413
8
REV. D
DIGITAL INPUT CODE Decimal
0.37500
0.08375
0
4096
512
LINEARITY ERROR
LSB
1024
1536
2048
2560
3072
3584
0.26125
0.09375
0.18750
0.23125
0.37500
0.18750
0
V
REFH
= +10V
V
REFL
= 0V
T
A
= +25 C
Figure 15. Channel-to-Channel Matching
(V
SUPPLY
=
15 V)
DIGITAL INPUT CODE Decimal
1.00
0.25
0
4096
512
LINEARITY ERROR
LSB
1024
1536
2048
2560
3072
3584
0.75
0.25
0.50
0.75
1.00
0.50
0
V
DD
= +5.0V
V
SS
= 0V
V
REFH
= +2.5V
T
A
= +25 C
Figure 16. Channel-to-Channel Matching
(V
SUPPLY
= +5 V/GND)
V
REFH
Volts
13
10
4
7
13
3
I
DD
mA
1
5
9
7
V
DD
=
+15V
V
SS
=
15V
V
REFL
=
10V
Figure 17. I
DD
vs. V
REFH
All DACs High
DIGITAL INPUT CODE Decimal
0.500
0.125
0
4096
512
LINEARITY ERROR
LSB
1024
1536
2048
2560
3072
3584
0.375
0.125
0.250
0.375
0.500
0.250
0
V
DD
= +15V
V
SS
= 15V
V
REFH
= +10V
V
REFL
= 10V
T
A
= 55 C, +25 C, +125 C
Figure 18. INL vs. Code
DIGITAL INPUT CODE Decimal
2.0
0.5
0
4095
511
I
VREFH
mA
1023
1535
2047
2559
3071
3583
1.5
0.5
1.0
0
V
DD
= +15V
V
SS
= 15V
V
REFH
= +10V
V
REFL
= 10V
T
A
= +25 C
Figure 19. I
VREFH
vs. Code
DAC8412/DAC8413
9
REV. D
1.96 s
32.5mV
+5V
INPUT
0
5mV/DIV
5
TRIG'D
17.5mV
2 s/DIV
18.04 s
V
DIV
V
DD
=
+15V
V
SS
=
15V
V
REFH
=
+10V
V
REFL
=
10V
T
A
=
+25 C
1 LSB ERROR BAND
Figure 20. Settling Time (Positive)
580ns
10V
V
DD
=
+15V
V
SS
=
15V
V
REFH
=
+10V
V
REFL
=
10V
T
A
=
+25 C
1V/
DIV
TRIG'D
0V
1 s/DIV
9.42 s
EA
Figure 23. Negative Slew Rate
10M
10
0
1M
100k
10k
1k
100
10
0
30
50
GAIN
dB
FREQUENCY Hz
V
DD
= +15V
V
SS
= 15V
V
REFH
= 0 100mV
V
REFL
= 10V
DATA BITS = +5V
200mV p-p
Figure 26. Small Signal Response
1.96 s
15.5mV
0
INPUT
5V
V
DD
=
+15V
V
SS
=
15V
V
REFH
=
+10V
V
REFL
=
10V
T
A
=
+25 C
2mV/DIV
5
TRIG'D
4.5mV
2 s/DIV
18.04 s
V
DIV
Figure 21. Settling Time (Negative)
100
0.01
10.0
1.00
0.10
0.6
1.0
INL
LSB
LOAD RESISTANCE K
V
DD
= +15V
V
SS
= 15V
V
REFH
= +10V
V
REFL
= 10V
T
A
= +25 C
0.8
0.4
0.2
0.0
0.2
Figure 24. DAC 8412 INL vs. Load
Resistance
TEMPERATURE
C
10
10
150
6
75
2
2
6
75
0
POWER SUPPLY CURRENT
mA
I
SS
I
DD
V
DD
=
+15V
V
SS
=
15V
Figure 27. Power Supply Current vs.
Temperature
580ns
10V
V
DD
=
+15V
V
SS
=
15V
V
REFH
=
+10V
V
REFL
=
10V
T
A
=
+25 C
1V/
DIV
TRIG'D
0V
1 s/DIV
9.42 s
EA
Figure 22. Positive Slew Rate
100
0.01
10.0
1.00
0.10
8
12
FULL SCALE VOLTAGE
V
LOAD RESISTANCE K
V
DD
= +15V
V
SS
= 15V
V
REFH
= +10V
V
REFL
= 10V
T
A
= +25 C
10
6
4
2
0
Figure 25. DAC 8412 Output Swing
vs. Load Resistance
100
0
1M
60
20
100
40
10
80
100k
10k
1k
FREQUENCY Hz
POWER SUPPLY REJECTION
dB
+PSRR:
V
DD
= +15V 1Vp
V
SS
= 15V
PSRR:
V
DD
= +15V
V
SS
= 15V 1V
V
REFH
= 10V
ALL DATA 0
+PSRR
PSRR
Figure 28. PSRR vs. Frequency
DAC8412/DAC8413
10
REV. D
10000
1
1000
100
10
10.0
NOISE DENSITY
V
NOISE FREQUENCY Hz
V
DD
= +15V
V
SS
= 15V
V
REFH
= +10V
V
REFL
= 10V
T
A
= +25 C
0.10
0.001
1.00
0.01
Figure 29. DAC8412 Noise
Frequency vs. Noise Density
0
0
25
20
30
25 20
0
10
10
20
30
20
15
10
5
0
5
10
15
I
OUT
mA
V
OUT
Volts
V
DD
= +15V
V
SS
= 15V
V
REFH
= +10V
V
REFL
= 10V
T
A
= +25 C
DATA = 000
H
+I
SC
I
SC
Figure 30. I
OUT
vs. V
OUT
V
DD
= +15V
V
SS
= 15V
V
REFH
= +10V
V
REFL
= 10V
T
A
= +25 C
CH1 MEAN
66.19 V
M 200 s
A CH1 12.9mV
20uV/DIV
1
Figure 31. Broadband Noise
OPERATION
Introduction
The DAC8412 and DAC8413 are quad, voltage output, 12-bit
parallel input DACs featuring a 12-bit data bus with readback
capability. The only differences between the DAC8412 and
DAC8413 are the reset functions. The DAC8412 resets to mid-
scale (code 800
H
) and the DAC8413 resets to minimum scale
(code 000
H
).
The ability to operate from a single +5 V supply is a unique fea-
ture of these DACs.
Operation of the DAC8412 and DAC8413 can be viewed by
dividing the system into three separate functional groups: the
digital I/O and logic, the digital to analog converters and the output
amplifiers.
DACs
Each DAC is a voltage switched, high impedance (R = 50 k
),
R-2R ladder configuration. Each 2R resistor is driven by a pair of
switches that connect the resistor to either V
REFH
or V
REFL
.
Glitch
Worst-case glitch occurs at the transition between half-scale
digital code 1000 0000 0000 to half-scale minus 1 LSB, 0111
1111 1111. It can be measured at about 2 V
s. (See Figure 33.)
For demanding applications such as waveform generation or
precision instrumentation control, a deglitcher circuit can be
implemented with a standard sample-and-hold circuit. (See
Figure 34.) When
CS is enabled by synchronizing the hold
period to be longer than the glitch tradition, the output voltage
can be smoothed with minimum disturbance. A quad sample-
and-hold amplifier, SMP04, has been used to illustrate the
deglitching result. (See Figure 33.)
H
S
H
S
S/H
CS
DACOUT'
DACOUT
DACOUT
DACOUT'
S/H
Figure 34. Deglitcher Circuit
I
SC
6
6
5
25
I
OUT
mA
V
OUT
Volts
V
DD
= +15V
V
SS
= 0V
V
REFH
= +10V
V
REFL
= 0V
T
A
= +25 C
DATA = 800
H
15
5
15
25
20
10
0
10
20
4
2
0
2
4
+I
SC
Figure 32. I
OUT
vs. V
OUT
4 s
1V
1V
GLITCH AT DAC OUTPUT
DEGLITCHER OUTPUT
CH2 1.86V
2
1
10 s
Figure 33. Glitch and Deglitched Results
DAC8412/DAC8413
11
REV. D
Table I. DAC8412/DAC8413 Logic Table
A1
A0
R/
W
CS
RS
LDAC
INPUT REG
OUTPUT REG
MODE
DAC
L
L
L
L
H
L
WRITE
WRITE
Transparent
A
L
H
L
L
H
L
WRITE
WRITE
Transparent
B
H
L
L
L
H
L
WRITE
WRITE
Transparent
C
H
H
L
L
H
L
WRITE
WRITE
Transparent
D
L
L
L
L
H
H
WRITE
HOLD
WRITE INPUT
A
L
H
L
L
H
H
WRITE
HOLD
WRITE INPUT
B
H
L
L
L
H
H
WRITE
HOLD
WRITE INPUT
C
H
H
L
L
H
H
WRITE
HOLD
WRITE INPUT
D
L
L
H
L
H
H
READ
HOLD
READ INPUT
A
L
H
H
L
H
H
READ
HOLD
READ INPUT
B
H
L
H
L
H
H
READ
HOLD
READ INPUT
C
H
H
H
L
H
H
READ
HOLD
READ INPUT
D
X
X
X
H
H
L
HOLD
Update all output registers
All
X
X
X
H
H
H
HOLD
HOLD
HOLD
All
X
X
X
X
L
X
*All registers reset to mid/zero-scale
All
X
X
X
H
g
X
*All registers latched to mid/zero-scale
All
*DAC8412 resets to midscale, and DAC8413 resets to zero scale. L = Logic Low; H = Logic High; X - Don't Care. Input and Output registers are transparent when
asserted.
The R/
W input, when enabled by CS, controls the writing to and
reading from the input register.
Coding
Both the DAC8412 and DAC8413 use binary coding. The out-
put voltage can be calculated by:
V
V
V
V
N
OUT
REFL
REF H
REFL
=
+
(
_
)
4096
where N is the digital code in decimal.
RESET
The
RESET function can be used either at power-up or at any
time during the DAC's operation. The
RESET function is inde-
pendent of
CS. This pin is active LOW and sets the DAC output
registers to either center code for the DAC8412, or zero code
for the DAC8413. The reset to center code is most useful when
the DAC is configured for bipolar references and an output of
zero volts after reset is desired.
Supplies
Supplies required are V
SS
, V
DD
and V
LOGIC
. The V
SS
supply can
be set between 15 V and 0 V. V
DD
is the positive supply; its op-
erating range is between +5 V and +15 V.
V
LOGIC
is the digital output supply voltage for the readback
function. It is normally connected to +5 V. This pin is a logic
reference input only. It does not supply current to the device.
If you are not using the readback function, V
LOGIC
can be left open-
circuit. While V
LOGIC
does not supply current to the DAC8412,
it does supply currents to the digital outputs when readback
is used.
Amplifiers
Unlike many voltage output DACs, the DAC8412 features buff-
ered voltage outputs. Each output is capable of both sourcing
and sinking 5 mA at
10 volts, eliminating the need for external
amplifiers when driving 500 pF or smaller capacitive load in
most applications. These amplifiers are short-circuit protected.
Reference Inputs
All four DACs share common reference high (V
REFH
) and refer-
ence low (V
REFL
) inputs. The voltages applied to these reference
inputs set the output high and low voltage limits of all four of
the DACs. Each reference input has voltage restrictions with
respect to the other reference and to the power supplies. The
V
REFL
can be set at any voltage between V
SS
and V
REFH
2.5 V,
and V
REFH
can be set to any value between +V
DD
2.5 V and
V
REFL
+ 2.5 V. Note that because of these restrictions the
DAC8412 references cannot be inverted (i.e., V
REFL
cannot be
greater than V
REFH
).
It is important to note that the DAC8412's V
REFH
input both
sinks and sources current. Also the input current of both V
REFH
and V
REFL
are code dependent. Many references have limited
current sinking capability and must be buffered with an ampli-
fier to drive V
REFH
. The V
REFL
has no such special requirements.
It is recommended that the reference inputs be bypassed with
0.2
F capacitors when operating with 10 V references. This
limits the reference bandwidth.
Digital I/O
See Table I for digital control logic truth table. Digital I/O consists
of a 12-bit bidirectional data bus, two registers select inputs, A0
and A1, a R/
W input, a RESET input, a Chip Select (CS), and
a Load DAC (
LDAC) input. Control of the DACs and bus
direction is determined by these inputs as shown in Table I.
Digital data bits are labeled with the MSB defined as data bit
"11" and the LSB as data bit "0." All digital pins are TTL/
CMOS compatible.
See Figure 35 for a simplified I/O logic diagram. The register
select inputs A0 and A1 select individual DAC registers "A"
(binary code 00) through "D" (binary code 11). Decoding of
the registers is enabled by the
CS input. When CS is high no
decoding takes place, and neither the writing nor the reading of
the input registers is enabled. The loading of the second bank of
registers is controlled by the asynchronous
LDAC input. By tak-
ing
LDAC low while CS is enabled, all output registers can be
updated simultaneously. Note that the t
LDW
required pulsewidth
for updating all DACs is a minimum of 170 ns.
DAC8412/DAC8413
12
REV. D
Careful attention to grounding is important to accurate opera-
tion of the DAC8412. This is not because the DAC8412 is
more sensitive than other 12-bit DACs, but because with four
outputs and two references there is greater potential for ground
loops. Since the DAC8412 has no analog ground, the ground
must be specified with respect to the reference.
Reference Configurations
Output voltage ranges can be configured as either unipolar or
bipolar, and within these choices a wide variety of options exists.
The unipolar configuration can be either positive or negative
voltage output, and the bipolar configuration can be either sym-
metrical or nonsymmetrical.
OP-400
REF10
+15V
INPUT
OUTPUT
TRIM
10k
V
REFH
0.2 F
V
REFL
+10V OPERATION
+
+15V
DAC8412
OR
DAC8413
V
SS
0.1 F
//10 F
OP400
V
DD
15V
Figure 36. Unipolar +10 V Operation
DAC A
DAC B
DAC C
DAC D
OUTPUT
REGISTER
WRDB0
WRDB1
WRDB2
WRDB3
WRDB4
WRDB5
WRDB6
WRDB7
WRDB8
WRDB9
WRDB10
RDDACB
INPUT
REGISTER
RDDACA
WRDACA
WRDACB
RDDACC
WRDACC
RDDACD
WRDACD
WRDB11
READBACKDATAIN_DB10
READOUT
READOUTBAR
READBACKDATAIN_DB11
READBACK
DATAOUT_DB11
V
LOGIC
DB11..DB0
R/
W
A1
A0
CS
V
REFH
V
DD
V
SS
V
OUTA
V
OUTB
V
OUTC
V
OUTD
V
REFL
LDAC
RESET
DGND
Figure 35. Simplified I/O Logic Diagram
+15V
1 F
0.2 F
AD688
FOR 10V
AD588
FOR 5V
39k
6.2
6.2
BALANCE
100k
GAIN
100k
0.2 F
0.1 F
//10 F
DAC8412
OR
DAC8413
V
REFH
V
REFL
V
DD
V
SS
+15V
15V
5 OR 10V OPERATION
Figure 37. Symmetrical Bipolar Operation
Figure 37 (Symmetrical Bipolar Operation) shows the DAC8412
configured for
10 V operation. Note: See the AD688 data
sheet for a full explanation of reference operation. Adjustments may
not be required for many applications since the AD688 is a very
high accuracy reference. However if additional adjustments are
required, adjust the DAC8412 full scale first. Begin by loading
the digital full-scale code (FFF
H
), and then adjust the Gain
Adjust potentiometer to attain a DAC output voltage of 9.9976 V.
Then, adjust the Balance Adjust to set the center scale output
voltage to 0.000 V.
DAC8412/DAC8413
13
REV. D
The 0.2
F bypass capacitors shown at the reference inputs
in Figure 37 should be used whenever
10 V references are
used. Applications with single references or references to
5 V
may not require the 0.2
F bypassing. The 6.2 resistor in series
with the output of the reference amplifier is to keep the amplifier
from oscillating with the capacitive load. We have found that this is
large enough to stabilize this circuit. Larger resistor values are
acceptable, provided that the drop across the resistor doesn't
exceed a V
BE
. Assuming a minimum V
BE
of 0.6 V and a maxi-
mum current of 2.75 mA, then the resistor should be under
200
for the loading of a single DAC8412.
Using two separate references is not recommended. Having two
references could cause different drifts with time and tempera-
ture; whereas with a single reference, most drifts will track.
Unipolar positive full-scale operation can usually be set with a
reference with the correct output voltage. This is preferable to
using a reference and dividing down to the required value. For a
10 V full-scale output, the circuit can be configured as shown
in Figure 38. In this configuration the full-scale value is set first
by adjusting the 10 k
resistor for a full-scale output of 9.9976 V.
0.1 F
//10 F
V
REFH
V
REFL
V
DD
V
SS
DAC8412
OR
DAC8413
10k
0.2 F
0.01 F
10 F
15V
GND
TRIM
OUTPUT
ZERO
TO
10V
OPERATION
REF08
Figure 38. Unipolar 10 V Operation
Figure 38 shows the DAC8412 configured for 10 V to 0 V
operation. A REF08 with a 10 V output is connected directly
to V
REFL
for the reference voltage.
Single +5 V Supply Operation
For operation with a +5 V supply, the reference voltage should be
set between 1.0 V and +2.5 V for optimum linearity. Figure
39 shows a REF43 used to supply a +2.5 V reference voltage.
The headroom of the reference and DAC are both sufficient to
support a +5 V supply with
5% tolerance. V
DD
and V
LOGIC
should be connected to the same supply. Separate bypassing
to each pin should also be used.
+5V
10 F
0.1 F
//10 F
0.01 F
10k
INPUT
OUTPUT
GND
TRIM
V
REFH
V
REFL
0.2 F
ZERO
TO
+2.5V
OPERATION
SINGLE
+5V
SUPPLY
REF43
DAC8412
OR
DAC8413
V
DD
V
SS
Figure 39. +5 V Single Supply Operation
DAC8412/DAC8413
14
REV. D
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Position Leadless Chip Carrier
(TC Suffix)
TOP
VIEW
0.458 (11.63)
0.442 (11.23)
SQ
1
28
5
11
18
BOTTOM
VIEW
19
25
26
4
12
0.028 (0.71)
0.022 (0.56)
45 TYP
0.015 (0.38)
MIN
0.055 (1.40)
0.045 (1.14)
0.050
(1.27)
BSC
0.075
(1.91)
REF
0.011 (0.28)
0.007 (0.18)
R TYP
0.095 (2.41)
0.075 (1.90)
0.150
(3.51)
BSC
0.300 (7.62)
BSC
0.200
(5.08)
BSC
0.075
(1.91)
REF
0.458
(11.63)
MAX
SQ
0.100 (2.54)
0.064 (1.63)
0.088 (2.24)
0.054 (1.37)
28-Lead PLCC (P-28A)
(PC Suffix)
4
PIN 1
IDENTIFIER
5
26
25
11
12
19
18
TOP VIEW
(PINS DOWN)
0.495 (12.57)
0.485 (12.32)
SQ
0.456 (11.58)
0.450 (11.43)
SQ
0.048 (1.21)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
0.020
(0.50)
R
0.050
(1.27)
BSC
0.021 (0.53)
0.013 (0.33)
0.430 (10.92)
0.390 (9.91)
0.032 (0.81)
0.026 (0.66)
0.180 (4.57)
0.165 (4.19)
0.040 (1.01)
0.025 (0.64)
0.056 (1.42)
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
0.110 (2.79)
0.085 (2.16)
28-Lead Epoxy DIP (N-28)
(P Suffix)
0.195 (4.95)
0.125 (3.18)
0.015 (0.381)
0.008 (0.204)
0.625 (15.87)
0.600 (15.24)
28
1
14
15
PIN 1
0.580 (14.73)
0.485 (12.32)
1.565 (39.70)
1.380 (35.10)
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
0.250
(6.35)
MAX
0.022 (0.558)
0.014 (0.356)
0.200 (5.05)
0.125 (3.18)
0.150
(3.81)
MIN
0.100
(2.54)
BSC
0.070
(1.77)
MAX
C1544a23/00 (rev. D)
PRINTED IN U.S.A.
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