ChipFind - документация

Электронный компонент: EVAL-AD7450CB

Скачать:  PDF   ZIP

Document Outline

REV. PrJ 27/02/02
Preliminary Technical Data
PRELIMINARY TECHNICAL DATA
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD7450
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2002
Differential Input, 1MSPS,
12-Bit ADC in SO-8 and S0-8
FEATURES
Fast Throughput Rate: 1MSPS
Specified for V
DD
of 3 V and 5 V
Low Power at max Throughput Rate:
3 mW typ at 833kSPS with 3 V Supplies
8 mW typ at 1MSPS with 5 V Supplies
Fully Differential Analog Input
Wide Input Bandwidth:
70dB SINAD at 300kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface - SPI
TM
/QSPI
TM
/
MicroWire
TM
/ DSP Compatible
Powerdown Mode: 1A max
8 Pin SOIC and SOIC Packages
APPLICATIONS
Transducer Interface
Battery Powered Systems
Data Acquisition Systems
Portable Instrumentation
Motor Control
Communications
GENERAL DESCRIPTION
The AD7450 is a 12-bit, high speed, low power, succes-
sive-approximation (SAR) analog-to-digital converter
featuring a fully differential analog input. It operates from
a single 3 V or 5 V power supply and features throughput
rates up to 833kSPS or 1MSPS respectively.
This part contains a low-noise, wide bandwidth, differen-
tial track and hold amplifier (T/H) which can handle
input frequencies in excess of 1MHz with the -3dB point
being 20MHz typically. The reference voltage for the
AD7450 is applied externally to the V
REF
pin and can be
varied from 100 mV to 2.5 V depending on the power
supply and to suit the application. The value of the refer-
ence voltage determines the common mode voltage range
of the part. With this truly differential input structure and
variable reference input, the user can select a variety of
input ranges and bias points.
The conversion process and data acquisition are controlled
using
CS and the serial clock allowing the device to inter-
face with Microprocessors or DSPs. The input signals are
sampled on the falling edge of
CS and the conversion is
also initiated at this point.
FUNCTIONAL BLOCK DIAGRAM
The SAR architecture of this part ensures that there are
no pipeline delays.
The AD7450 uses advanced design techniques to achieve
very low power dissipation at high throughput rates.
PRODUCT HIGHLIGHTS
1.Operation with either 3 V or 5 V power supplies.
2.High Throughput with Low Power Consumption.
With a 3V supply, the AD7450 offers 3mW typ power
consumption for 833kSPS throughput.
3.Fully Differential Analog Input.
4.Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock,
allowing the power to be reduced as the conversion time
is reduced through the serial clock speed increase. This
part also features a shutdown mode to maximize power
efficiency at lower throughput rates.
5.Variable Voltage Reference Input.
6.No Pipeline Delay.
7.Accurate control of the sampling instant via a
CS input
and once off conversion control.
8. ENOB > 8 bits typ with 100mV Reference
.
MicroWire is a trademark of National Semiconductor Corporation.
SPI and QSPI are trademarks of Motorola, Inc.
12-BIT SUCCESSIVE
APPROXIMATION
A DC
CONTROL
LOGIC
AD7450
VIN+
VIN-
VREF
GND
SCLK
SDATA
CS
VDD
T/H
REV. PrJ
PRELIMINARY TECHNICAL DATA
2
Parameter
A Version
1
B Version
1
Units
Test Conditions/Comments
DYNAMIC PERFORMANCE
F
IN
= 300kHz Sine Wave,
f
SAMPLE
= 833kSPS, 1MSPS
Signal to (Noise + Distortion) Ratio
70
70
dB min
(SINAD)
2
Total Harmonic Distortion (THD)
2
-80
-80
dB max
Peak Harmonic or Spurious Noise
2
-80
-80
dB max
Intermodulation Distortion (IMD)
2
Second Order Terms
-78
-78
dB typ
Third Order Terms
-78
-78
dB typ
Aperture Delay
3
10
10
ns typ
Aperture Jitter
3
50
50
ps typ
Full Power Bandwidth
3
20
20
MHz typ
@ -3 dB
2.5
2.5
MHz typ
@ -0.1 dB
Common Mode Rejection Ratio
T B D
T B D
dB
(CMRR)
2
DC ACCURACY
Resolution
12
12
Bits
Integral Nonlinearity (INL)
2
2
1
LSB max
Differential Nonlinearity (DNL)
2
1
1
LSB max
Guaranteed No Missed Codes to 12 Bits.
Zero Code Error
2
5
5
LSB max
Positive Gain Error
2
5
5
LSB max
Negative Gain Error
2
5
5
LSB max
ANALOG INPUT
Full Scale Input Span
V
IN+
- V
IN -
Volts
2 x V
REF
4
Absolute Input Voltage
V
I N +
V
CM
3
V
REF
/2
Volts
V
CM
= V
REF
V
IN-
V
CM
3
V
REF
/2
Volts
V
CM
= V
REF
DC Leakage Current
1
1
A max
Input Capacitance
20
20
pF typ
When in Track
5
5
pF typ
When in Hold
REFERENCE INPUT
V
REF
Input Voltage
2.5
5
2.5
Volts
5 V supply (1% tolerance for specified
performance)
1.25
6
1.25
Volts
3 V supply (1% tolerance for specified
performance)
DC Leakage Current
1
1
A max
V
REF
Input Capacitance
15
15
pF typ
LOGIC INPUTS
Input High Voltage, V
INH
2.4
2.4
V min
Input Low Voltage, V
INL
0.8
0.8
V max
Input Current, I
IN
1
1
A max
Typically 10 nA, V
IN
= 0 V or V
DD
Input Capacitance, C
IN
7
10
10
pF max
LOGIC OUTPUTS
Output High Voltage, V
OH
2.8
2.8
V min
I
SOURCE
= 200A
Output Low Voltage, V
OL
0.4
0.4
V max
I
SINK
=200A
Floating-State Leakage Current
10
10
A max
Floating-State Output Capacitance
7
10
10
pF max
Output Coding
Two's Complement
CONVERSION RATE
Conversion Time
16
16
SCLK cycles 888ns with an 18MHz SCLK
1.07s with a 15MHz SCLK
Track/Hold Acquisition Time
8
275
275
ns max
Sine Wave input
Throughput Rate
9
1
1
MSPS max
@ V
DD
= 5V
833
833
kSPS max
@ V
DD
= 3V
AD7450 - SPECIFICATIONS
1
( V
DD
= 2.7V to 3.3V, f
SCLK
= 15MHz, f
S
= 833kHz, V
REF
= 1.25 V;
V
DD
= 4.75V to 5.25V, f
SCLK
= 18MHz, f
S
= 1MHz, V
REF
= 2.5 V;
V
CM
3
= V
REF
; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
REV. PrJ
PRELIMINARY TECHNICAL DATA
3
Limit at T
MIN
, T
MAX
Parameter
+3V
+5V
Units
Description
f
SCLK
4
10
10
kHz min
15
18
MHz max
t
CONVERT
16 x t
SCLK
16 x t
SCLK
t
SCLK
= 1/f
SCLK
1.07
0.88
s max
SCLK = 15MHz, 18MHz
t
QUIET
50
50
ns min
Minimum Quiet Time between the End of a Serial Read and the
Next Falling Edge of
CS
t
1
10
10
ns min
Minimum
CS Pulsewidth
t
2
10
10
ns min
CS falling Edge to SCLK Falling Edge Setup Time
t
3
5
20
20
ns max
Delay from
CS Falling Edge Until SDATA 3-State Disabled
t
4
5
40
40
ns max
Data Access Time After SCLK Falling Edge
t
5
0.4 t
SCLK
0.4 t
SCLK
ns min
SCLK High Pulse Width
t
6
0.4 t
SCLK
0.4 t
SCLK
ns min
SCLK Low Pulse Width
t
7
10
10
ns min
SCLK Edge to Data Valid Hold Time
t
8
6
10
10
ns min
SCLK Falling Edge to SDATA 3-State Enabled
45
45
ns max
SCLK Falling Edge to SDATA 3-State Enabled
t
POWER-UP
7
T B D
T B D
s max
Power-Up Time from Full Power-Down
NOTES
1
Sample tested at +25C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 Volts.
2
See Figure 1 and the "Serial Interface" section.
3
Common Mode Voltage.
4
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
5
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with V
DD
= 5 V and time for
an output to cross 0.4 V or 2.0 V for V
DD
= 3 V.
6
t
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured num-
ber is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the
timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
7
See `Power-up Time' Section.
Specifications subject to change without notice.
Parameter
A Version
1
B Version
1
Units Test Conditions/Comments
POWER REQUIREMENTS
V
D D
3/5
3/5
Vmin/max
Range: 3 V 10%; 5 V 5%
I
D D
8 , 1 0
Normal Mode(Static)
1
1
mA typ
V
DD
=3 V/5 V. SCLK On or Off
Normal Mode (Operational)
2.6
2.6
mA max
V
DD
= 5 V. f
SAMPLE
=1MSPS
2
2
mA max
V
DD
= 3 V. f
SAMPLE
=833kSPS
Full Power-Down Mode
1
1
A max
SCLK On or Off
Power Dissipation
Normal Mode (Operational)
13
13
mW max
V
DD
=5 V. f
SAMPLE
=1MSPS
6
6
mW max
V
DD
=3 V. f
SAMPLE
=833kSPS
Full Power-Down
5
5
W max
V
DD
=5 V. SCLK On or Off
3
3
W max
V
DD
=3 V. SCLK On or Off
AD7450 - TIMING SPECIFICATIONS
1,2
( V
DD
= 2.7V to 3.3V, f
SCLK
= 15MHz, f
S
= 833kHz, V
REF
= 1.25 V;
V
DD
= 4.75V to 5.25V, f
SCLK
= 18MHz, f
S
= 1MHz, V
REF
= 2.5 V;
V
CM
3
= V
REF
; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
AD7450
N O T E S
1
Temperature ranges as follows: A, B Versions: 40C to +85C.
2
See `Terminology' section.
3
Common Mode Voltage. The input signal can be centered on any choice of dc Common Mode Voltage as long as this value is in the range
specified in Figure 8.
4
Because the input span of V
IN+
and V
IN-
are both V
REF
, and they are 180 out of phase, the differential voltage is 2 x V
REF
.
5
The reference is functional from 100mV and for 5V supplies it can range up to TBDV (see `Reference Section').
6
The reference is functional from 100mV and for 3V supplies it can range up to 2.2V (see `Reference Section').
7
Sample tested @ +25C to ensure compliance.
8
See POWER VERSUS THROUGHPUT RATE section.
8
T
CONVERT
+ T
QUIET
(See `Serial Interface Section')
10
Measured with a midscale DC input.
Specifications subject to change without notice.
REV. PrJ
PRELIMINARY TECHNICAL DATA
4
AD7450
C A U T I O N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7450 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V
V
IN+
to GND . . . . . . . . . . . . . . . . . 0.3 V to V
DD
+ 0.3 V
V
IN-
to GND . . . . . . . . . . . . . . . . . 0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to GND . . . -0.3 V to V
DD
+ 0.3 V
Digital Output Voltage to GND . . -0.3 V to V
DD
+ 0.3 V
V
REF
to GND . . . . . . . . . . . . . . . . . . . -0.3 V to V
DD
+0.3 V
Input Current to Any Pin Except Supplies
2
. . . . 10mA
Operating Temperature Range
Commercial (A, B Version) . . . . . . . . . -40
o
C to +85
o
C
Storage Temperature Range . . . . . . . . . -65
o
C to +150
o
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . +150
o
C
SOIC, SOIC Package, Power Dissipation . . . . 450mW
JA
Thermal Impedance . . . . . . . . . . 157C/W (SOIC)
205.9C/W (SOIC)
JC
Thermal Impedance . . . . . . . . . . . 56C/W (SOIC)
43.74C/W (SOIC)
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . +215
o
C
Infared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . +220
o
C
E S D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T B D
Linearity
Package
Model
Range
Error (LSB)
1
Option
4
Branding Information
AD7450AR
-40C to +85C
2 LSB
S O - 8
AD7450AR
AD7450ARM
-40C to +85C
2 LSB
RM-8
CPA
AD7450BR
-40C to +85C
1 LSB
S O - 8
AD7450BR
AD7450BRM
-40C to +85C
1 LSB
RM-8
CPB
EVAL-AD7450CB
2
Evaluation Board
EVAL-CONTROL BRD2
3
Controller Board
ORDERING GUIDE
NOTES
1
Linearity error here refers to Integral Linearity Error.
2
This can be used as a stand-alone evaluation board or in conjunction with the EVALUATION BOARD CONTROLLER for evaluation/demonstration purposes.
3
EVALUATION BOARD CONTROLLER. This board is a complete unit allowing a PC to control and communicate with all Analog Devices
evaluation boards ending in the CB designators.
4
S0 = SOIC; RM = SOIC
NOTES
1
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch up.
Figure 1. Serial Interface Timing Diagram
Figure 2. Load Circuit for Digital Output Timing Specifications
1
2
3
4
5
1 3
16
15
14
t 3
0
0
0
0
DB11
DB10
DB2
DB1
DB0
t 2
4 LEADING ZERO'S
3-STATE
t 4
t 6
t 5
t 7
t
8
t
QUIET
CONVE RT
t
B
CS
SCLK
SDATA
t
1
+1.6V
IOL
200A
200A
IOH
TO
OUTP UT
PIN
CL
50 pF
REV. PrJ
PRELIMINARY TECHNICAL DATA
5
AD7450
PIN CONFIGURATION SOIC and SOIC
PIN FUNCTION DESCRIPTION
Pin No. Pin Mnemonic Function
1
V
REF
Reference Input for the AD7450. An external reference must be applied to this input. For a
5 V power supply, the reference is 2.5 V (1%) and for a 3 V power supply, the reference is
1.25 V (1%) for specified performance. This pin should be decoupled to GND with a
capacitor of at least 0.1F. See the `Reference Section' for more details.
2
V
I N +
Positive Terminal for Differential Analog Input.
3
V
IN-
Negative Terminal for Differential Analog Input.
4
G N D
Analog Ground. Ground reference point for all circuitry on the AD7450. All analog input
signals and any external reference signal should be referred to this GND voltage.
5
C S
Chip Select. Active low logic input. This input provides the dual function of initiating a
conversion on the AD7450 and framing the serial data transfer.
6
SDATA
Serial Data. Logic Output. The conversion result from the AD7450 is provided on this
output as a serial data stream. The bits are clocked out on the falling edge of the SCLK
input. The data stream consists of four leading zeros followed by the 12 bits of conversion
data which are provided MSB first. The output coding is two's complement.
7
SCLK
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part.
This clock input is also used as the clock source for the AD7450's conversion process.
8
V
D D
Power Supply Input. V
DD
is 3 V (10%) or 5 V (5%). This supply should be decoupled to
GND with a 0.1F Capacitor and a 10F Tantalum Capacitor.
AD7450
(Not to Scale)
TOP VIEW
1
2
3
4
5
6
7
8
VREF
VIN +
VIN -
GND
CS
S DATA
SCLK
VDD
REV. PrJ
PRELIMINARY TECHNICAL DATA
6
AD7450
TERMINOLOGY
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion)
at the output of the ADC. The signal is the rms amplitude
of the fundamental. Noise is the sum of all
nonfundamental signals up to half the sampling frequency
(f
S
/2), excluding dc. The ratio is dependent on the number
of quantization levels in the digitization process; the more
levels, the smaller the quantization noise. The theoretical
signal to (noise + distortion) ratio for an ideal N-bit con-
verter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms
sum of harmonics to the fundamental. For the AD7450, it
is defined as:
THD (dB )
=
20 log
V
2
2
+
V
3
2
+
V
4
2
+
V
5
2
+
V
6
2
V
1
where V
1
is the rms amplitude of the fundamental and V
2
,
V
3
, V
4
, V
5
and V
6
are the rms amplitudes of the second to
the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of
the rms value of the next largest component in the ADC
output spectrum (up to f
S
/2 and excluding dc) to the rms
value of the fundamental. Normally, the value of this
specification is determined by the largest harmonic in the
spectrum, but for ADCs where the harmonics are buried
in the noise floor, it will be a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa
and fb, any active device with nonlinearities will create
distortion products at sum and difference frequencies of
mfa nfb where m, n = 0, 1, 2, 3, etc. Intermodulation
distortion terms are those for which neither m nor n are
equal to zero. For example, the second order terms in-
clude (fa + fb) and (fa fb), while the third order terms
include (2fa + fb), (2fa fb), (fa + 2fb) and (fa 2fb).
The AD7450 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth
are used. In this case, the second order terms are usually
distanced in frequency from the original sine waves while
the third order terms are usually at a frequency close to
the input frequencies. As a result, the second and third
order terms are specified separately. The calculation of the
intermodulation distortion is as per the THD specification
where it is the ratio of the rms sum of the individual dis-
tortion products to the rms amplitude of the sum of the
fundamentals expressed in dBs.
Aperture Delay
This is the amount of time from the leading edge of the
sampling clock until the ADC actually takes the sample.
Aperture Jitter
This is the sample to sample variation in the effective
point in time at which the actual sample is taken.
Full Power Bandwidth
The full power bandwidth of an ADC is that input fre-
quency at which the amplitude of the reconstructed
fundamental is reduced by 0.1dB or 3dB for a full scale
input.
Common Mode Rejection Ratio (CMRR)
The Common Mode Rejection Ratio is defined as the
ratio of the power in the ADC output at full-scale fre-
quency, f, to the power of a 200mV p-p sine wave applied
to the Common Mode Voltage of V
IN+
and V
IN-
of fre-
quency fs:
CMRR (dB) = 10log(Pf/Pfs)
Pf is the power at the frequncy f in the ADC output; Pfs is
the power at frequency fs in the ADC output.
Integral Nonlinearity (INL)
This is the maximum deviation from a straight line pass-
ing through the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL)
This is the difference between the measured and the ideal 1
LSB change between any two adjacent codes in the ADC.
Zero Code Error
This is the deviation of the midscale code transition (111...111
to 000...000) from the ideal V
IN+
-V
IN -
(i.e., 0LSB).
Positive Gain Error
This is the deviation of the last code transition (011...110 to
011...111) from the ideal V
IN+
-V
IN-
(i.e., +V
REF
- 1LSB), after
the Zero Code Error has been adjusted out.
Negative Gain Error
This is the deviation of the first code transition (100...000 to
100...001) from the ideal V
IN+
-V
IN -
(i.e., -V
REF
+ 1LSB), after
the Zero Code Error has been adjusted out.
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode on the
13th SCLK rising edge (see the "Serial Interface Sec-
tion"). The track/hold acquisition time is the minimum
time required for the track and hold amplifier to remain in
track mode for its output to reach and settle to within 0.5
LSB of the applied input signal.
Power Supply Rejection (PSR)
The power supply rejection ratio is defined as the ratio of
the power in the ADC output at full-scale frequency, f, to
the power of a 200mV p-p sine wave applied to the ADC
V
DD
supply of frequency fs.
PSRR (dB) = 10 log (Pf/Pfs)
Pf is the power at frequency f in the ADC output; Pfs is
the power at frequency fs in the ADC output.
REV. PrJ
PRELIMINARY TECHNICAL DATA
7
AD7450
PERFORMANCE CURVES
TPC 1 and TPC 2 show the typical FFT plots for the
AD7450 with V
DD
of 5V and 3V, 1MHz and 833kHz sam-
pling frequency respectively and an input frequency of
300kHz.
-120
-100
-80
-60
-40
-20
0
0
50
100
150
200
250
300
350
400
450
500
FREQUENCY (kHz)
SN
R (dB
s)
8192 POINT FFT
FSAMPLE = 1MSPS
FIN = 300kHz
SINAD = 71.7dB
THD = -82.8dB
SFDR = -85.3dB
TPC 1. AD7450 Dynamic Performance at 1MSPS
with V
DD
=5V
-120
-100
-80
-60
-40
-20
0
0
50
100
150
200
250
300
350
FREQUENCY (kHz)
S
NR (
d
Bs
)
8192 POINT FFT
f
SAMPLE
= 833ksps
f
IN
= 300kHz
SINAD = 70.2dB
THD = -86dB
SFDR = -87.1dB
TPC 2. AD7450 Dynamic Performance at 833ksps with
V
DD
= 3V
TPC 3 shows the signal-to-(noise+distortion) ratio
performance versus the analog input frequency for
various supply voltages while sampling at 1MSPS
(V
DD
= 5V5%) and 833kSPS (V
DD
= 3V10%).
TITLE
0
0
0
0
0
0
T
IT
LE
0
0
0
0
TPC 3. SINAD vs Analog Input Frequency
for Various Supply Voltages TBD
TPC 4 shows the power supply rejection ratio versus
supply ripple frequency for the AD7450. Here, a
200mV p-p sine wave is coupled onto the V
DD
supply.
A 10nF decoupling capacitor was used on the supply
and a 1F decoupling capacitor was used on V
REF
.
TITLE
0
0
0
0
0
0
T
IT
L
E
0
0
0
0
TPC 4. Power Supply Rejection (see Terminology Sec-
tion) vs. Supply Ripple Frequency at 5V and 3V TBD
REV. PrJ
PRELIMINARY TECHNICAL DATA
8
AD7450
TPC 5 and TPC 6 show typical DNL plots for the
AD7450 with V
DD
of 5V and 3V, 1MHz and 833kHz
sampling frequency respectively and an input frequency of
300kHz.
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0
1024
2048
3072
4096
CODE
DNL ERROR
(
LSB
)
TPC 5 Typical Differential Nonlinearity (DNL) V
DD
= 5V
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0
1024
2048
3072
4096
CODE
DNL
ERROR
(
LSB
)
TPC 6 Typical Differential Nonlinearity (DNL) V
DD
= 3V
TPC 7 and TPC 8 show typical INL plots for the
AD7450 with V
DD
of 5V and 3V, 1MHz and 833kHz
sampling frequency respectively and an input frequency of
300kHz.
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0
1024
2048
3072
4096
CODE
I
N
L
ER
RO
R
(
LS
B
)
TPC 7 Typical Integral Nonlinearity (INL) V
DD
= 5V
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0
1024
2048
3072
4096
CODE
INL
ERR
O
R
(
LS
B
)
TPC 8 Typical Integral Nonlinearity (INL) V
DD
= 3V
REV. PrJ
PRELIMINARY TECHNICAL DATA
9
AD7450
TPC 9 and TPC 10 show the change in DNL versus V
REF
for V
DD
of 5V and 3.3V respectively.
-1
-0.5
0
0.5
1
0
0.5
1
1.5
2
2.5
VREF
Ch
a
n
g
e in
D
N
L
Positive DNL
Negative DNL
TPC 9.Change in DNL vs Reference Voltage V
DD
= 5V
-1
-0.5
0
0.5
1
1.5
0
0.6
1.2
1.8
2.4
VREF
Ch
an
g
e

in
D
N
L
Positive DNL
Negative DNL
TPC 10. Change in DNL vs Reference Voltage V
DD
= 3.3V*
TPC 11 and TPC 12 show the change in INL versus V
REF
for V
DD
of 5V and 3.3V respectively.
-1.5
-1
-0.5
0
0.5
1
1.5
0
0.5
1
1.5
2
2.5
VREF
Ch
a
n
g
e
in
INL
Positive INL
Negative INL
TPC 11. Change in INL vs Reference Voltage V
DD
= 5V
-1.5
-1
-0.5
0
0.5
1
1.5
2
0
0.6
1.2
1.8
2.4
VREF
Ch
a
n
g
e i
n
IN
L
Positive INL
Negative INL
TPC 12. Change in INL vs Reference Voltage V
DD
= 3.3V*
*See `Reference Section
REV. PrJ
PRELIMINARY TECHNICAL DATA
1 0
AD7450
TPC 13 shows the change in Zero Code Error versus the
Reference Voltage for V
DD
= 5V and 3.3V.
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
0.25
0.75
1.25
1.75
2.25
VREF
Ze
r
o
C
ode

E
rror
(
LS
B
)
2.5
VDD = 5 V
Fs = 1MSPS
VDD = 3.3 V
Fs = 833kSPS
TPC 13. Change in Zero Code Error vs Reference Voltage
V
DD
= 5V and 3.3 V*
TPC 14 shows a histogram plot for 10000 conversions of
a dc input using the AD7450 with V
DD
= 5V. Both ana-
log inputs were set to V
REF
, which is the center of the
code transition.
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
10000
2044
2045
2046
2047
2048
2049
CODE
10000 Codes
TPC 14. Histogram of 10000 conversions of a DC Input with
V
DD
= 5V
TPC 15 shows a histogram plot for 10000 conversions of
a dc input for V
DD
of 3V. As in TPC 14, both inputs are
set to V
REF
. Both plots indicate good noise performance as
the majority of codes appear in one output bin.
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
10000
2044
2045
2046
2047
2048
2049
CODE
71 Codes
9839 Codes
90 Codes
TPC 15. Histogram of 10000 conversions of a DC Input with
V
DD
= 3V
TPC 16 shows the Effective Number of Bits (ENOB)
versus the Reference Voltage for V
DD
5V and 3.3V. Note
that the AD7450 has an ENOB of greater than 8-bits typi-
cally when V
REF
= 100mV.
6
7
8
9
10
11
12
0
0.5
1
1.5
2
2.5
VREF
E
f
fecti
ve Nu
m
b
er o
f
Bi
ts
VDD = 5V
Fs = 1MSPS
VDD = 3.3V
Fs = 833kSPS
TPC 16. Change in ENOB vs Reference Voltage
V
DD
= 5V and 3.3 V*
*See Reference Section.
REV. PrJ
PRELIMINARY TECHNICAL DATA
1 1
AD7450
TPC 17 shows the Common Mode Rejection Ratio versus
supply ripple frequency for the AD7450 for both V
DD
=
5V and 3 V. Here a 200mV p-p sine wave is coupled onto
the Common Mode Voltage of V
IN+
and V
IN-
.
0
10
20
30
40
50
60
70
80
90
10
100
1000
10000
Frequency (kHz)
CM
R
R

(
dB
)
VDD = 5 V
VDD = 3 V
TPC 17. CMRR versus Frequency for V
DD
= 5V and 3 V
CIRCUIT INFORMATION
The AD7450 is a fast, low power, single supply, 12-bit
successive approximation analog-to-digital converter
(ADC). It can operate with a 5 V and 3V power supply
and is capable of throughput rates up to 1MSPS and
833kSPS when supplied with a 18MHz or 15MHz clock
respectively. This part requires an external reference to be
applied to the V
REF
pin, with the value of the reference
chosen depending on the power supply and to suit the
application.
When operated with a 5 V supply, the maximum reference
that can be applied to the part is 2.5 V and when operated
with a 3 V supply, the maximum reference that can be
applied to the part is 2.2 V. (See `Reference Section').
The AD7450 has an on-chip differential track and hold
amplifier, a successive approximation (SAR) ADC and a
serial interface, housed in either an 8-lead SOIC or
SOIC package. The serial clock input accesses data
from the part and also provides the clock source for the
successive-approximation ADC. The AD7450 features a
power-down option for reduced power consumption be-
tween conversions. The power-down feature is
implemented across the standard serial interface as de-
scribed in the `Modes of Operation' section.
CONVERTER OPERATION
The AD7450 is a successive approximation ADC based
around two capacitive DACs. Figures 3 and 4 show sim-
plified schematics of the ADC in Acquisition and
Conversion phase respectively. The ADC comprises of
Control Logic, a SAR and two capacitive DACs. In
figure 3 (acquisition phase), SW3 is closed and SW1 and
SW2 are in position A, the comparator is held in a bal-
anced condition and the sampling capacitor arrays acquire
the differential signal on the input.
SW3
VIN+
VIN-
SW1
Cs
Cs
A
A
B
VREF
SW2
CONTROL
LOGIC
CAPACITIVE
DAC
CAPACITIVE
DAC
COMPARATOR
B
Figure 3. ADC Acquisition Phase
When the ADC starts a conversion (figure 4), SW3 will
open and SW1 and SW2 will move to position B, causing
the comparator to become unbalanced. Both inputs are
disconnected once the conversion begins. The Control
Logic and the charge redistribution DACs are used to add
and subtract fixed amounts of charge from the sampling
capacitor arrays to bring the comparator back into a bal-
anced condition. When the comparator is rebalanced, the
conversion is complete. The Control Logic generates the
ADC's output code. The output impedances of the
sources driving the V
IN+
and the V
IN-
pins must be
matched otherwise the two inputs will have different set-
tling times, resulting in errors.
SW3
VIN+
VIN-
SW1
Cs
Cs
A
B
A
B
VREF
SW2
CONTROL
LOGIC
CAPACITIVE
DAC
CAPACITIVE
DAC
COMPARATOR
Figure 4. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding for the AD7450 is two's complement.
The designed code transitions occur at successive LSB
values (i.e. 1LSB, 2LSBs, etc.) and the LSB size is
2xV
REF
/4096. The ideal transfer characteristic of the
AD7450 is shown in figure 5.
REV. PrJ
PRELIMINARY TECHNICAL DATA
1 2
AD7450
100...000
+VREF - 1LSB
100...001
100...010
111...111
000...000
000...001
011...110
011...111
-VREF + 1LSB
0LSB
A
D
C
C
O
D
E
1LSB = 2xVREF/4096
ANALOG INPUT
(VIN+- VIN-)
Figure 5. AD7450 Ideal Transfer Characteristic
TYPICAL CONNECTION DIAGRAM
Figure 6 shows a typical connection diagram for the
AD7450 for both 5 V and 3 V supplies. In this setup the
GND pin is connected to the analog ground plane of the
system. The V
REF
pin is connected to either a 2.5 V or a
1.25 V decoupled reference source depending on the
power supply, to set up the analog input range. The com-
mon mode voltage has to be set up externally and is the
value that the two inputs are centered on. For more details
on driving the differential inputs and setting up the com-
mon mode, see the `Driving Differential Inputs' section.
The conversion result for the ADC is output in a 16-bit
word consisting of four leading zeros followed by the
MSB of the 12-bit result. For applications where power
consumption is of concern, the power-down mode should
be used between conversions or bursts of several conver-
sions to improve power performance. See `Modes of
Operation' section.
CM*
CM*
* CM - COMMON MODE VOLTAGE
VIN+
VIN-
VDD
SCLK
SDATA
CS
GND
VREF
C/P
SERIAL
INTERFACE
+3V/+5V
SUPPLY
1.25V/2.5V
VREF
0.1F
0.1F
10F
AD7450
VREF
P-to-P
VREF
P-to-P
Figure 6. Typical Connection Diagram
THE ANALOG INPUT
The analog input of the AD7450 is fully differential. Dif-
ferential signals have a number of benefits over single
ended signals including noise immunity based on the
device's common mode rejection, improvements in distor-
tion performance, doubling of the device's available
dynamic range and flexibility in input ranges and bias
points.
Figure 7 defines the fully differential analog input of the
AD7450.
VIN+
AD7450
VIN-
VREF
P-to-P
VREF
P-to-P
COMMON
MODE
VOLTAGE
Figure 7. Differential Input Definition
The amplitude of the differential signal is the difference
between the signals applied to the V
IN+
and V
IN-
pins (i.e.
V
IN+
- V
IN-
). V
IN+
and V
IN-
are simultaneously driven by
two signals each of amplitude V
REF
that are 180 out of
phase. The amplitude of the differential signal is therefore
-V
REF
to +V
REF
peak-to-peak (i.e. 2 x V
REF
). This is re-
gardless of the common mode (CM). The common mode
is the average of the two signals, i.e. (V
IN+
+ V
IN-
)/2 and
is therefore the voltage that the two inputs are centered on.
This results in the span of each input being CM V
REF
/2.
This voltage has to be set up externally and its range var-
ies with V
REF
. As the value of V
REF
increases, the
common mode range decreases. When driving the inputs
with an amplfier, the actual common mode range will be
determined by the amplifier's output voltage swing.
Figure 8 shows how the common mode range varies with
V
REF
for a 5 V power supply and figure 9 shows an ex-
ample of the common mode range when using the
AD8138 differential amplifer to drive the analog inputs.
The common mode must be in this range to guarantee the
specifications. With a 3V power supply, the Common
Mode range is TBD.
For ease of use, the common mode can be set up to be
equal to V
REF
, resulting in the differential signal being
V
REF
centered on V
REF
. When a conversion takes place,
the common mode is rejected resulting in a virtually noise
free signal of amplitude -V
REF
to +V
REF
corresponding to
he digital codes of 0 to 4095.
REV. PrJ
PRELIMINARY TECHNICAL DATA
1 3
AD7450
TITLE
0
0
0
0
0
0
T
IT
L
E
0
0
0
0
Figure 8. Input Common Mode Range (CM) versus V
REF
(Vdd = 5V and V
REF
(max) = 2.5V)
-1
0
1
2
3
4
5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
VREF
C
o
m
m
on M
ode R
a
n
g
e
2.8
0.9
Figure 9. Input Common Mode Range versus V
REF
(Vdd = 5V and V
REF
(max) = 2.5V) when Driving V
IN+
and V
IN-
with the AD8138 Differential Amplifier
Figure 10 shows examples of the inputs to V
IN+
and V
IN-
for different values of V
REF
for V
DD
= 5 V. It also gives
the maximum and minimum common mode voltages for
each reference value according to figure 8.
Reference = 0.625 V (VREFmax/4)
0.625 V peak to peak
Common Mode (CM)
CMmin= 0.275 V
CMmax= 3.8 V
Reference = 1.25 V (VREFmax/2)
1.25 V peak to peak
Common Mode (CM)
CMmin= 0.85 V
CMmax= 3.55 V
Reference = 2.5 V (VREFmax)
2.5 V peak to peak
Common Mode (CM)
CMmin= 2 V
CMmax= 3 V
Figure 10. Examples of the Analog Inputs to V
IN+
and V
IN-
for Different Values of V
REF
for V
DD
= 5 V.
Analog Input Structure
Figure 11 shows the equivalent circuit of the analog input
structure of the AD7450. The four diodes provide ESD
protection for the analog inputs. Care must be taken to
ensure that the analog input signals never exceed the sup-
ply rails by more than 200mV. This will cause these
diodes to become forward biased and start conducting into
the substrate. These diodes can conduct up to 10mA with-
out causing irreversible damage to the part.
The capacitors C1, in figure 11 are typically 4pF and can
primarily be attributed to pin capacitance. The resistors
are lumped components made up of the on-resistance of
the switches. The value of these resistors is typically about
100 . The capacitors, C2, are the ADC's sampling ca-
pacitors and have a capacitance of 16pF typically.
For ac applications, removing high frequency components
from the analog input signal is recommended by the use of
an RC low-pass filter on the relevant analog input pins.
In applications where harmonic distortion and signal to
noise ratio are critical, the analog input should be driven
from a low impedance source. Large source impedances
will significantly affect the ac performance of the ADC.
This may necessitate the use of an input buffer amplifier.
The choice of the opamp will be a function of the particu-
lar application.
REV. PrJ
PRELIMINARY TECHNICAL DATA
1 4
AD7450
VDD
C1
D
D
VIN+
R1
C2
VIN-
R1
C2
VDD
D
D
C1
Figure 11. Equivalent Analog Input Circuit.
Conversion Phase - Switches Open
Track Phase - Switches Closed
When no amplifier is used to drive the analog input, the
source impedance should be limited to low values. The
maximum source impedance will depend on the amount of
Total Harmonic Distortion (THD) that can be tolerated.
The THD will increase as the source impedance increases
and performance will degrade. Figure 12 shows a graph
of the THD versus analog input signal frequency for dif-
ferent source impedances.
TITLE
0
0
0
0
0
0
T
IT
L
E
0
0
0
0
Figure 12.THD vs Analog Input Frequency for Various
Source Impedances TBD
Figure 13 shows a graph of THD versus analog input
frequency for V
DD
of 5V and 3V, while sampling at
1MHz and 833kHz with a SCLK of 18 MHz and 15MHz
respectively.
T IT LE
0
0
0
0
0
0
T
IT
L
E
0
0
0
0
Figure 13.THD vs Analog Input Frequency for 3V and 5V
Supply Voltages TBD
DRIVING DIFFERENTIAL INPUTS
Differential operation requires that V
IN+
and V
IN-
be si-
multaneously driven with two equal signals that are 180
o
out of phase. The common mode must be set up exter-
nally and has a range which is determined by V
REF
, the
power supply and the particular amplifier used to drive the
analog inputs (see figure 8). Differential modes of opera-
tion with either an ac or dc input, provide the best THD
performance over a wide frequency range. Since not all
applications have a signal preconditioned for differential
operation, there is often a need to perform single ended to
differential conversion.
Differential Amplifier
An ideal method of applying dc differential drive to the
AD7450 is to use a differential amplifier such as the AD8138.
This part can be used as a single ended to differential
amplifier or as a differential to differential amplifier. In both
cases the analog input needs to be bipolar. It also provides
common mode level shifting and buffering of the bipolar
input signal. Figure 14 shows how the AD8138 can be used
as a single ended to differential amplifier. The positive and
negative outputs of the AD8138 are connected to the respec-
tive inputs on the ADC via a pair of series resistors to
minimize the effects of switched capacitance on the front end
of the ADC. The RC low pass filter on each analog input is
recommended in ac applications to remove high frequency
components of the analog input. The architecture of the
AD8138 results in outputs that are very highly balanced over
a wide frequency range without requiring tightly matched
external components.
If the analog input source being used has no impedance then
all four resistors (Rg1, Rg2, Rf1, Rf2) should be the same. If
the source has a 50 impedance and a 50
termination for
example, the value of Rg2 should be increased by 25
to
balance this parallel impedance on the input and thus ensure
that both the positive and negative analog inputs have the
same gain (see figure 14). The outputs of the amplifier are
perfectly matched, balanced differential outputs of identical
amplitude and are exactly 180
o
out of phase.
REV. PrJ
PRELIMINARY TECHNICAL DATA
1 5
AD7450
The AD8138 is specified with 3 V, 5 V and 5 V power
supplies but the best results are obtained when it is supplied
by 5 V. A lower cost device that could also be used in this
configuration with slight differences in characteristics to the
AD8138 but with similar performance and operation is the
AD8132.
2.5V
3.75V
1.25V
Rs*
Rs*
Rf2
2.5V
3.75V
1.25V
EXTERNAL
VREF (2.5V)
VREF
VIN+
AD7450
VIN-
AD8138
C*
C*
*Moun t as close to the AD7450 as
possible and ensure high
precision Rs and Cs are used
Rs - 10R; C - 1nF;
Rg1=Rf1=Rf2= 499R; Rg2 = 523R
Rf1
Rg1
Vocm
51R
Rg2
.
GND
+2.5V
-2.5V
Figure 14. Using the AD8138 as a Single Ended to Differen-
tial Amplifier
Opamp Pair
An opamp pair can be used to directly couple a differential
signal to the AD7450. The circuit configurations shown
in figures 15(a) and 15(b) show how a dual opamp can be
used to convert a single ended signal into a differential
signal for both a bipolar and a unipolar input signal re-
spectively.
The voltage applied to point A is the Common Mode
Voltage. In both diagrams, it is connected in some way to
the reference but any value in the common mode range can
be input here to setup the common mode. Examples of
suitable dual opamps that could be used in this configura-
tion to provide differential drive to the AD7450 are the
AD8042, AD8056 and the AD8022.
Care must be taken when chosing the opamp used, as the
selection will depend on the required power supply and the
system performance objectives. The driver circuits in fig-
ures 15(a) and 15(b) are optimized for dc coupling
applications requiring optimum distortion performance.
The differential op-amp driver circuit in figure 15(a) is
configured to convert and level shift a 2.5 V p-p single
ended, ground referenced (bipolar) signal to a 5 V p-p
differential signal centered at the V
REF
level of the ADC.
The circuit configuration shown in figure 15(b) converts a
unipolar, single ended signal into a differential signal.
GND
VREF P-to-P
27
27
390
220
220
10K
EXTERNAL
VREF
220
VDD
V+
V+
V-
V-
VIN+
VIN- VREF
AD7450
220
20K
.
0.1F
.
.
A
Figure 15(a). Dual Opamp Circuit to Convert a Single Ended
Bipolar Input into a Differential Input
GND
VREF P-to-P
27
27
390
220
10K
EXTERNAL
VREF
220
VDD
V+
V+
V-
V-
VIN+
VIN- VREF
AD7450
220
.
.
0.1F
A
VREF/2
Figure 15(b). Dual Opamp Circuit to Convert a Single Ended
Unipolar Input into a Differential Input
RF Transformer
In systems that do not need to be dc-coupled, an RF trans-
former with a center tap offers a good solution for
generating differential inputs. Figure 16 shows how a
transformer is used for single ended to differential conver-
sion. It provides the benefits of operating the ADC in the
differential mode without contributing additional noise
and distortion. An RF transformer also has the benefit of
providing electrical isolation between the signal source
and the ADC. A transformer can be used for most ac ap-
plications. The center tap is used to shift the differential
signal to the common mode level required, in this case it
is connected to the reference so the common mode level is
the value of the reference.
REV. PrJ
PRELIMINARY TECHNICAL DATA
1 6
AD7450
C
EXTERNAL
VREF (2.5V)
R
R
R
VREF
VIN+
AD7450
VIN-
2.5V
3.75V
1.25V
2.5V
3.75V
1.25V
Figure 16. Using an RF Transformer to Generate
Differential Inputs
REFERENCE SECTION
An external reference source is required to supply the
reference to the AD7450. This reference input can range
from 100 mV to 2.5 V. With a 5V power supply, the
specified and maximum reference is 2.5V. With a 3V
power supply, the specified reference is 1.25V and the
maximum reference is 2.2V. In both cases, the reference is
functional from 100mV. It is important to note that as the
reference input moves closer to the maximum reference
input, the performance improves. When operating the
device from V
DD
= 2.7V to 3.3V, the maximum analog
input range (VINmax) must never be greater than V
DD
+
0.3V to comply with the maximum ratings of the device.
For example:
VINmax = V
DD
+ 0.3
VINmax = V
REF
+ V
REF
/2
If V
DD
= 3.3V
then VINmax = 3.6 V
Therefore 3xV
REF
/2 = 3.6 V
V
REF
max = 2.4 V
Therefore, when operating at V
DD
= 3.3 V, the value of
V
REF
can range from 100mV to a maximum value of 2.4V.
When V
DD
= 2.7 V, V
REF
max = 2 V.
When operating from V
DD
= 4.75 V to 5.25 V, there is
no need to worry about the maximum analog input in
relation to V
DD
as the maximum V
REF
is 2.5 V resulting
the maximum analog input span being 3.75 V which is not
close to V
DD
.
The performance of the part at different reference values is
shown in TPC9 to TPC13 and in TPC16 and TPC17.
The value of the reference sets the analog input span and
the common mode voltage range. Errors in the reference
source will result in gain errors in the AD7450 transfer
function and will add to specified full scale errors on the
part. A capacitor of 0.1F should be used to decouple the
V
REF
pin to GND. Table I lists examples of suitable volt-
age references that could be used that are available from
Analog Devices and Figure 17 shows a typical connection
diagram for the V
REF
pin.
Table I Examples of Suitable Voltage References
Reference Output Initial
Operating
Voltage Accuracy Current
(% max)
(A)
AD589 1.235
1.2-2.8
50
AD1580 1.225
0.08-0.8
50
REF192 2.5
0.08-0.4
45
REF43 2.5
0.06-0.1
600
AD780 2.5
0.04-0.2
1000
VREF
AD7450*
VDD
1
2
3
4
5
6
7
8
VIN
Temp
GND
Trim
Vout
OpSel
0.1F
NC
NC
NC
NC
VDD
0.1F
0.1F
10nF
*ADDITIONA L PINS OMITTED FOR CLARITY
AD780
Figure 17. Typical V
REF
Connection Diagram
SINGLE ENDED OPERATION
When supplied with a 5 V power supply, the AD7450 can
handle a single ended input. The design of this part is
optimized for differential operation so with a single ended
input performance will degrade. Linearity will degrade by
typically 0.2LSBs, Zero Code and the Full Scale Errors
will degrade by typically 2LSBs and AC performance is
not guaranteed.
To operate the AD7450 in single ended mode, the V
IN+
input is coupled to the signal source while the V
IN-
input is
biased to the appropriate voltage corresponding to the
mid-scale code transition. This voltage is the Common
Mode, which is a fixed dc voltage (usually the reference).
The V
IN+
input swings around this value and should have
voltage span of 2 x V
REF
to make use of the full dynamic
range of the part. The input signal will therefore have peak
to peak values of Common Mode V
REF
. If the analog
input is unipolar then an opamp in a non-inverting
unity gain configuration can be used to drive the V
IN+
pin.
Because the ADC operates from a single supply, it will be
necessary to level shift ground based bipolar signals to
comply with the input requirements. An opamp can be
configured to rescale and level shift the ground based bi-
polar signal so it is compatible with the selected input
range of the AD7450 (see Figure 18).
REV. PrJ
PRELIMINARY TECHNICAL DATA
1 7
AD7450
Figure 19. Serial interface Timing Diagram
1
2
3
4
5
1 3
16
15
14
t 3
0
0
0
0
DB11
DB10
DB2
DB1
DB0
t 2
4 LEADING ZERO'S
3-STATE
t 4
t 6
t 5
t 7
t
8
t
QUIET
CONVE RT
t
B
CS
SCLK
SDATA
t
1
EXTERNAL
VREF (2.5V)
VIN
0V
+2.5V
-2.5V
0.1F
VREF
VIN+
AD7450
VIN-
R
R
R
R
0V
+2.5V
+ 5V
Figure 18. Applying a Bipolar Single Ended Input to the
AD7450
SERIAL INTERFACE
Figure 19 shows a detailed timing diagram for the serial
interface of the AD7450. The serial clock provides the
conversion clock and also controls the transfer of data
from the AD7450 during conversion.
CS initiates the
conversion process and frames the data transfer. The fall-
ing edge of
CS puts the track and hold into hold mode
and takes the bus out of three-state. The analog input is
sampled and the conversion initiated at this point. The
conversion will require 16 SCLK cycles to complete.
Once 13 SCLK falling edges have occurred, the track and
hold will go back into track on the next SCLK rising edge
as shown at point B in Figure 19. On the 16th SCLK
falling edge the SDATA line will go back into three-state.
If the rising edge of
CS occurs before 16 SCLKs have
elapsed, the conversion will be terminated and the SDATA
line will go back into three-state on the 16th SCLK falling
edge. 16 serial clock cycles are required to perform a
conversion and to access data from the AD7450.
CS going
low provides the first leading zero to be read in by the micro-
controller or DSP. The remaining data is then clocked out
on the subsequent SCLK falling edges beginning with the
second leading zero. Thus the first falling clock edge on the
serial clock provides the second leading zero. The final bit
in the data transfer is valid on the 16th falling edge, having
been clocked out on the previous (15th) falling edge.
In applications with a slower SCLK, it may be possible to
read in data on each SCLK rising edge i.e. the first rising
edge of SCLK after the
CS falling edge would have the
leading zero provided and the 15th SCLK edge would have
DB0 provided.
Timing Example 1
Having F
SCLK
= 18MHz and a throughput rate of
1MSPS gives a cycle time of:
1/Throughput = 1/1000000 = 1s
A cycle consists of:
t
2
+ 12.5 (1/F
SCLK
) + t
ACQ
= 1s.
Therefore if t
2
= 10ns then:
10ns + 12.5(1/18MHz) + t
ACQ
= 1s
t
ACQ
= 296ns
This 296ns satisfies the requirement of 275ns for t
ACQ
.
From Figure 20, t
ACQ
comprises of:
2.5(1/F
SCLK
) + t
8
+ t
QUIET
where t
8
= 45ns. This allows a value of 113ns for t
QUIET
satisfying the minimum requirement of 100ns.
Timing Example 2
Having F
SCLK
= 5MHz and a throughput rate of
315kSPS gives a cycle time of :
1/Throughput = 1/315000 = 3.174s
A cycle consists of:
t
2
+ 12.5 (1/F
SCLK
) + t
ACQ
= 3.174s.
Therefore if t
2
is 10ns then:
10ns + 12.5(1/5MHz) + t
ACQ
= 3.174s
t
ACQ
= 664ns
REV. PrJ
PRELIMINARY TECHNICAL DATA
1 8
AD7450
Figure 20. Serial Interface Timing example
1
2
3
4
5
13
16
15
14
t
2
t
6
t
5
t
8
t
QUIET
CONVERT
t
B
CS
t
ACQUISITION
12.5(1/fSCLK)
1/Throughput
10ns
SCLK
C
This 664ns satisfies the requirement of 275ns for t
ACQ
.
From Figure 20, t
ACQ
comprises of:
2.5(1/F
SCLK
) + t
8
+ t
QUIET
where t
8
= 45ns. This allows a value of 119ns for t
QUIET
satisfying the minimum requirement of 100ns.
As in this example and with other slower clock values, the
signal may already be acquired before the conversion is
complete but it is still necessary to leave 100ns minimum
t
QUIET
between conversions. In example 2 the signal should
be fully acquired at approximately point C in Figure 20.
MODES OF OPERATION
The mode of operation of the AD7450 is selected by
controlling the logic state of the
CS signal during a
conversion. There are two possible modes of operation,
Normal Mode and Power-Down Mode. The point at which
CS is pulled high after the conversion has been initiated will
determine whether or not the AD7450 will enter the power-
down mode. Similarly, if already in power-down,
CS
controls whether the device will return to normal operation
or remain in power-down. These modes of operation are
designed to provide flexible power management options.
These options can be chosen to optimize the power dissipa-
tion/throughput rate ratio for differing application
requirements.
Normal Mode
This mode is intended for fastest throughput rate perfor-
mance. The user does not have to worry about any
power-up times as the AD7450 is kept fully powered up.
Figure 21 shows the general diagram of the operation of
the AD7450 in this mode. The conversion is initiated on
the falling edge of
CS as described in the `Serial Interface
Section'. To ensure the part remains fully powered up,
CS must remain low until at least 10 SCLK falling edges
have elapsed after the falling edge of
CS.
If
CS is brought high any time after the 10th SCLK fall-
ing edge, but before the 16th SCLK falling edge, the part
will remain powered up but the conversion will be termi-
nated and SDATA will go back into three-state.
Sixteen serial clock cycles are required to complete the
conversion and access the complete conversion result.
CS
may idle high until the next conversion or may idle low
until sometime prior to the next conversion. Once a data
transfer is complete, i.e. when SDATA has returned to
three-state, another conversion can be initiated after the
quiet time, t
QUIET
has elapsed by again bringing
CS low.
4 LEADING ZEROS + CONVERSION RESULT
SDATA
10
16
CS
SCLK
1
Figure 21. Normal Mode Operation
Power Down Mode
This mode is intended for use in applications where
slower throughput rates are required; either the ADC is
powered down between each conversion, or a series of
conversions may be performed at a high throughput rate
and the ADC is then powered down for a relatively long
duration between these bursts of several conversions.
When the AD7450 is in the power down mode, all analog
circuitry is powered down. To enter power down mode,
the conversion process must be interrupted by bringing
CS high anywhere after the second falling edge of SCLK
and before the tenth falling edge of SCLK as shown in
Figure 22.
Once
CS has been brought high in this window of
SCLKs, the part will enter power down and the conver-
sion that was initiated by the falling edge of
CS will be
terminated and SDATA will go back into three-state.
The time from the rising edge of
CS to SDATA three-
state enabled will never be greater than t
8
(see the
`Timing Specifications'). If
CS is brought high before
the second SCLK falling edge, the part will remain in
normal mode and will not power-down. This will avoid
accidental power-down due to glitches on the
CS line.
REV. PrJ
PRELIMINARY TECHNICAL DATA
1 9
AD7450
Figure 23. Exiting Power Down Mode
SDATA
CS
INVALID DATA
SCLK
1
16
VALID DATA
1
A
THE PART BEGINS
TO POWER UP
THE PART IS FULLY POWERED
UP WITH VIN FULLY ACQUIRED
10
10
16
tPOWERUP
In order to exit this mode of operation and power the
AD7450 up again, a dummy conversion is performed. On
the falling edge of
CS the device will begin to power up,
and will continue to power up as long as
CS is held low
until after the falling edge of the 10th SCLK. The device
will be fully powered up after 1sec has elapsed and, as
shown in Figure 23, valid data will result from the next
conversion.
If
CS is brought high before the 10th falling edge of
SCLK, the AD7450 will again go back into power-down.
This avoids accidental power-up due to glitches on the
CS
line or an inadvertent burst of eight SCLK cycles while
CS is low. So although the device may begin to power up
on the falling edge of
CS, it will again power-down on the
rising edge of
CS as long as it occurs before the 10th
SCLK falling edge.
CS
THREE STATE
SCLK
SDATA
1
2
10
Figure 22. Entering Power Down Mode
Power up Time
The power up time of the AD7450 is typically 1sec,
which means that with any frequency of SCLK up to
18MHz, one dummy cycle will always be sufficient to
allow the device to power-up. Once the dummy cycle is
complete, the ADC will be fully powered up and the input
signal will be acquired properly. The quiet time t
QUIET
must still be allowed from the point at which the bus goes
back into three-state after the dummy conversion, to the
next falling edge of
CS.
When running at the maximum throughput rate of
1MSPS, the AD7450 will power up and acquire a signal
within 0.5LSB in one dummy cycle, i.e. 1s. When
powering up from the power-down mode with a dummy
cycle, as in Figure 23, the track and hold, which was in
hold mode while the part was powered down, returns to
track mode after the first SCLK edge the part receives
after the falling edge of
CS. This is shown as point A in
Figure 23.
Although at any SCLK frequency one dummy cycle is
sufficient to power the device up and acquire V
IN
, it does
not necessarily mean that a full dummy cycle of 16
SCLKs must always elapse to power up the device and
acquire V
IN
fully; 1s will be sufficient to power the de-
vice up and acquire the input signal.
For example, if a 5MHz SCLK frequency was applied to
the ADC, the cycle time would be 3.2s (i.e. 1/(5MHz)
x 16). In one dummy cycle, 3.2s, the part would be
powered up and V
IN
acquired fully. However after 1s
with a 5MHz SCLK only 5 SCLK cycles would have
elapsed. At this stage, the ADC would be fully powered
up and the signal acquired. So, in this case the
CS can
be brought high after the 10th SCLK falling edge and
brought low again after a time t
QUIET
to initiate the con-
version.
When power supplies are first applied to the AD7450,
the ADC may either power up in the power-down mode
or normal mode. Because of this, it is best to allow a
dummy cycle to elapse to ensure the part is fully powered
up before attempting a valid conversion. Likewise, if the
user wishes the part to power up in power-down mode,
then the dummy cycle may be used to ensure the device is
in power-down by executing a cycle such as that shown in
Figure 22.
Once supplies are applied to the AD7450, the power up
time is the same as that when powering up from the
power-down mode. It takes approximately 1s to power
up fully if the part powers up in normal mode. It is not
necessary to wait 1s before executing a dummy cycle to
ensure the desired mode of operation. Instead, the
dummy cycle can occur directly after power is supplied to
the ADC. If the first valid conversion is then performed
directly after the dummy conversion, care must be taken
to ensure that adequate acquisition time has been al-
lowed.
As mentioned earlier, when powering up from the power-
down mode, the part will return to track upon the first
SCLK edge applied after the falling edge of
CS. How-
ever, when the ADC powers up initially after supplies are
applied, the track and hold will already be in track. This
means if (assuming one has the facility to monitor the
ADC supply current) the ADC powers up in the desired
mode of operation and thus a dummy cycle is not re-
REV. PrJ
PRELIMINARY TECHNICAL DATA
2 0
AD7450
quired to change mode, then neither is a dummy cycle
required to place the track and hold into track.
POWER VERSUS THROUGHPUT RATE
By using the power-down mode on the AD7450 when not
converting, the average power consumption of the ADC
decreases at lower throughput rates. Figure 24 shows
how, as the throughput rate is reduced, the device remains
in its power-down state longer and the average power con-
sumption reduces accordingly. It shows this for both 5V
and 3V power supplies.
For example, if the AD7450 is operated in continous sam-
pling mode with a throughput rate of 100kSPS and an
SCLK of 18MHz and the device is placed in the power
down mode between conversions, then the power con-
sumption is calculated as follows:
Power dissipation during normal operation = 13mW max
(for V
DD
= 5V).
If the power up time is 1 dummy cycle i.e. 1sec, and the
remaining conversion time is another cycle i.e. 1sec, then
the AD7450 can be said to dissipate 13mW for 2sec*
during each conversion cycle.
If the throughput rate = 100kSPS then the cycle time =
10sec and the average power dissipated during each cycle
is:
(2/10) x 13mW = 2.6mW
For the same scenario, if V
DD
= 3V, the power dissipation
during normal operation is 6mW max.
The AD7450 can now be said to dissipate 6mW for 2sec*
during each conversion cycle.
The average power dissipated during each cycle with a
throughput rate of 100kSPS is therefore:
(2/10) x 6mW = 1.2mW
This is how the power numbers in Figure 24 are calcu-
lated.
For throughput rates above 320kSPS, it is recommended
that for optimum power performance, the serial clock fre-
quency is reduced.
*This figure assumes a very small time used to enter the power down
mode. This will increase as the burst of clocks used to enter the power
down mode is increased.
0
50
100
150
200
250
300
350
TH R O U G H PU T (kS P S )
POW
E
R (
m
W
)
V D D = 5V
S C L K = 18M H z
V D D = 3V
S C L K = 15M H z
0.01
0.1
1
10
100
Figure 24. AD7450 Power versus Throughput Rate for
Power Down Mode
REV. PrJ
PRELIMINARY TECHNICAL DATA
2 1
AD7450
MICROPROCESSOR AND DSP INTERFACING
The serial interface on the AD7450 allows the part to be
directly connected to a range of different microproces-
sors. This section explains how to interface the AD7450
with some of the more common microcontroller and DSP
serial interface protocols.
AD7450 to ADSP21xx
The ADSP21xx family of DSPs are interfaced directly to
the AD7450 without any glue logic required.
The SPORT control register should be set up as follows:
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data words
ISCLK = 1, Internal serial clock
TFSR = RFSR = 1, Frame every word
IRFS = 0,
ITFS = 1.
To implement the power-down mode SLEN should be
set to 1001 to issue an 8-bit SCLK burst.
The connection diagram is shown in Figure 25. The
ADSP21xx has the TFS and RFS of the SPORT tied
together, with TFS set as an output and RFS set as an
input. The DSP operates in Alternate Framing Mode and
the SPORT control register is set up as described. The
Frame Synchronisation signal generated on the TFS is
tied to
CS and as with all signal processing applications
equidistant sampling is necessary. However, in this ex-
ample, the timer interrupt is used to control the sampling
rate of the ADC and under certain conditions, equidistant
sampling may not be acheived.
.
AD7450*
SCLK
SDATA
CS
SCLK
DR
RFS
TFS
ADSP21xx*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 25. Interfacing to the ADSP 21xx
AD7450 to TMS320C5x/C54x
The serial interface on the TMS320C5x/C54x uses a
continuous serial clock and frame synchronization signals
to synchronize the data transfer operations with peripheral
devices like the AD7450. The
CS input allows easy
interfacing between the TMS320C5x/C54x and the
AD7450 without any glue logic required. The serial port
of the TMS320C5x/C54x is set up to operate in burst
mode with internal CLKX (TX serial clock) and FSX
(TX frame sync). The serial port control register (SPC)
must have the following setup: FO = 0, FSM = 1, MCM
= 1 and TXM = 1. The format bit, FO, may be set to 1
to set the word length to 8-bits, in order to implement the
power-down mode on the AD7450. The connection dia-
gram is shown in Figure 26. It should be noted that for
signal processing applications, it is imperative that the
frame synchronisation signal from the TMS320C5x/C54x
will provide equidistant sampling.
AD7450*
SCLK
SDATA
CS
CLKX
FSR
TMS320C5x/C54x*
*ADDITIONAL PINS OMITTED FOR CLARITY
CLKR
DR
FSX
Figure 26. Interfacing to the TMS320C5x/C54x
The timer registers etc., are loaded with a value which
will provide an interrupt at the required sample interval.
When an interrupt is received, a value is transmitted with
TFS/DT (ADC control word). The TFS is used to con-
trol the RFS and hence the reading of data. The frequency
of the serial clock is set in the SCLKDIV register. When
the instruction to transmit with TFS is given, (i.e.
AX0=TX0), the state of the SCLK is checked. The DSP
will wait until the SCLK has gone High, Low and High
before transmission will start. If the timer and SCLK val-
ues are chosen such that the instruction to transmit occurs
on or near the rising edge of SCLK, then the data may be
transmitted or it may wait until the next clock edge.
For example, the ADSP-2111 has a master clock fre-
quency of 16MHz. If the SCLKDIV register is loaded
with the value 3 then a SCLK of 2MHz is obtained, and 8
master clock periods will elapse for every 1 SCLK period.
If the timer registers are loaded with the value 803, then
100.5 SCLKs will occur between interrupts and subse-
quently between transmit instructions. This situation will
result in non-equidistant sampling as the transmit instruc-
tion is occuring on a SCLK edge. If the number of
SCLKs between interrupts is a whole integer figure of N
then equidistant sampling will be implemented by the
DSP.
AD7450 to MC68HC16
The Serial Peripheral Interface (SPI) on the MC68HC16
is configured for Master Mode (MSTR = 1), Clock Polar-
ity Bit (CPOL) = 1 and the Clock Phase Bit (CPHA) = 0.
The SPI is configured by writing to the SPI Control Reg-
ister (SPCR) - see 68HC16 user manual. The serial
transfer will take place as a 16-bit operation when the
SIZE bit in the SPCR register is set to SIZE = 1. To
implement the power-down modes with an 8-bit transfer
set SIZE = 0. A connection diagram is shown in figure
27.
REV. PrJ
PRELIMINARY TECHNICAL DATA
2 2
AD7450
AD7450*
SDATA
CS
*
*ADDITIONAL PINS OMITTED FOR CLARITY
MISO/PMC0
SCLK/PMC2
SCLK
SS/PMC3
MC68HC16*
Figure 27. Interfacing to the MC68HC16
AD7450 to DSP56xxx
The connection diagram in figure 28 shows how the
AD7450 can be connected to the SSI (Synchronous Serial
Interface) of the DSP56xxx family of DSPs from
Motorola. The SSI is operated in Synchronous Mode
(SYN bit in CRB =1) with internally generated 1-bit clock
period frame sync for both Tx and Rx (bits FSL1 =1 and
FSL0 =0 in CRB). Set the word length to 16 by setting
bits WL1 =1 and WL0 = 0 in CRA. To implement the
power-down mode on the AD7450 then the word length
can be changed to 8 bits by setting bits WL1 = 0 and WL0
= 0 in CRA. It should be noted that for signal processing
applications, it is imperative that the frame
synchronisation signal from the DSP56xxx will
provideequidistant sampling.
AD7450*
SDATA
CS
*
*ADDITIONAL PINS OMITTED FOR CLARITY
SRD
SCLK
SCLK
SR2
DSP56xxx*
Figure 28. Interfacing to the DSP56xx
REV. PrJ
PRELIMINARY TECHNICAL DATA
2 3
AD7450
APPLICATION HINTS
Grounding and Layout
The printed circuit board that houses the AD7450 should
be designed so that the analog and digital sections are
separated and confined to certain areas of the board. This
facilitates the use of ground planes that can be easily sepa-
rated. A minimum etch technique is generally best for
ground planes as it gives the best shielding. Digital and
analog ground planes should be joined in only one place
and the connection should be a star ground point estab-
lished as close to the GND pin on the AD7450 as
possible. Avoid running digital lines under the device as
this will couple noise onto the die. The analog ground
plane should be allowed to run under the AD7450 to
avoid noise coupling. The power supply lines to the
AD7450 should use as large a trace as possible to provide
low impedance paths and reduce the effects of glitches on
the power supply line.
Fast switching signals like clocks should be shielded with
digital ground to avoid radiating noise to other sections
of the board, and clock signals should never run near the
analog inputs. Avoid crossover of digital and analog sig-
nals. Traces on opposite sides of the board should run at
right angles to each other. This will reduce the effects of
feedthrough through the board. A microstrip technique is
by far the best but is not always possible with a double-
sided board.
In this technique the component side of the board is dedi-
cated to ground planes while signals are placed on the
solder side.
Good decoupling is also important. All analog supplies
should be decoupled with 10F tantalum capacitors in
parallel with 0.1F capacitors to GND. To achieve the
best from these decoupling components, they must be
placed as close as possible to the device.
EVALUATING THE AD7450 PERFORMANCE
The recommended layout for the AD7450 is outlined in
the evaluation board for the AD7450. The evaluation
board package includes a fully assembled and tested evalu-
ation board, documentation and software for controlling
the board from a PC via the EVALUATION BOARD
CONTROLLER. The EVALUATION BOARD CON-
TROLLER can be used in conjunction with the AD7450
evaluation board, as well as many other Analog Devices'
evaluation boards ending with the CB designator, to dem-
onstrate/evaluate the ac and dc performance of the
AD7450.
The software allows the user the perform ac (fast Fourier
Transform) and dc (Histogram of codes) tests on the
AD7450.
REV. PrJ
PRELIMINARY TECHNICAL DATA
2 4
AD7450
0 .1 968 (5.0 0)
0 .1 890 (4.8 0)
8
5
4
1
0 .2 440 (6.20)
0 .2 284 (5.80)
PIN 1
0 .1 574 (4.00)
0 .1 497 (3.80)
0 .0 688 (1.75)
0 .0 532 (1.35)
SEATING
PL ANE
0 .0 098 (0.25)
0 .0 040 (0.10)
0 .0192 (0.4 9)
0 .0138 (0.3 5)
0 .0 500
(1 .27)
BSC
0.0 098 (0.2 5)
0.0 075 (0.1 9)
0.0 500 (1.2 7)
0.0 160 (0.4 1)
8
0
0 .0196 (0.5 0)
0 .0099 (0.2 5)
x 45
8-lead SOIC (SO-8)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-lead microSOIC (RM-8)
8
5
4
1
0 .1 22 (3.10)
0 .1 14 (2.90)
0 .199 (5.05)
0 .187 (4.75)
PIN 1
0.0 256 (0 .65) BSC
0 .1 22 (3.1 0)
0 .1 14 (2.9 0)
SEATING
PL AN E
0 .0 06 (0.15)
0 .0 02 (0.05)
0 .018 (0.46)
0 .008 (0.20)
0 .0 43 (1.09)
0 .0 37 (0.94)
0 .1 20 (3.05)
0 .1 12 (2.84)
0 .0 11 (0.28)
0 .0 03 (0.08)
0 .0 28 (0.71)
0 .0 16 (0.41)
33
27
0 .1 20 (3.05)
0 .1 12 (2.84)