Document Outline
- FEATURES
- APPLICATIONS
- PRODUCT DESCRIPTION
- FUNCTIONAL BLOCK DIAGRAM
-
-
-
-
-
-
-
-
Multirate to 2.7 Gb/s Clock and Data
Recovery IC with Integrated Limiting Amp
ADN2819
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
FEATURES
Meets SONET requirements for jitter
transfer/generation/tolerance
Quantizer sensitivity: 4 mV typical
Adjustable slice level: 100 mV
1.9 GHz minimum bandwidth
Patented clock recovery architecture
Loss of signal detect range: 3 mV to 15 mV
Single reference clock frequency for all rates, including
15/14 (7%) wrapper rate
Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz
REFCLK
LVPECL/LVDS/LVCMOS/LVTTL compatible inputs
(LVPECL/LVDS only at 155.52 MHz)
19.44 MHz oscillator on-chip to be used with external crystal
Loss of lock indicator
Loopback mode for high speed test data
Output squelch and bypass features
Single-supply operation: 3.3 V
Low power: 540 mW typical
7 mm 7 mm 48-lead LFCSP
APPLICATIONS
SONET OC-3/-12/-48, SDH STM-1/-4/-16, GbE and 15/14
FEC rates
WDM transponders
Regenerators/repeaters
Test equipment
Backplane applications
PRODUCT DESCRIPTION
The ADN2819 provides the receiver functions of quantization,
signal level detect, and clock and data recovery at rates of OC-3,
OC-12, OC-48, Gigabit Ethernet, and 15/14 FEC rates. All
SONET jitter requirements are met, including jitter transfer,
jitter generation, and jitter tolerance. All specifications are
quoted for 40C to +85C ambient temperature, unless
otherwise noted.
The device is intended for WDM system applications, and can
be used with either an external reference clock or an on-chip
oscillator with external crystal. Both native rates and 15/14 rate
digital wrappers are supported by the ADN2819, without any
change of reference clock.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power, fiber
optic receiver.
The receiver front end signal detect circuit indicates when the
input signal level has fallen below a user-adjustable threshold.
The signal detect circuit has hysteresis to prevent chatter at the
output.
The ADN2819 is available in a compact 7 mm 7 mm, 48-lead
chip scale package.
FUNCTIONAL BLOCK DIAGRAM
LEVEL
DETECT
DATA
RETIMING
DIVIDER
1/2/4/16
FRACTIONAL
DIVIDER
FREQUENCY
LOCK
DETECTOR
LOOP
FILTER
PHASE
SHIFTER
PHASE
DET.
VCO
XTAL
OSC
LOOP
FILTER
QUANTIZER
/n
ADN2819
SLICEP/N
VCC
VEE
CF1
CF2
LOL
REFSEL[0..1]
REFCLKP/N
XO1
XO2
REFSEL
SEL[0..2]
CLKOUTP/N
DATAOUTP/N
SDOUT
THRADJ
VREF
NIN
PIN
2
2
2
2
2
3
02999-0-001
Figure 1.
ADN2819
Rev. B | Page 2 of 24
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Definition of Terms.......................................................................... 9
Maximum, Minimum, and Typical Specifications ................... 9
Input Sensitivity and Input Overdrive....................................... 9
Single-Ended vs. Differential ...................................................... 9
LOS Response Time ................................................................... 10
Jitter Specifications..................................................................... 10
Theory of Operation ...................................................................... 12
Functional Description .................................................................. 14
Multirate Clock and Data Recovery......................................... 14
Limiting Amplifier ..................................................................... 14
Slice Adjust .................................................................................. 14
Loss of Signal (LOS) Detector .................................................. 14
Reference Clock.......................................................................... 14
Lock Detector Operation .......................................................... 15
Squelch Mode ............................................................................. 16
Test Modes: Bypass and Loopback........................................... 16
Applications Information .............................................................. 17
PCB Design Guidelines ............................................................. 17
Choosing AC-Coupling Capacitors ......................................... 19
DC-Coupled Application .......................................................... 20
LOL Toggling During Loss of Input Data............................... 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
5/04--Data Sheet Changed from Rev. A to Rev. B
Updated Format..............................................................Universal
Changes to Specifications ............................................................ 3
Changes to Table 7 and Table 8................................................. 15
Updated Outline Dimensions ................................................... 21
Changes to Ordering Guide ...................................................... 21
1/03--Data Sheet Changed from Rev. 0 to Rev. A
Changes to Table IV ................................................................... 12
Updated OUTLINE DIMENSIONS ........................................ 16
ADN2819
Rev. B | Page 3 of 24
SPECIFICATIONS
Table 1. T
A
= T
MIN
to T
MAX
, VCC = V
MIN
to V
MAX
, VEE = 0 V, C
F
= 4.7 F, SLICEP = SLICEN = VCC, unless otherwise noted.
Parameter
Conditions
Min
Typ
Max
Unit
QUANTIZER--DC CHARACTERISTICS
Input Voltage Range
@ PIN or NIN, dc-coupled
0
1.2
V
Peak-to-Peak Differential Input
2.4
V
Input Common-Mode Level
DC-coupled (See Figure 28)
0.4
V
Differential Input Sensitivity
PIN-NIN, ac-coupled
1
, BER = 1 10
10
4
10
mV p-p
Input Overdrive
See Figure 8
2
5
mV p-p
Input Offset
500
V
Input rms Noise
BER = 1 10
10
244
V rms
QUANTIZER--AC CHARACTERISTICS
Upper 3 dB Bandwidth
1.9
GHz
Small Signal Gain
Differential
54
dB
S11
@ 2.5 GHz
15
dB
Input Resistance
Differential
100
Input Capacitance
0.65
pF
Pulse Width Distortion
2
10
ps
QUANTIZER SLICE ADJUSTMENT
Gain
SLICEPSLICEN = 0.5 V
0.11
0.20
0.30
V/V
Control Voltage Range
SLICEPSLICEN
0.8
+0.8
V
@ SLICEP or SLICEN
1.3
VCC
V
Slice Threshold Offset
1.0
mV
LEVEL SIGNAL DETECT (SDOUT)
Level Detect Range (See Figure 4)
R
THRESH
= 2
9.4
13.3
18.0
mV
R
THRESH
= 20 k
2.5
5.3
7.6
mV
R
THRESH
= 90 k
0.7
3.0
5.2
mV
Response Time
DC-coupled
0.1
0.3
5
s
Hysteresis (Electrical)
OC-48, PRBS 2
23
R
THRESH
= 2 k
5.6
6.6
7.8
dB
R
THRESH
= 20 k
3.9
6.2
8.5
dB
R
THRESH
= 90 k
3.2
6.7
9.9
dB
OC-12, PRBS 2
23
R
THRESH
= 2 k
4.7
6.4
7.8
dB
R
THRESH
= 20 k
1.8
6.0
10.0
dB
R
THRESH
= 90 k
6.3
dB
R
THRESH
= 90 k @ 25C
4.8
6.9
8.9
dB
OC-3, PRBS 2
23
R
THRESH
= 2 k
3.6
6.2
8.5
dB
R
THRESH
= 20 k
5.6
dB
R
THRESH
= 90 k
5.6
dB
R
THRESH
= 90 k @ 25C
3.4
6.6
9.9
dB
OC-48, PRBS 2
7
R
THRESH
= 2 k
5.6
6.6
7.8
dB
R
THRESH
= 20 k
3.9
6.2
8.5
dB
R
THRESH
= 90 k
3.2
6.7
9.9
dB
OC-12, PRBS 2
7
R
THRESH
= 2 k
5.7
6.6
7.8
dB
R
THRESH
= 20 k
3.9
6.2
8.5
dB
R
THRESH
= 90 k
3.2
6.7
9.9
dB
ADN2819
Rev. B | Page 4 of 24
Parameter
Conditions
Min
Typ
Max
Unit
Hysteresis (Electrical) (continued)
OC-3, PRBS 2
7
R
THRESH
= 2 k
5.4
6.6
7.7
dB
R
THRESH
= 20 k
4.6
6.4
8.2
dB
R
THRESH
= 90 k
3.9
6.8
9.7
dB
LOSS OF LOCK DETECTOR (LOL)
Loss of Lock Response Time
From f
VCO
error > 1000 ppm
60
mV
POWER SUPPLY VOLTAGE
3.0
3.3
3.6
V
POWER SUPPLY CURRENT
150
164
215
mA
PHASE-LOCKED LOOP CHARACTERISTICS
PINNIN = 10 mV p-p
Jitter Transfer BW
OC-48
590
880
kHz
GbE
310
480
kHz
OC-12
140
200
kHz
OC-3
48
85
kHz
Jitter Peaking
OC-48
0.025
dB
OC-12
0.004
dB
OC-3
0.002
dB
Jitter Generation
OC-48, 12 kHz20 MHz
0.003
UI rms
0.05
0.09
UI p-p
OC-12, 12 kHz5 MHz
0.002
UI rms
0.02
0.04
UI p-p
OC-3, 12 kHz1.3 MHz
0.002
UI rms
0.02
0.04
UI p-p
Jitter Tolerance
OC-48 (See Figure 14)
600
Hz
3
92
UI p-p
6
kHz
3
20
UI p-p
100 kHz
5.5
UI p-p
1
MHz
3
1.0
UI p-p
GbE (OC-24) (See Figure 14)
300
Hz
3
16
UI p-p
3
kHz
3
16
UI p-p
50 kHz
7.7
UI p-p
500
kHz
3
2.2
UI p-p
OC-12 (See Figure 14)
30
Hz
3
100
UI p-p
300 Hz
44
UI p-p
25 kHz
5.8
UI p-p
250
kHz
3
1.0
UI p-p
OC-3 (See Figure 14)
30
Hz
3
50
UI p-p
300
Hz
3
23.5
UI p-p
6500 Hz
6.0
UI p-p
65
kHz
3
1.0
UI p-p
CML OUTPUTS (CLKOUTP/N, DATAOUTP/N)
Single-Ended Output Swing
V
SE
(See Figure 7)
300
455
600
mV
Differential Output Swing
V
DIFF
(See Figure 7)
600
910
1200
mV
Output High Voltage
V
OH
VCC
V
Output Low Voltage
V
OL
, referred to VCC
0.60
0.30
V
Rise Time
20%80%
150
ps
Fall Time
80%20%
150
ps
ADN2819
Rev. B | Page 5 of 24
Parameter
Conditions
Min
Typ
Max
Unit
Setup Time
T
S
(See Figure 3)
OC-48
140
ps
GbE
350
ps
OC-12
750
ps
OC-3
3145
ps
Hold Time
T
H
(See Figure 3)
OC-48
150
ps
GbE
350
ps
OC-12
750
ps
OC-3
3150
ps
REFCLK DC INPUT CHARACTERISTICS
Input Voltage Range
@ REFCLKP or REFCLKN
0
VCC
V
Peak-to-Peak Differential Input
100
mV
Common-Mode Level
DC-coupled, single-ended
VCC/2
V
TEST DATA DC INPUT CHARACTERISTICS
4
(TDINP/N)
CML inputs
Peak-to-Peak Differential Input Voltage
0.8
V
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage
V
IH
2.0
V
Input Low Voltage
V
IL
0.8
V
Input Current
V
IN
= 0.4 V or V
IN
= 2.4 V
5
+5
A
Input Current (SEL0 and SEL1 Only)
5
V
IN
= 0.4 V or V
IN
= 2.4 V
5
+50
A
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage
V
OH
, I
OH
= 2.0 mA
2.4
V
Output Low Voltage
V
OL
, I
OL
= +2.0 mA
0.4
V
1
PIN and NIN should be differentially driven, ac-coupled for optimum sensitivity.
2
PWD measurement made on quantizer outputs in bypass mode.
3
Jitter tolerance measurements are equipment limited.
4
TDINP/N are CML inputs. If the drivers to the TDINP/N inputs are anything other than CML, they must be ac-coupled.
5
SEL0 and SEL1 have internal pull-down resistors, causing higher I
IH
.
ADN2819
Rev. B | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage (VCC)
5.5 V
Minimum Input Voltage (All Inputs)
VEE 0.4 V
Maximum Input Voltage (All Inputs)
VCC + 0.4 V
Maximum Junction Temperature
165C
Storage Temperature
65C to +150C
Lead Temperature (Soldering 10 sec)
300C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
48-lead LFCSP, 4-layer board with exposed paddle soldered
to VCC
JA
= 25C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADN2819
Rev. B | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
TOPVIEW
ADN2819
THRADJ 1
VCC 2
VEE 3
VREF 4
PIN 5
NIN 6
SLICEP 7
SLICEN 8
VEE 9
LOL 10
XO1 11
XO2 12
RE
FCLKN 1
3
REFCLKP 14
R
E
FSEL 15
VEE 16
TDINP 17
TDINN 1
8
VEE 19 V
CC 2
0
C
F
1 21
VEE 22
R
E
FSEL1 23
R
E
FSEL0 24
36 VCC
35 VCC
34 VEE
33 VEE
32 SEL0
31 SEL1
30 SEL2
29 VEE
28 VCC
27 VEE
26 VCC
25 CF2
48 LOOPEN
47
VC
C
46
VEE
45 SD
OU
T
44 B
Y
PA
SS
43
VEE
42
VEE
4
1
CLK
O
UTP
4
0
CLK
O
UTN
39 SQ
U
E
LC
H
3
8
DATAOUTP
3
7
DATAOUTN
02999-B
-
002
Figure 2. 48-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin Number
Mnemonic
Type
1
Description
1
THRADJ
AI
LOS Threshold Setting Resistor.
2, 26, 28, Pad
VCC
P
Analog Supply.
3, 9, 16, 19, 22, 27,
29, 33, 34, 42, 43, 46
VEE
P
Ground.
4
VREF
AO
Internal VREF Voltage. Decouple to GND with 0.1 F capacitor.
5
PIN
AI
Differential Data Input.
6
NIN
AI
Differential Data Input.
7
SLICEP
AI
Differential Slice Level Adjust Input.
8
SLICEN
AI
Differential Slice Level Adjust Input.
10
LOL
DO
Loss of Lock Indicator. LVTTL active high.
11
XO1
AO
Crystal Oscillator.
12
XO2
AO
Crystal Oscillator.
13
REFCLKN
DI
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz).
14
REFCLKP
DI
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz).
15
REFSEL
DI
Reference Source Select. 0 = on-chip oscillator with external crystal; 1 = external clock source, LVTTL.
17
TDINP
AI
Differential Test Data Input. CML.
18
TDINN
AI
Differential Test Data Input. CML.
20, 47
VCC
P
Digital Supply.
21
CF1
AO
Frequency Loop Capacitor.
23
REFSEL1
DI
Reference Frequency Select (See Table 6) LVTTL.
24
REFSEL0
DI
Reference Frequency Select (See Table 6) LVTTL.
25
CF2
AO
Frequency Loop Capacitor.
30
SEL2
DI
Data Rate Select (See Table 5) LVTTL.
31
SEL1
DI
Data Rate Select (See Table 5) LVTTL.
32
SEL0
DI
Data Rate Select (See Table 5) LVTTL.
35, 36
VCC
P
Output Driver Supply.
37
DATAOUTN
DO
Differential Retimed Data Output. CML.
38
DATAOUTP
DO
Differential Retimed Data Output. CML.
39
SQUELCH
DI
Disable Clock and Data Outputs. Active high. LVTTL.
40
CLKOUTN
DO
Differential Recovered Clock Output. CML.
41
CLKOUTP
DO
Differential Recovered Clock Output. CML.
44
BYPASS
DI
Bypass CDR Mode. Active high. LVTTL.
45
SDOUT
DO
Loss of Signal Detect Output. Active high. LVTTL.
48
LOOPEN
DI
Enable Test Data Inputs. Active high. LVTTL.
1
Type: P = Power, AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output.
ADN2819
Rev. B | Page 8 of 24
T
S
T
H
CLKOUTP
DATAOUTP/N
02999-B
-
003
Figure 3. Output Timing
RESISTANCE (k
)
0
100
18
16
0
mV
8
6
4
2
12
10
14
THRADJ RESISTOR VS. LOS TRIP POINT
10
20
30
40
50
60
70
80
90
02999-B
-
004
Figure 4. LOS Comparator Trip Point Programming
0
1
1
2
3
4
5
6
7
8
9
02999-B
-
005
0
HYSTERESIS (dB)
10
9
0
FRE
Q
UE
NCY
5
4
3
2
7
6
8
1
Figure 5. LOS Hysteresis OC-3, 40C, 3.6 V,
2
23
1 PRBS Input Pattern, R
TH
= 90 k
HYSTERESIS (dB)
18
16
0
FRE
Q
UE
NCY
8
6
4
2
12
10
14
02999-B
-
006
0
1
1
2
3
4
5
6
7
8
9
0
Figure 6. LOS Hysteresis OC-12, 40C, 3.6 V,
2
23
1 PRBS Input Pattern, R
TH
= 90 k
OUTP
OUTN
V
SE
V
CML
0V
OUTPOUTN
V
SE
V
DIFF
02999-B
-
007
Figure 7. Single-Ended vs. Differential Output Specifications
ADN2819
Rev. B | Page 9 of 24
DEFINITION OF TERMS
MAXIMUM, MINIMUM, AND TYPICAL
SPECIFICATIONS
Specifications for every parameter are derived from statistical
analyses of data taken on multiple devices from multiple wafer
lots. Typical specifications are the mean of the distribution of
the data for that parameter. If a parameter has a maximum (or a
minimum), that value is calculated by adding to (or subtracting
from) the mean six times the standard deviation of the
distribution. This procedure is intended to tolerate production
variations. If the mean shifts by 1.5 standard deviations, the
remaining 4.5 standard deviations still provide a failure rate of
only 3.4 parts per million. For all tested parameters, the test
limits are guardbanded to account for tester variation and
therefore guarantee that no device is shipped outside of data
sheet specifications.
INPUT SENSITIVITY AND INPUT OVERDRIVE
Sensitivity and overdrive specifications for the quantizer involve
offset voltage, gain, and noise. The relationship between the
logic output of the quantizer and the analog voltage input is
shown in Figure 8. For a sufficiently large positive input voltage,
the output is always Logic 1; similarly for negative inputs, the
output is always Logic 0. However, the transitions between
output Logic Levels 1 and 0 are not at precisely defined input
voltage levels, but occur over a range of input voltages. Within
this zone of confusion, the output may be either 1 or 0, or it may
even fail to attain a valid logic state. The width of this zone is
determined by the input voltage noise of the quantizer. The
center of the zone of confusion is the quantizer input offset
voltage. Input overdrive is the magnitude of signal required to
guarantee the correct logic level with 1 10
10
confidence level.
0
1
INPUT (V p-p)
OUTPUT
NOISE
SENSITIVITY
(2
OVERDRIVE)
OFFSET
OVERDRIVE
02999-B
-
008
Figure 8. Input Sensitivity and Input Overdrive
SINGLE-ENDED VS. DIFFERENTIAL
AC-coupling is typically used to drive the inputs to the
quantizer. The inputs are internally dc biased to a common-
mode potential of ~0.6 V. Driving the ADN2819 single-ended
and observing the quantizer input with an oscilloscope probe at
the point indicated in Figure 9 shows a binary signal with an
average value equal to the common-mode potential and
instantaneous values above and below the average value. It is
convenient to measure the peak-to-peak amplitude of this
signal and to call the minimum required value the quantizer
sensitivity. Referring to Figure 8, since both positive and
negative offsets need to be accommodated, the sensitivity is
twice the overdrive.
50
50
QUANTIZER
+
ADN2819
VREF
PIN
SCOPE
PROBE
VREF
10mV p-p
02999-B
-
009
Figure 9. Single-Ended Sensitivity Measurement
50
50
QUANTIZER
+
ADN2819
VREF
NIN
PIN
SCOPE
PROBE
VREF
5mV p-p
02999-B
-
010
Figure 10. Differential Sensitivity Measurement
Driving the ADN2819 differentially (see Figure 10), sensitivity
seems to improve by observing the quantizer input with an
oscilloscope probe. This is an illusion caused by the use of a
single-ended probe. A 5 mV p-p signal appears to drive the
ADN2819 quantizer. However, the single-ended probe measures
only half the signal. The true quantizer input signal is twice this
value since the other quantizer input is complementary to the
signal being observed.
ADN2819
Rev. B | Page 10 of 24
LOS RESPONSE TIME
The LOS response time is the delay between the removal of the
input signal and indication of loss of signal (LOS) at SDOUT.
The ADN2819's response time is 300 ns typ when the inputs are
dc-coupled. In practice, the time constant of ac-coupling at the
quantizer input determines the LOS response time.
JITTER SPECIFICATIONS
The ADN2819 CDR is designed to achieve the best bit-error-
rate (BER) performance, and has exceeded the jitter transfer,
generation, and tolerance specifications proposed for
SONET/SDH equipment defined in the Telcordia Technologies
specification.
Jitter is the dynamic displacement of digital signal edges from
their long-term average positions measured in UI (unit
intervals), where 1 UI = 1 bit period. Jitter on the input data
can cause dynamic phase errors on the recovered clock
sampling edge. Jitter on the recovered clock causes jitter on the
retimed data.
The following sections summarize the specifications of the jitter
generation, transfer, and tolerance in accordance with the
Telcordia document (GR-253-CORE, Issue 3, September 2000)
for the optical interface at the equipment level, and the
ADN2819 performance with respect to those specifications.
Jitter Generation
Jitter generation specification limits the amount of jitter that
can be generated by the device with no jitter and wander
applied at the input. For OC-48 devices, the band-pass filter has
a 12 kHz high-pass cutoff frequency, with a roll-off of
20 dB/decade and a low-pass cutoff frequency of at least
20 MHz. The jitter generated should be less than 0.01 UI rms
and 0.1 UI p-p.
Jitter Transfer
Jitter transfer function is the ratio of the jitter on the output
signal to the jitter applied on the input signal versus the
frequency. This parameter measures the limited amount of jitter
on an input signal that can be transferred to the output signal
(see Figure 11).
SLOPE = 20dB/DECADE
JITTER FREQUENCY (kHz)
0.1
J
I
TTE
R GAIN (dB)
f
C
ACCEPTABLE
RANGE
02999-B
-
011
Figure 11. Jitter Transfer Curve
Jitter Tolerance
Jitter tolerance is defined as the peak-to-peak amplitude of the
sinusoidal jitter applied on the input signal that causes a 1 dB
power penalty. This is a stress test that is intended to ensure no
additional penalty is incurred under the operating conditions
(see Figure 12). Figure 13 shows the typical OC-48 jitter
tolerance performance of the ADN2819.
SLOPE = 20dB/DECADE
f
0
f
1
f
2
f
3
f
4
JITTER FREQUENCY (Hz)
15
1.5
0.15
I
N
P
U
T J
I
TTE
R AMP
L
I
T
UDE
(UI
)
02999-B
-
012
Figure 12. SONET Jitter Tolerance Mask
MODULATION FREQUENCY (Hz)
10
1k
100k
10M
100
10
0.1
A
M
P
L
ITUDE
(UI
p
-
p
)
1
100
10k
1M
1
ADN2819
OC-48 SONET MASK
02999-B
-
013
Figure 13. OC-48 Jitter Tolerance Curve
ADN2819
Rev. B | Page 11 of 24
0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
9.0
9.5
10.0
8.5
1k
10k
100k
1M
100M
FREQUENCY (Hz)
10M
OC3_JIT_TOLERANCE
GBE_JIT_TOLERANCE
OC3_JIT_TRANSFER
GBE_JIT_TRANSFER
OC12_JIT_TOLERANCE
OC48_JIT_TOLERANCE
OC12_JIT_TRANSFER
OC48_JIT_TRANSFER
02999-B
-
014
Figure 14. Jitter Transfer and Jitter Tracking BW
Table 4. Jitter Transfer and Tolerance: SONET Spec vs. ADN2819
Jitter Transfer
Jitter Tolerance
Rate
SONET Spec (f
C
)
ADN2819
(kHz)
Implementation
Margin
Mask Corner
Frequency
ADN2819
SONET Spec
(UI p-p)
ADN2819
(UI p-p)
Implementation
Margin
1
OC-48 2 MHz
590
3.4
1 MHz
4.8 MHz
0.15
1.0
6.67
OC-12
500 kHz
140
3.6
250 kHz
4.8 MHz
0.15
1.0
6.67
OC-3
130 kHz
48
2.7
65 kHz
600 kHz
0.15
1.0
6.67
1
Jitter tolerance measurements limited by test equipment capabilities.
ADN2819
Rev. B | Page 12 of 24
THEORY OF OPERATION
The ADN2819 is a delay-locked and phase-locked loop circuit
for clock recovery and data retiming from an NRZ encoded
data stream. The phase of the input data signal is tracked by two
separate feedback loops that share a common control voltage. A
high speed delay-locked loop path uses a voltage controlled
phase shifter to track the high frequency components of the
input jitter. A separate phase control loop, comprised of the
VCO, tracks the low frequency components of the input jitter.
The initial frequency of the VCO is set by a third loop that
compares the VCO frequency with the reference frequency and
sets the coarse tuning voltage. The jitter tracking phase-locked
loop controls the VCO by the fine tuning control.
The delay- and phase-locked loops together track the phase of
the input data signal. For example, when the clock lags input
data, the phase detector drives the VCO to a higher frequency
and increases the delay through the phase shifter. Both of these
actions serve to reduce the phase error between the clock and
data. The faster clock picks up phase while the delayed data
loses phase. Since the loop filter is an integrator, the static phase
error is driven to zero.
Another view of the circuit is that the phase shifter implements
the zero required for the frequency compensation of a second-
order phase-locked loop. This zero is placed in the feedback
path and therefore does not appear in the closed-loop transfer
function. Jitter peaking in a conventional second-order phase-
locked loop is caused by the presence of this zero in the closed-
loop transfer function. Since this circuit has no zero in the
closed-loop transfer, jitter peaking is minimized.
The delay- and phase-locked loops together simultaneously
provide wideband jitter accommodation and narrow-band jitter
filtering. The linearized block diagram in Figure 15 shows that
the jitter transfer function, Z(s)/X(s), is a second-order low-pass
providing excellent filtering. Note that the jitter transfer has no
zero, unlike an ordinary second-order phase-locked loop. This
means the main PLL loop has low jitter peaking (see Figure 16),
which makes this circuit ideal for signal regenerator applica-
tions where jitter peaking in a cascade of regenerators can
contribute to hazardous jitter accumulation.
d/sc
o/s
psh
1/n
e(s)
X(s)
INPUT
DATA
Z(s)
RECOVERED
CLOCK
d = PHASE DETECTOR GAIN
o = VCO GAIN
c = LOOP INTEGRATOR
psh = PHASE SHIFTER GAIN
n = DIVIDE RATIO
JITTER TRANSFER FUNCTION
Z(s)
X(s)
1
s
2
+ s +1
cn
do
n psh
o
=
TRACKING ERROR TRANSFER FUNCTION
e(s)
X(s)
s
2
s
2
+ s
+
do
cn
d psh
c
=
02999-B
-
015
Figure 15. PLL/DLL Architecture
The error transfer, e(s)/X(s), has the same high-pass form as an
ordinary phase-locked loop. This transfer function is free to be
optimized to give excellent wideband jitter accommodation
since the jitter transfer function, Z(s)/X(s), provides the narrow-
band jitter filtering. See Table 4 for error transfer bandwidths
and jitter transfer bandwidths at the various data rates.
The delay-locked and phase-locked loops contribute to overall
jitter accommodation. At low frequencies of input jitter on the
data signal, the integrator in the loop filter provides high gain to
track large jitter amplitudes with small phase error. In this case,
the VCO is frequency modulated, and jitter is tracked as in an
ordinary phase-locked loop. The amount of low frequency jitter
that can be tracked is a function of the VCO tuning range. A
wider tuning range gives larger accommodation of low
frequency jitter. The internal loop control voltage remains small
for small phase errors, so the phase shifter remains close to the
center of its range, and therefore contributes little to the low
frequency jitter accommodation.
At medium jitter frequencies, the gain and tuning range of the
VCO are not large enough to track the input jitter. In this case,
the VCO control voltage becomes large and saturates, and the
VCO frequency dwells at one or the other extreme of its tuning
range. The size of the VCO tuning range therefore has only a
small effect on the jitter accommodation. The delay-locked loop
control voltage is now larger; thus, the phase shifter takes on the
burden of tracking the input jitter. The phase shifter range, in
UI, can be seen as a broad plateau on the jitter tolerance curve.
The phase shifter has a minimum range of 2 UI at all data rates.
ADN2819
Rev. B | Page 13 of 24
The gain of the loop integrator is small for high jitter
frequencies, so larger phase differences are needed to make the
loop control voltage big enough to tune the range of the phase
shifter. Large phase errors at high jitter frequencies cannot be
tolerated. In this region, the gain of the integrator determines
the jitter accommodation. Since the gain of the loop integrator
declines linearly with frequency, jitter accommodation is lower
with higher jitter frequency. At the highest frequencies, the loop
gain is very small and little tuning of the phase shifter can be
expected. In this case, jitter accommodation is determined by
the eye opening of the input data, the static phase error, and the
residual loop jitter generation. The jitter accommodation is
roughly 0.5 UI in this region. The corner frequency between the
declining slope and the flat region is the closed-loop bandwidth
of the delay-locked loop, which is roughly 5 MHz for OC-12,
OC-48, and GbE data rates, and 600 kHz for OC-3 data rates.
JITTER PEAKING
IN ORDINARY PLL
ADN2819
Z(s)
X(s)
f
(kHz)
JITTER
GAIN
(dB)
o
n psh
d psh
c
02999-B
-
016
Figure 16. Jitter Response vs. Conventional PLL
ADN2819
Rev. B | Page 14 of 24
FUNCTIONAL DESCRIPTION
MULTIRATE CLOCK AND DATA RECOVERY
The ADN2819 will recover clock and data from serial bit
streams at OC-3, OC-12, OC-48, and GbE data rates as well as
the 15/14 FEC rates. The output of the 2.5 GHz VCO is divided
down in order to support the lower data rates. The data rate is
selected by the SEL[2..0] inputs (see Table 5).
Table 5. Data Rate Selection
SEL[2..0] Rate
Frequency
(MHz)
000 OC-48 2488.32
001 GbE 1250.00
010 OC-12 622.08
011 OC-3 155.52
100 OC-48
FEC
2666.06
101 GbE
FEC
1339.29
110 OC-12
FEC
666.51
111 OC-3
FEC
166.63
LIMITING AMPLIFIER
The limiting amplifier has differential inputs (PIN/NIN) that
are internally terminated with 50 to an on-chip voltage
reference (VREF = 0.6 V typically). These inputs are normally
ac-coupled, although dc-coupling is possible as long as the input
common-mode voltage remains above 0.4 V (see Figure 26,
Figure 27, and Figure 28 in the Applications Information
section). Input offset is factory trimmed to achieve better than
4 mV typical sensitivity with minimal drift. The limiting
amplifier can be driven differentially or single-ended.
SLICE ADJUST
The quantizer slicing level can be offset by 100 mV to mitigate
the effect of amplified spontaneous emission (ASE) noise by
applying a differential voltage input of 0.8 V to SLICEP/N
inputs. If no adjustment of the slice level is needed, SLICEP/N
should be tied to VCC.
LOSS OF SIGNAL (LOS) DETECTOR
The receiver front end level signal detect circuit indicates when
the input signal level has fallen below a user adjustable
threshold. The threshold is set with a single external resistor
from Pin 1, THRADJ, to GND. The LOS comparator trip point
versus the resistor value is illustrated in Figure 4 (this is only
valid for SLICEP = SLICEN = VCC). If the input level to the
ADN2819 drops below the programmed LOS threshold,
SDOUT (Pin 45) will indicate the loss of signal condition with a
Logic 1. The LOS response time is ~300 ns by design, but it is
dominated by the RC time constant in ac-coupled applications.
If the LOS detector is used, the quantizer slice adjust pins must
both be tied to VCC. This is to avoid interaction with the LOS
threshold level.
Note that it is not expected to use both LOS and slice adjust at
the same time. Systems with optical amplifiers need the slice
adjust to evade ASE. However, a loss of signal in an optical link
that uses optical amplifiers causes the optical amplifier output
to be full-scale noise. Under this condition, the LOS would not
detect the failure. In this case, the loss of lock signal indicates
the failure because the CDR circuitry is unable to lock onto a
signal that is full-scale noise.
REFERENCE CLOCK
There are three options for providing the reference frequency to
the ADN2819: differential clock, single-ended clock, or crystal
oscillator. See Figure 17, Figure 18, and Figure 19 for example
configurations.
100k
100k
BUFFER
ADN2819
VCC/2
REFCLKN
REFCLKP
CRYSTAL
OSCILLATOR
XO1
XO2
VCC
VCC
VCC
REFSEL
02999-B
-
017
Figure 17. Differential REFCLK Configuration
OUT
100k
100k
BUFFER
ADN2819
VCC/2
REFCLKN
REFCLKP
CRYSTAL
OSCILLATOR
XO1
XO2
VCC
VCC
VCC
REFSEL
CLK
OSC
VCC
NC
02999-B
-
018
Figure 18. Single-Ended REFCLK Configuration
ADN2819
Rev. B | Page 15 of 24
100k
100k
BUFFER
ADN2819
VCC/2
REFCLKN
REFCLKP
CRYSTAL
OSCILLATOR
XO1
XO2
REFSEL
NC
19.44MHz
VCC
02999-B
-
019
Figure 19. Crystal Oscillator Configuration
The ADN2819 can accept any of the following reference clock
frequencies: 19.44 MHz, 38.88 MHz, and 77.76 MHz at LVTTL/
LVCMOS/LVPECL/LVDS levels, or 155.52 MHz at LVPECL/
LVDS levels via the REFCLKN/P inputs, independent of data
rate (including Gigabit Ethernet and wrapper rates). The input
buffer accepts any differential signal with a peak-to-peak
differential amplitude of greater than 100 mV (e.g., LVPECL or
LVDS) or a standard single-ended low voltage TTL input,
providing maximum system flexibility. The appropriate division
ratio can be selected using the REFSEL0/1 pins, according to
Table 6. Phase noise and duty cycle of the reference clock are
not critical, and 100 ppm accuracy is sufficient.
Table 6. Reference Frequency Selection
REFSEL REFSEL[1..0]
Applied Reference Frequency
(MHz)
1
00
19.44
1
01
38.88
1
10
77.76
1
11
155.52
0
XX
REFCLKP/N Inactive. Use 19.44 MHz
XTAL on Pins XO1, XO2 (pull REFCLKP
to VCC)
An on-chip oscillator to be used with an external crystal is also
provided as an alternative to using the REFCLKN/P inputs.
Details of the recommended crystal are given in Table 7.
Table 7. Required Crystal Specifications
Parameter
Value
Mode
Series Resonant
Frequency/Overall Stability
19.44 MHz 100 ppm
Frequency Accuracy
100 ppm
Temperature Stability
100 ppm
Aging
100 ppm
ESR
50 max
REFSEL must be tied to VCC when the REFCLKN/P inputs are
active, or tied to VEE when the oscillator is used. No connection
between the XO pin and the REFCLK input is necessary (see
Figure 17, Figure 18, and Figure 19). Note that the crystal should
operate in series resonant mode, which renders it insensitive to
external parasitics. No trimming capacitors are required.
LOCK DETECTOR OPERATION
The lock detector monitors the frequency difference between
the VCO and the reference clock, and deasserts the loss of lock
signal when the VCO is within 500 ppm of center frequency.
This enables the phase loop, which then maintains phase lock,
unless the frequency error exceeds 0.1%. Should this occur, the
loss of lock signal is reasserted and control returns to the fre-
quency loop, which will reacquire and maintain a stable clock
signal at the output. The frequency loop requires a single exter-
nal capacitor between CF1 and CF2. The capacitor specification
is given in Table 8.
Table 8. Recommended C
F
Capacitor Specification
Parameter
Value
Temperature Range
40C to +85C
Capacitance
>3.0 F
Leakage
<80 nA
Rating
>6.3 V
1000
500
0
500
1000
f
VCO
ERROR
(ppm)
LOL
1
02999-B
-
020
Figure 20. Transfer Function LOL
ADN2819
Rev. B | Page 16 of 24
50
50
QUANTIZER
+
ADN2819
VREF
NIN
PIN
50
50
VCC
TDINP/N
LOOPEN BYPASS
CDR
RETIMED
DATA
CLK
0
1
1
0
DATAOUTP/N
CLKOUTP/N SQUELCH
FROM
QUANTIZER
OUTPUT
02999-B
-
021
Figure 21. Test Modes
SQUELCH MODE
When the squelch input is driven to a TTL high state, the clock
and data outputs are set to the zero state to suppress down-
stream processing. If desired, this pin can be directly driven by
the LOS (loss of signal) detector output (SDOUT). If the
squelch function is not required, the pin should be tied to VEE.
TEST MODES: BYPASS AND LOOPBACK
When the bypass input is driven to a TTL high state, the
quantizer output is connected directly to the buffers driving the
data out pins, thus bypassing the clock recovery circuit (see
Figure 21). This feature can help the system deal with
nonstandard bit rates.
The loopback mode can be invoked by driving the LOOPEN
pin to a TTL high state, which facilitates system diagnostic
testing. This connects the test inputs (TDINP/N) to the clock
and data recovery circuit (per Figure 21). The test inputs have
internal 50 terminations, and can be left floating when not in
use. TDINP/N are CML inputs and can only be dc-coupled
when being driven by CML outputs. The TDINP/N inputs must
be ac-coupled if driven by anything other than CML outputs.
Bypass and loopback modes are mutually exclusive: only one of
these modes can be used at any given time. The ADN2819 is put
into an indeterminate state if both the BYPASS and LOOPEN
pins are set to Logic 1 at the same time.
ADN2819
Rev. B | Page 17 of 24
APPLICATIONS INFORMATION
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal
performance.
Power Supply Connections and Ground Planes
Use of one low impedance ground plane to both analog and
digital grounds is recommended. The VEE pins should be
soldered directly to the ground plane to reduce series
inductance. If the ground plane is an internal plane and
connections to the ground plane are made through vias,
multiple vias may be used in parallel to reduce the series
inductance, especially on Pins 33 and 34, which are the ground
returns for the output buffers.
Use of a 10 F electrolytic capacitor between VCC and GND is
recommended at the location where the 3.3 V supply enters the
PCB. Use of 0.1 F and 1 nF ceramic chip capacitors should be
placed between IC power supply VCC and GND as close as
possible to the ADN2819 VCC pins. Again, if connections to the
supply and ground are made through vias, the use of multiple
vias in parallel will help to reduce series inductance, especially
on Pins 35 and 36, which supply power to the high speed
CLKOUTP/N and DATAOUTP/N output buffers. Refer to the
schematic in Figure 22 for recommended connections.
Transmission Lines
Use of 50 transmission lines are required for all high
frequency input and output signals to minimize reflections,
including PIN, NIN, CLKOUTP, CLKOUTN, DATAOUTP, and
DATAOUTN (also REFCLKP/N for a 155.52 MHz REFCLK). It
is also recommended that the PIN/NIN input traces are
matched in length and that the CLKOUTP/N and
DATAOUTP/N traces are matched in length. All high speed
CML outputs, CLKOUTP/N and DATAOUTP/N, also require
100 back termination chip resistors connected between the
output pin and VCC. These resistors should be placed as close
as possible to the output pins. These 100 resistors are in
parallel with on-chip 100 termination resistors to create a
50 back termination (see Figure 23).
The high speed inputs, PIN and NIN, are internally terminated
with 50 to an internal reference voltage (see Figure 24). A
0.1 F capacitor is recommended between VREF, Pin 4, and
GND to provide an ac ground for the inputs.
As with any high speed mixed-signal design, take care to keep
all high speed digital traces away from sensitive analog nodes.
Soldering Guidelines for Chip Scale Package
The lands on the 48-lead LFCSP are rectangular. The printed
circuit board pad for these should be 0.1 mm longer than the
package land length and 0.05 mm wider than the package land
width. The land should be centered on the pad. This ensures
that the solder joint size is maximized. The bottom of the chip
scale package has a central exposed pad. The pad on the printed
circuit board should be at least as large as this exposed pad. The
user must connect the exposed pad to analog VCC. If vias are
used, they should be incorporated into the pad at 1.2 mm pitch
grid. The via diameter should be between 0.3 mm and 0.33 mm;
the via barrel should be plated with 1 oz. copper to plug the via.
ADN2819
Rev. B | Page 18 of 24
ADN2819
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
36
35
34
33
32
31
30
29
28
27
26
25
48 47 46 45 44 43 42 41 40 39 38 37
1nF
0.1
F
1nF
0.1
F
THRADJ
VCC
VEE
VREF
PIN
NIN
SLICEP
SLICEN
VEE
LOL
XO1
XO2
VCC
C
IN
50
R
TH
1nF
0.1
F
0.1
F
50
TIA
VCC
19.44MHz
C
REFCLKN
REFCLKP
R
E
FSEL
VEE
TDINP
TDINN
VEE
VC
C
CF1
VEE
R
E
FSEL1
R
E
FSEL0
NC
VC
C
NC
NC
C
C
4.7
F
(SEE TABLE 8 FOR SPECS)
1nF
0.1
F
VCC
VCC
VCC
VEE
VEE
SEL0
SEL1
SEL2
VEE
VCC
VEE
VCC
CF2
C
VCC
LOOPEN
VC
C
VEE
SD
OU
T
B
YPA
SS
VEE
VEE
CLK
O
UTP
CLK
O
UTN
SQ
U
E
LC
H
DATAOUTP
DATAOUTN
C
1nF
0.1
F
10
F
VCC
50
TRANSMISSION
LINES
CLKOUTP
CLKOUTN
DATAOUTP
DATAOUTN
VCC
4
100
EXPOSED PAD
TIED OFF TO
VCC PLANE
WITH VIAS
1nF
0.1
F
VCC
02999-B
-
022
Figure 22. Typical Application Circuit
100
50
ADN2819
50
50
100
VCC
100
100
VCC
0.1
F
0.1
F
50
V
TERM
V
TERM
02999-B
-
023
Figure 23. AC-Coupled Output Configuration
50
50
ADN2819
0.1
F
NIN
PIN
C
IN
C
IN
50
TIA
VREF
VCC
50
02999-B
-
024
Figure 24. AC-Coupled Input Configuration
ADN2819
Rev. B | Page 19 of 24
CHOOSING AC-COUPLING CAPACITORS
The choice of ac-coupling capacitors at the input (PIN, NIN)
and output (DATAOUTP, DATAOUTN) of the ADN2819 must
be chosen such that the device works properly at the lower
OC-3 and higher OC-48 data rates. When choosing the
capacitors, the time constant formed with the two 50 resistors
in the signal path must be considered. When a large number of
consecutive identical digits (CIDs) are applied, the capacitor
voltage can drop due to baseline wander (see Figure 23), causing
pattern dependent jitter (PDJ).
For the ADN2819 to work robustly at both OC-3 and OC-48, a
minimum capacitor of 1.6 F to PIN/NIN and 0.1 F on
DATAOUTP/DATAOUTN should be used. This is based on the
assumption that 1000 CIDs must be tolerated and that the PDJ
should be limited to 0.01 UI p-p.
50
ADN2819
NIN
PIN
50
V
REF
C
IN
C
IN
V2
V1
V2b
V1b
TIA
LIMAMP
CDR
C
OUT
C
OUT
DATAOUTP
DATAOUTN
+
4
3
2
1
V1
V1b
V2
V2b
V
DIFF
V
DIFF
= V2V2b
VTH = ADN2819 QUANTIZER THRESHOLD
V
REF
VTH
NOTES
1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS 0.
2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE V
REF
LEVEL,
WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.
3. WHEN THE BURST OF DATA STARTS AGAIN,THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO THE INPUT LEVELS,
CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES, EITHER HIGH OR LOW DEPENDING ON
THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELLED OUT. THE QUANTIZER WILL NOT RECOGNIZE THIS AS A VALID STATE.
4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2819. THE QUANTIZER WILL BE
ABLE TO RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT.
02999-B
-
025
Figure 25. Example of Baseline Wander
ADN2819
Rev. B | Page 20 of 24
DC-COUPLED APPLICATION
The inputs to the ADN2819 can also be dc-coupled. This may
be necessary in burst mode applications where there are long
periods of CIDs and baseline wander cannot be tolerated. If the
inputs to the ADN2819 are dc-coupled, care must be taken not
to violate the input range and common-mode level
requirements of the ADN2819 (see Figure 26, Figure 27, and
Figure 28). If dc-coupling is required, and the output levels of
the TIA do not adhere to the levels shown in Figure 27 and
Figure 28, there needs to be level shifting and/or an attenuator
between the TIA outputs and the ADN2819 inputs.
LOL TOGGLING DURING LOSS OF INPUT DATA
If the input data stream is lost due to a break in the optical link
(or for any reason), the clock output from the ADN2819 will
stay within 1000 ppm of the VCO center frequency as long as
there is a valid reference clock. The LOL pin toggles at a rate of
several kHz because the LOL pin toggles between a Logic 1 and
a Logic 0, while the frequency loop and phase loop swap control
of the VCO. The chain of events is as follows:
The ADN2819 is locked to the input data stream; LOL = 0.
The input data stream is lost due to a break in the link. The
VCO frequency drifts until the frequency error is greater
than 1000 ppm. LOL is asserted to a Logic 1 as control of
the VCO is passed back to the frequency loop.
The frequency loop pulls the VCO to within 500 ppm of its
center frequency. Control of the VCO is passed back to the
phase loop and LOL is deasserted to a Logic 0.
The phase loop tries to acquire, but there is no input data
present so the VCO frequency drifts.
The VCO frequency drifts until the frequency error is
greater than 1000 ppm. LOL is asserted to a Logic 1 as
control of the VCO is passed back to the frequency loop.
This process is repeated until a valid input data stream is
re-established.
50
50
ADN2819
0.1
F
NIN
PIN
50
TIA
VREF
VCC
50
02999-B
-
026
Figure 26. ADN2819 with DC-Coupled Inputs
V
CM
= 0.4V MIN
(DC-COUPLED)
V
SE
= 5mV MIN
PIN
NIN
V p-p = PIN NIN = 2
V
SE
= 10mV AT SENSITIVITY
INPUT (V)
02999-
B-
027
Figure 27. Minimum Allowed DC-Coupled Input Levels
INPUT (V)
PIN
NIN
V
CM
= 0.6V
(DC-COUPLED)
V
SE
= 1.2V MAX
V p-p = PIN NIN = 2
V
SE
= 2.4V MAX
02999-
B-
028
Figure 28. Maximum Allowed DC-Coupled Input Levels
ADN2819
Rev. B | Page 21 of 24
OUTLINE DIMENSIONS
PIN 1
INDICATOR
TOP
VIEW
6.75
BSC SQ
7.00
BSC SQ
1
48
12
13
37
36
24
25
5.25
5.10 SQ
4.95
0.50
0.40
0.30
0.30
0.23
0.18
0.50 BSC
12 MAX
0.20 REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
5.50
REF
0.05 MAX
0.02 NOM
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
COPLANARITY
0.08
SEATING
PLANE
0.25 MIN
EXPOSED
PAD
(BOTTOM VIEW)
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 29. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm 7 mm Body
(CP-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADN2819ACP-CML
40C to +85C
48-Lead LFCSP
CP-48
ADN2819ACP-CML-RL
40C to +85C
48-Lead LFCSP
CP-48
ADN2819ACPZ-CML
1
40C to +85C
48-Lead LFCSP
CP-48
ADN2819ACPZ-CML-RL
1
40C to +85C
48-Lead LFCSP
CP-48
EVAL-ADN2819-CML
Evaluation
Board
1
Z = Pb Free.
ADN2819
Rev. B | Page 22 of 24
NOTES
ADN2819
Rev. B | Page 23 of 24
NOTES
ADN2819
Rev. B | Page 24 of 24
NOTES
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C0299905/04(B)
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