MAT02 DS

Low Noise, Matched

Dual Monolithic Transistor

MAT02

FEATURES
Low Offset Voltage: 50 V max
Low Noise Voltage at 100 Hz, 1 mA: 1.0 nV/

Hz max

High Gain (h

500 min at I

= 1 mA

300 min at I

= 1 A

Excellent Log Conformance: r

0.3

Low Offset Voltage Drift: 0.1 V/ C max
Improved Direct Replacement for LM194/394

NOTE
Substrate is connected to case on TO-78 package.
Substrate is normally connected to the most negative
circuit potential, but can be floated.

PIN CONNECTION

TO-78

(H Suffix)

PRODUCT DESCRIPTION

The design of the MAT02 series of NPN dual monolithic tran-
sistors is optimized for very low noise, low drift and low r

Precision Monolithics' exclusive Silicon Nitride "Triple-
Passivation" process stabilizes the critical device parameters
over wide ranges of temperature and elapsed time. Also, the high
current gain (h

) of the MAT02 is maintained over a wide

range of collector current. Exceptional characteristics of the
MAT02 include offset voltage of 50

µV max (A/E grades) and

150

µV max F grade. Device performance is specified over the

full military temperature range as well as at 25

°C.

Input protection diodes are provided across the emitter-base
junctions to prevent degradation of the device characteristics
due to reverse-biased emitter current. The substrate is clamped
to the most negative emitter by the parasitic isolation junction
created by the protection diodes. This results in complete isola-
tion between the transistors.

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 2002

REV. E

The MAT02 should be used in any application where low
noise is a priority. The MAT02 can be used as an input
stage to make an amplifier with noise voltage of less than
1.0 nV/

Hz at 100 Hz. Other applications, such as log/antilog

circuits, may use the excellent logging conformity of the
MAT02. Typical bulk resistance is only 0.3

to 0.4 . The

MAT02 electrical characteristics approach those of an ideal
transistor when operated over a collector current range of 1
µA to 10 mA. For applications requiring multiple devices
see MAT04 Quad Matched Transistor data sheet.

REV. E

ELECTRICAL CHARACTERISTICS

MAT02E MAT02F

Parameter

Symbol

Conditions

Min

Typ

Max

Min

Typ

Max

Unit

Current Gain

= 1 mA

500

605

400

605

= 100

µA

500

590

400

590

= 10

µA

400

550

300

550

= 1

µA

300

485

200

485

Current Gain Match

µA I

1 mA

0.5

Offset Voltage

= 0, 1

µA I

1 mA

150

µV

Offset Voltage

MAX

µV

Change vs. V

µA I

1 mA

µV

Offset Voltage Change

= 0 V

µV

vs. Collector Current

µA I

1 mA

µV

Offset Current

Change vs. V

MAX

pA/V

Bulk Resistance

µA I

10 mA

0.3

0.5

0.3

0.5

Collector-Base

Leakage Current

CBO

= V

MAX

200

400

Collector-Collector

Leakage Current

= V

MAX

5, 6

200

400

Collector-Emitter

= V

MAX

5, 6

Leakage Current

CES

= 0

200

400

Noise Voltage Density

= 1 mA, V

= 0

= 10 Hz

1.6

nV/

= 100 Hz

0.9

nV/

= 1 kHz

0.85

nV/

= 10 kHz

0.85

nV/

Collector Saturation

Voltage

CE(SAT)

= 1 mA, I

= 100

µA

0.05

0.1

0.05

0.2

Input Bias Current

= 10

µA

Input Offset Current

= 10

µA

0.6

1.3

Breakdown Voltage

CEO

Gain-Bandwidth Product

= 10 mA, V

= 10 V

200

MHz

Output Capacitance

= 15 V, I

= 0

Collector-Collector

Capacitance

= 0

NOTES

Current gain is guaranteed with Collector-Base Voltage (V

) swept from 0 to V

MAX

at the indicated collector currents.

Current gain match (

) is defined as:

FE =

Measured at I

= 10

µA and guaranteed by design over the specified range of I

This is the maximum change in V

as V

is swept from 0 V to 40 V.

Guaranteed by design.

and I

CES

are verified by measurement of I

CBO

Sample tested.

Specifications subject to change without notice.

100 (

) (h

min)

MAT02SPECIFICATIONS

(@ V

= 15 V, I

= 10 A, T

= 25 C, unless otherwise noted.)

ELECTRICAL CHARACTERISTICS

MAT02E MAT02F

Parameter

Symbol

Conditions

Min

Typ

Max

Min

Typ

Max

Unit

Offset Voltage

= 0

220

µV

µA I

1 mA

Average Offset

Voltage Drift

TCV

µA I

1 mA, 0 V

MAX

0.08 0.3

0.08 1

µV/°C

Trimmed to Zero

0.03 0.1

0.03 0.3

Input Offset Current

= 10

µA

Input Offset

Current Drift

TCI

= 10

µA

150

pA/

°C

Input Bias Current

= 10

µA

Current Gain

= 1 mA

325

300

= 100

µA

275

250

= 10

µA

225

200

= 1

µA

200

150

Collector-Base

CBO

= V

MAX

Leakage Current

Collector-Emitter

CES

= V

MAX

, V

= 0

Leakage Current

Collector-Collector

= V

MAX

Leakage Current

NOTES

Measured at I

= 10

µA and guaranteed by design over the specified range of I

Guaranteed by V

test (TCV

for V

) T = 298K for T

= 25

°C.

The initial zero offset voltage is established by adjusting the ratio of I

1 to I

2 at T

= 25

°C. This ratio must be held to 0.003% over the entire temperature range.

Measurements are taken at the temperature extremes and 25

°C.

Guaranteed by design.

Current gain is guaranteed with Collector-Base Voltage (V

) swept from 0 V to V

MAX

at the indicated collector current.

Specifications subject to change without notice.

= 15 V, 25 C

+85 C, unless otherwise noted.)

MAT02

REV. E

WARNING!

ESD SENSITIVE DEVICE

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the MAT02 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

ABSOLUTE MAXIMUM RATINGS

Collector-Base Voltage (BV

CBO

) . . . . . . . . . . . . . . . . . . . . 40 V

Collector-Emitter Voltage (BV

CEO

) . . . . . . . . . . . . . . . . . . 40 V

Collector-Collector Voltage (BV

) . . . . . . . . . . . . . . . . . . 40 V

Emitter-Emitter Voltage (BV

) . . . . . . . . . . . . . . . . . . . . 40 V

Collector Current (I

) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Emitter Current (I

) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Total Power Dissipation

Case Temperature

40°C

. . . . . . . . . . . . . . . . . . . . . 1.8 W

Ambient Temperature

70°C

. . . . . . . . . . . . . . . . 500 mW

Operating Temperature Range

MAT02E, F . . . . . . . . . . . . . . . . . . . . . . . . . 25

°C to +85°C

ORDERING GUIDE

max

Temperature

Package

Model

= 25 C)

Range

Option

MAT02EH

µV

°C to +85°C

TO-78

MAT02FH

150

µV

°C to +85°C

TO-78

Operating Junction Temperature . . . . . . . . . . 55

°C to +150°C

Storage Temperature . . . . . . . . . . . . . . . . . . . 65

°C to +150°C

Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . 300

°C

Junction Temperature . . . . . . . . . . . . . . . . . . 65

°C to +150°C

NOTES

Absolute maximum ratings apply to both DICE and packaged devices.

Rating applies to applications using heat sinking to control case temperature.

Derate linearly at 16.4 mW/

°C for case temperature above 40°C.

Rating applies to applications not using a heat sinking; devices in free air only.

Derate linearly at 6.3 mW/

°C for ambient temperature above 70°C.

MAT02

REV. E

Figure 1. Log Conformance Test Circuit

LOG CONFORMANCE TESTING

The log conformance of the MAT02 is tested using the circuit
shown above. The circuit employs a dual transdiode logarithmic
converter operating at a fixed ratio of collector currents that are
swept over a 10:1 range. The output of each transdiode converter
is the V

of the transistor plus an error term which is the prod-

uct of the collector current and r

, the bulk emitter resistance.

The difference of the V

is amplified at a gain of

×100 by the

AMP01 instrumentation amplifier. The differential emitter-base
voltage (

) consists of a temperature-dependent dc level plus

an ac error voltage, which is the deviation from true log confor-
mity as the collector currents vary.

The output of the transdiode logarithmic converter comes from
the idealized intrinsic transistor equation (for silicon):

(1)

where

k = Boltzmann's Constant (1.38062

× 10

J/K)

q = Unit Electron Charge (1.60219

× 10

°C)

T = Absolute Temperature, K (=

°C + 273.2)

= Extrapolated Current for V

= Collector Current

An error term must be added to this equation to allow for the
bulk resistance (r

) of the transistor. Error due to the op amp

input current is limited by use of the OP15 BiFET-input op
amp. The resulting AMP01 input is:

+ I

BE1

 I

BE2

(2)

A ramp function that sweeps from 1 V to 10 V is converted by
the op amps to a collector current ramp through each transistor.
Because I

is made equal to 10 I

, and assuming T

= 25

°C,

the previous equation becomes:

= 59 mV + 0.9 I

(

~ 0)

As viewed on an oscilloscope, the change in

for a 10:1

change in I

is then displayed as shown in Figure 2 below:

Figure 2.

With the oscilloscope ac coupled, the temperature dependent
term becomes a dc offset and the trace represents the deviation
from true log conformity. The bulk resistance can be calculated
from the voltage deviation

and the change in collector

current (9 mA):

9 mA

100

(3)

This procedure finds r

for Side A. Switching R

and R

will

provide the r

for Side B. Differential r

is found by making

= R

MAT02

REV. E

Figure 3. One-Quadrant Multiplier/Divider

APPLICATIONS: NONLINEAR FUNCTIONS

MULTIPLIER/DIVIDER CIRCUIT

The excellent log conformity of the MAT02 over a very wide
range of collector current makes it ideal for use in log-antilog
circuits. Such nonlinear functions as multiplying, dividing,
squaring and square-rooting are accurately and easily imple-
mented with a log antilog circuit using two MAT02 pairs (see
Figure 3). The transistor circuit accepts three input currents (I

and I

) and provides an output current I

according to

= I

. All four currents must be positive in the log antilog

circuit, but negative input voltages can be easily accommodated
by various offsetting techniques. Protective diodes across each
base-to-emitter junction would normally be needed, but these
diodes are built into the MAT02. External protection diodes
are, therefore, not needed.

For the circuit shown in Figure 3, the operational amplifiers
make I

= V

, I

= V

, I

= V

, and I

= V

. The

output voltage for this one-quadrant, log-antilog multiplier/
divider is ideally:

, V

> 0)

(4)

If all the resistors (R

, R

) are made equal, then

= V

Resistor values of 50 k

to 100 k are recommended assuming

an input range of 0.1 V to +10 V.

ERROR ANALYSIS

The base-to-emitter voltage of the MAT02 in its forward active
operation is:

+ r

, V

~ 0

(5)

The first term comes from the idealized intrinsic transistor
equation previously discussed (see equation (1)).

Extrinsic resistive terms and the early effect cause departure
from the ideal logarithmic relationship. For small V

, all of

these effects can be lumped together as a total effective bulk
resistance r

. The r

term causes departure from the desired

logarithmic relationship. The r

term for the MAT02 is less

than 0.5

and r

between the two sides is negligible.

Returning to the multiplier/divider circuit of Figure 1 and using
Equation (4):

BE1A

+ V

BE2A

 V

BE2B

 V

BE1B

+ (I

+ I

 I

) r

= 0

If the transistor pairs are held to the same temperature, then:

I I

S A S A

S B S B

1 2

+ (I

+ I

 I

) r

(6)

If all the terms on the right-hand side were zero, then In
(I

) would equal zero, which would lead directly to

the desired result:

, where I

, I

> 0

(7)

Note that this relationship is temperature independent. The
right-hand side of Equation (6) is near zero and the output
current I

will be approximately I

. To estimate error,

define ø as the right-hand side terms of Equation (6):

ø = In

S A S A

S B S B

+ I

 I

) r

(8)

For the MAT02, In (I

) and I

are very small. For small

ø,

~ 1 + ø and therefore:

= 1 + ø

(9)

(1 ø)

The In (I

) terms in ø cause a fixed gain error of less than

±0.6% from each pair when using the MAT02, and this gain
error is easily trimmed out by varying R

. The I

OUT

terms are

MAT02

REV. E

more troublesome because they vary with signal levels and are
multiplied by absolute temperature. At 25

°C, kT/q is

approximately 26 mV and the error due to an r

term will be

/26 mV. Using an r

of 0.4

for the MAT02 and assum-

ing a collector current range of up to 200

µA, then a peak error

of 0.3% could be expected for an r

error term when using

the MAT02. Total error is dependent on the specific application
configuration (multiply, divide, square, etc.) and the required
dynamic range. An obvious way to reduce I

error is to re-

duce the maximum collector current, but then op amp offsets
and leakage currents become a limiting factor at low input lev-
els. A design range of no greater than 10

µA to 1 mA is generally

recommended for most nonlinear function circuits.

A powerful technique for reducing error due to I

is shown in

Figure 4. A small voltage equal to I

is applied to the transis-

tor base. For this circuit:

and I

(10)

The error from r

is cancelled if R

is made equal to r

OUT

Since the MAT02 bulk resistance is approximately 0.39

, an

of 3.9

and R

of 10 R

will give good error cancellation.

In more complex circuits, such as the circuit in Figure 3, it may
be inconvenient to apply a compensation voltage to each indi-
vidual base. A better approach is to sum all compensation to the
bases of Q1. The "A" side needs a base voltage of (V

+ V

) r

, and the "B" side needs a base voltage of (V

)

. Linearity of better than

±0.1% is readily achievable with

this compensation technique.

Operational amplifier offsets are another source of error. In
Figure 4, the input offset voltage and input bias current will
cause an error in collector current of (V

) + I

. A low

offset op amp, such as the OP07 with less than 75

µV of V

and I

of less than

± 3 nA, is recommended. The OP193,

micropower op amp, should be considered if low power con-

sumption or single-supply operation is needed. The value of
frequency-compensating capacitor (C

) is dependent on the

op amp frequency response and peak collector current. Typi-
cal values for C

range from 30 pF to 300 pF.

Figure 4. Compensation of Bulk Resistance Error

FOUR-QUADRANT MULTIPLIER

A simplified schematic for a four-quadrant log-antilog multiplier
is shown in Figure 5. Similar to the previously discussed one-
quadrant multiplier, the circuit makes I

= I

. The two

input currents, I

and I

, are each offset in the positive direction.

This positive offset is then subtracted out at the output stage.
Assuming ideal op amps, the currents are:

(11)

From I

= I

, the output voltage will be:

(12)

Figure 5. Four-Quadrant Multiplier

MAT02

REV. E

Collector current range is the key design decision. The inher-
ently low r

of the MAT02 allows the use of a relatively high

collector current. For input scaling of

±10 V full-scale and using

a 10 V reference, we have a collector-current range for I

and I

of:

(13)

Practical values for R

and R

would range from 50 k

100 k

. Choosing an R

of 82 k

and R

of 62 k

provides a

collector current range of approximately 39

µA to 283 µA. An

of 108 k

will then make the output scale factor 1/10 and

= V

/10. The output, as well as both inputs, are scaled for

±10 V full scale.
Linear error for this circuit is substantially improved by the
small correction voltage applied to the base of Q1 as shown in
Figure 5. Assuming an equal bulk emitter resistance for each
MAT02 transistor, then the error is nulled if:

+ I

 I

) r

= 0

The currents are known from the previous discussion, and the
relationship needed is simply:

(14)

The output voltage is attenuated by a factor of r

and ap-

plied to the base of Q1 to cancel the summation of voltage drops
due to r

terms. This will make In (I

) more nearly

zero which will thereby make I

= I

a more accurate rela-

tionship. Linearity of better than 0.1% is readily achievable with
this circuit if the MAT02 pairs are carefully kept at the same
temperature.

Figure 6. Multifunction Converter

MULTIFUNCTION CONVERTER

The multifunction converter circuit provides an accurate means
of squaring, square rooting, and raising ratios to arbitrary pow-
ers. The excellent log conformity of the MAT02 allows a wide
range of exponents. The general transfer function is:

= V

(15)

, V

, and V

are input voltages and the exponent "m" has a

practical range of approximately 0.2 to 5. Inputs V

and V

are

often taken from a fixed reference voltage. With a REF01 pro-
viding a precision 10 V to both V

and V

, the transfer function

would simplify to:

= 10

(16)

As with the multiplier/divider circuits, assume that the transistor
pairs have excellent matching and are at the same temperature.
The In I

will then be zero. In the circuit of Figure 6, the

voltage drops across the base-emitter junctions of Q1 provide:

+ KR

(17)

is V

and I

is V

. Similarly, the relationship for Q2 is:

+ 1 K

(

)

(18)

is V

and I

is V

. These equations for Q1 and Q2 can

then be combined.

+ KR

+ 1 K

(

)

= In

(19)

MAT02

REV. E

Substituting in the voltage relationships and simplifying leads
to:

, where

(20)

m =

+ KR

+ 1 K

(

)

The factor "K" is a potentiometer position and varies from zero
to 1.0, so "m" ranges from R

/(R

+ R

) to (R

+ R

)/R

Practical values are 125

for R

and 500

for R

; these

values will provide an adjustment range of 0.2 to 5.0. A value
of 100 k

is recommended for the R

resistors assuming a full-

scale input range of 10 V. As with the one-quadrant
multiplier/divider circuit previously discussed, the V

, V

, and

inputs must all be positive.

The op amps should have the lowest possible input offsets. The
OP07 is recommended for most applications, although such
programmable micropower op amps as the OP193/OP293 offer
advantages in low-power or single-supply circuits. The micro-
power op amps also have very low input bias-current drift, an
important advantage in log/antilog circuits. External offset
nulling may be needed, particularly for applications requiring a
wide dynamic range. Frequency compensating capacitors, on
the order of 50 pF, may be required for A

and A

. Amplifier

is likely to need a larger capacitor, typically 0.0047

µF, to

assure stability.

Accuracy is limited at the higher input levels by bulk emitter
resistance, but this is much lower for the MAT02 than for other
transistor pairs. Accuracy at the lower signal levels primarily
depends on the op amp offsets. Accuracies of better than 1%
are readily achievable with this circuit configuration and can be
better than

±0.1% over a limited operating range.

FAST LOGARITHMIC AMPLIFIER

The circuit of Figure 7 is a modification of a standard logarith-
mic amplifier configuration. Running the MAT02 at 2.5 mA
per side (full-scale) allows a fast response with wide dynamic
range. The circuit has a 7 decade current range, a 5 decade
voltage range, and is capable of 2.5

µs settling time to 1% with

a 1 V to 10 V step.

The output follows the equation:

+ R

REF

(21)

The output is inverted with respect to the input, and is nomi-
nally 1 V/decade using the component values indicated.

Figure 7. Fast Logarithmic Amplifier

LOW-NOISE 1000 AMPLIFIER

The MAT02 noise voltage is exceptionally low, only 1 nV/

at 10 Hz when operated over a collector current range of 1 mA
to 4 mA. A single-ended

×1000 amplifier that takes advantage of

this low MAT02 noise level is shown in Figure 8. In addition to
low noise, the amplifier has very low drift and high CMRR. An
OP184 is used for the second stage to obtain good speed with
minimal power consumption. Small-signal bandwidth is 4.0
MHz, slew rate is 2.4 V/

µs, and total supply current is approxi-

mately 2.25 mA.

Figure 8. Low-Noise, Single-Ended

× 1000 Amplifier

MAT02

REV. E

Transistors Q2 and Q3 form a 2 mA current source (0.65 V/
330

~ 2 mA). Each collector of Q1 operates at 1 mA. The

OP184 inputs are 3 V below the positive supply voltage (R

~ 3 V). Input stage gain is g

, which is approximately 100

when operating at I

of 1 mA with R

of 3 k

. Since the

OP184 has a minimum open-loop gain of 500,000, total
open-loop gain for the composite amplifier is over 50 million.
Even at closed-loop gain of 1000, the gain error due to finite
open-loop gain will be negligible. The OP184 features excellent
symmetry of slew-rate and very linear gain. Signal distortion is
minimal.

Dynamic range of this amplifier is excellent; the OP184 has an
output voltage swing of

±14.8 V with a ±15 V supply.

Input characteristics are outstanding. The MAT02F has offset
voltage of less than 150

µV at 25°C and a maximum offset drift

of 1

µV/°C. Nulling the offset will further reduce offset drift.

This can be accomplished by slightly unbalancing the collector
load resistors. This adjustment will reduce the drift to less than
0.1

µV/°C.

Input bias current is relatively low due to the high current gain
of the MAT02. The minimum

of 400 at 1 mA for the

MAT02F implies an input bias current of approximately 2.5

µA.

This circuit should be used with signals having relatively low
source impedance. A high source impedance will degrade offset
and noise performance.

This circuit configuration provides exceptionally low input noise
voltage and low drift. Noise can be reduced even further by
raising the collector currents from 1 mA to 3 mA, but power
consumption is then increased.

MAT02

REV. E

C0028304/02(E)

PRINTED IN U.S.A.

OUTLINE DIMENSION

Dimensions shown in inches and (mm).

6-Lead Metal Can

(TO-78)

0.250 (6.35) MIN

0.750 (19.05)

0.500 (12.70)

0.185 (4.70)

0.165 (4.19)

REFERENCE PLANE

0.050 (1.27) MAX

0.019 (0.48)
0.016 (0.41)

0.021 (0.53)
0.016 (0.41)

0.045 (1.14)
0.010 (0.25)

0.040 (1.02) MAX

BASE AND SEATING PLANE

0.335 (8.51)

0.305 (7.75)

0.370 (9.40)

0.335 (8.51)

0.034 (0.86)
0.027 (0.69)

0.045 (1.14)
0.027 (0.69)

0.160 (4.06)
0.110 (2.79)

0.100 (2.54) BSC

0.200
(5.08)

BSC

0.100
(2.54)

BSC

° BSC

Revision History

Location

Page

4/02--Data Sheet changed from REV. D to REV. E.

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1/02--Data Sheet changed from REV. C to REV. D.

Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Deleted ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Deleted WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Deleted TYPICAL ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Deleted DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Edits to text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Updated Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MAT02E

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MAT02E