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Tel: 617/329-4700

Fax: 617/326-8703

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

Bipolar/JFET,

Audio Operational Amplifier

OP176*

FEATURES
Low Noise: 6 nV/

High Slew Rate: 25 V/

Wide Bandwidth: 10 MHz
Low Supply Current: 2.5 mA
Low Offset Voltage: 1 mV
Unity Gain Stable
SO-8 Package

APPLICATIONS
Line Driver
Active Filters
Fast Amplifiers
Integrators

PIN CONNECTIONS

8-Lead Narrow-Body SO

8-Lead Epoxy DIP

(S Suffix)

(P Suffix)

NULL

IN

+IN

V+

OUT

NULL

OP176

NULL

IN

+IN

OP-482

V+

OUT

NULL

OP176

GENERAL DESCRIPTION

The OP176 is a low noise, high output drive op amp that
features the Butler Amplifier front-end. This new front-end
design combines both bipolar and JFET transistors to attain
amplifiers with the accuracy and low noise performance of
bipolar transistors, and the speed and sound quality of JFETs.
Total Harmonic Distortion plus Noise equals previous audio
amplifiers, but at much lower supply currents.

Improved dc performance is also provided with bias and offset
currents greatly reduced over purely bipolar designs. Input
offset voltage is guaranteed at 1 mV and is typically less than

200

V. This allows the OP176 to be used in many dc coupled

or summing applications without the need for special selections
or the added noise of additional offset adjustment circuitry.

The output is capable of driving 600

loads to 10 V rms while

maintaining low distortion. THD + Noise at 3 V rms is a low
0.0006%.

The OP176 is specified over the extended industrial (40

C to

+85

C) temperature range. OP176s are available in both plastic

DIP and SO-8 packages. SO-8 packages are available in 2500
piece reels. Many audio amplifiers are not offered in SO-8
surface mount packages for a variety of reasons, however, the
OP176 was designed so that it would offer full performance in
surface mount packaging.

*Protected by U.S. Patent No. 5101126.

Simplified Schematic

RB4

RB3

QB5

RB5

QB6

RB7

RB6

QB7

Q10

CCB

QS1

RS1

RS2

QS2

QS3

QB9

Q11

CC2

QB8

R2L

R2P1

R2A

R2P2

R2S

R1P2

R1P1

R1L

R1A

R1S

QB3

QB1

JB1

QB4

CB1

QB2

RB1

RB2

CC1

ELECTRICAL CHARACTERISTICS

Parameter

Symbol

Conditions

Min

Typ

Max

Units

INPUT CHARACTERISTICS

Offset Voltage

+85

1.25

Input Bias Current

= 0 V

350

= 0 V, 40

+85

400

Input Offset Current

= 0 V

= 0 V, 40

+85

100

Input Voltage Range

10.5

+10.5

Common-Mode Rejection

CMRR

10.5 V,

+85

106

Large Signal Voltage Gain

= 2 k

250

V/mV

= 2 k

, 40

+85

175

V/mV

= 600

200

V/mV

Offset Voltage Drift

OUTPUT CHARACTERISTICS

Output Voltage Swing

= 2 k

, 40

+85

13.5

+13.5

= 600

, V

18 V

14.8

+14.8

Output Short Circuit Current

POWER SUPPLY

Power Supply Rejection Ratio

PSRR

4.5 V to

18 V

108

+85

Supply Current

4.5 V to

18 V, V

= 0 V,

, 40

+85

2.5

Supply Current

22 V, V

= 0 V, R

+85

2.75

Supply Voltage Range

4.5

DYNAMIC PERFORMANCE

Slew Rate

= 2 k

Gain Bandwidth Product

GBP

MHz

AUDIO PERFORMANCE

THD + Noise

= 3 V rms,

= 2 k

, f = 1 kHz

0.001

Voltage Noise Density

f = 1 kHz

nV/

Current Noise Density

f = 1 kHz

0.5

pA/

Specifications subject to change without notice.

REV. 0

OP176SPECIFICATIONS

(@ V

15.0 V, T

= +25

C unless otherwise noted)

OP176

REV. 0

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

22 V

Input Voltage

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

18 V

Differential Input Voltage

. . . . . . . . . . . . . . . . . . . . . . .

7.5 V

Output Short-Circuit Duration to GND . . . . . . . . . . Indefinite
Storage Temperature Range

P, S Package . . . . . . . . . . . . . . . . . . . . . . . . 65

C to +150

Operating Temperature Range

OP176G . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

C to +85

Junction Temperature Range

P, S Package . . . . . . . . . . . . . . . . . . . . . . . . 65

C to +150

Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300

Package Type

Units

8-Pin Plastic DIP (P)

103

C/W

8-Pin SOIC (S)

158

C/W

NOTES

Absolute maximum ratings apply to both DICE and packaged parts, unless

otherwise noted.

For input voltages greater than

7.5 V limit input current to less than 5 mA.

is specified for the worst case conditions, i.e.,

is specified for device in socket

for P-DIP packages;

is specified for device soldered in circuit board for SOIC

package.

(@ V

15.0 V, T

= +25

C unless otherwise noted)

WARNING!

ESD SENSITIVE DEVICE

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the OP176 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

Parameter

Symbol

Conditions

Limit

Units

Offset Voltage

mV max

Input Bias Current

= 0 V

350

nA max

Input Offset Current

= 0 V

nA max

Input Voltage Range

10.5

V min

Common-Mode Rejection

CMRR

10.5 V

dB min

Power Supply Rejection Ratio

PSRR

V =

4.5 V to

18 V

dB min

Large Signal Voltage Gain

= 2 k

250

V/mV min

Output Voltage Range

= 2 k

13.5

V min

18.0 V, R

= 600

14.8

V min

Supply Current

22.0 V, V

= 0 V, R

2.75

mA max

4.5 V to

18 V,

2.5

mA max

= 0 V, R

NOTES
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

Guaranteed by CMR test.

OP176 Die Size 0.069

0.067 Inch, 4,623 Sq. Mils.

Substrate (Die Backside) Is Connected to V.
Transistor Count, 26.

WAFER TEST LIMITS

NULL

OUT

NULL

IN

+IN

DICE CHARACTERISTICS

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

OP176GP

C to +85

8-Pin Plastic DIP

N-8

OP176GS

C to +85

8-Pin SOIC

SO-8

OP176GSR

C to +85

SO-8 Reel, 2500 Pieces

OP176GBC

+25

DICE

Figure 3. Input Bias Current vs. Temperature

Figure 6. Supply Current per Amplifier vs. Supply Voltage

OP176Typical Characteristics

REV. 0

Figure 1. Input Offset Voltage Drift Distribution @

15 V

Figure 4. Maximum Output Swing vs. Frequency

Figure 2. Output Swing vs. Temperature

Figure 5. Maximum Output Swing vs. Load Resistance

120

100

V/°C

15V

40°C

+85°C

BASED ON 300 OP AMPS

100

10k

LOAD RESISTANCE 

OUTPUT SWING Volts

POSITIVE SWING

NEGATIVE SWING

= ±15V

= +25°C

2.50

1.50

2.25

1.75

2.00

SUPPLY VOLTAGE V

SUPPLY CURRENT mA

= +85°C

= +25°C

= 40°C

100

25

50

TEMPERATURE °C

ABSOLUTE OUTPUT VOLTAGE V

18V, +V

, R

= 600

15V, +V

, R

= 600

15V, +V

, R

= 2k

18V,

, R

= 600

15V,

, R

= 2k

15V,

, R

= 600

10k

10M

100k

15V

= +25°C

FREQUENCY Hz

MAXIMUM OUTPUT SWING Volts

= 2k

300

100

150

25

100

50

250

200

TEMPERATURE °C

INPUT BIAS CURRENT nA

15V

= 0V

OP176

REV. 0

Figure 10. Power Supply Rejection vs. Frequency

Figure 7. Short Circuit Current vs. Temperature @

15 V

Figure 8. Open-Loop Gain & Phase vs. Frequency

Figure 11. Open-Loop Gain vs. Temperature

Figure 12. Closed-Loop Output Impedance vs. Frequency

Figure 9. Closed-Loop Gain vs. Frequency

120

100k

10k

100

FREQUENCY Hz

POWER SUPPLY REJECTION dB

15V

= +25°C

+PSRR

PSRR

FREQUENCY Hz

GAIN dB

120

100

60

10k

100M

10M

100k

20

40

GAIN

PHASE

PHASE MARGIN = 60°

135

180

225 PHASE Degrees

= +25°C

= ±15V

= >600

30

10k

100M

10M

100k

20

10

FREQUENCY Hz

GAIN dB

= +25°C

= ±15V

2000

100

500

250

25

50

1000

750

1250

1500

1750

TEMPERATURE °C

OPEN-LOOP GAIN V/mV

15V

10V

GAIN, R

= 2k

+GAIN, R

= 600

GAIN, R

= 600

+GAIN, R

= 2k

100k

10k

100

FREQUENCY Hz

IMPEDANCE 

= +100

= +10

= +1

= +25°C

= ±15V

100

25

50

TEMPERATURE °C

ABSOLUTE OUTPUT CURRENT mA

SINK

SOURCE

15V

OP176

REV. 0

Figure 16. Gain Bandwidth Product & Phase Margin vs.
Temperature

Figure 13. Common-Mode Rejection vs. Frequency

Figure 14. Small Signal Overshoot vs. Load Capacitance

Figure 17. Slew Rate vs. Load Capacitance

Figure 18. Slew Rate vs. Temperature

Figure 15. Slew Rate vs. Differential Input Voltage

75

125

50

100

25

15V

TEMPERATURE °C

PHASE MARGIN Degrees

GAIN BANDWIDTH PRODUCT MHz

PHASE

GAIN

2000

200

1800

1600

1400

1200

1000

800

600

400

LOAD CAPACITANCE pF

SLEW RATE V/µ

NEGATIVE SLEW RATE

POSITIVE SLEW RATE

= ±15V

= 2k

SWING = ±10V

SLEW WINDOW = ±5V

= +25°C

140

100

100k

10k

100

120

FRERQUENCY Hz

COMMON-MODE REJECTION dB

= +25°C

= ±15V

100

1000

100

900

800

700

600

500

400

300

200

15V

LOAD CAPACITANCE pF

OVERSHOOT %

NEGATIVE SWING

POSITIVE SWING

= 2k

= 100mVp-p

= 1

100

25

50

15V

= 2k

SLEW RATE V/µs

TEMPERATURE °C

SR

SR+

2.0

0.4

1.6

1.2

0.8

SLEW RATE V/µ

DIFFERENTIAL INPUT VOLTAGE V

SR+ AND SR

= ±15V

= 2k

= +25°C

OP176

REV. 0

APPLICATIONS
Short Circuit Protection

The OP176 has been designed with output short circuit
protection. The typical output drive current is

50 mA. This

high output current and wide output swing combine to yield an
excellent audio amplifier, even when driving large signals, at low
power and in a small package.

Total Harmonic Distortion

Total Harmonic Distortion + Noise (THD + N) of the OP176
is well below 0.001% with any load down to 600

. However,

this is dependent upon the peak output swing. In Figure 23 it is
seen that the THD + Noise with 3 V rms output is below
0.001%. In the following Figure 24, THD + Noise is below
0.001% for the 10 k

and 2 k

loads but increases to above

0.01% for the 600

load condition. This is a result of the

output swing capability of the OP176. Notice the results in
Figure 25, showing THD vs. V

(V rms).

FIGURE 23. THD + Noise vs. Frequency

0.1

0.010

0.001

0.0001

100

10k

20k

18V

= 10Vrms

600

10k

Figure 24. THD + Noise vs. R

LOAD

Figure 25. THD + Noise vs. Output Amplitude (V rms)

The output of the OP176 is designed to maintain low harmonic
distortion while driving 600

loads. However, driving 600

loads with very high output swings results in higher distortion if
clipping occurs.

To attain low harmonic distortion with large output swings,
supply voltages may be increased. Figure 26 shows the perfor-
mance of the OP176 driving 600

loads with supply voltages

varying from

18 volts to

20 volts. Notice that with

18 volt

supplies the distortion is fairly high, while with

20 volt supplies

it is a very low 0.0007%.

0.1

0.010

0.001

0.0001

100

10k

20k

= 600

18V

20V

19V

22V

Figure 26. THD + Noise vs. Supply Voltage

15V

= 3Vrms

0.1

0.010

0.001

.0001

100

10k

20k

600

0.1

0.010

0.001

.0001

100

10k

20k

18V

= 600

10Vrms

5Vrms

3Vrms

1Vrms

OP176

REV. 0

Noise

The voltage noise density of the OP176 is below 6 nV/

from

30 Hz. This enables low noise designs to have good perfor-
mance throughout the full audio range. Figure 27 shows a
typical OP176 with a 1/f corner at 6 Hz.

Figure 27. 1/f Noise Corner

Noise Testing

For audio applications the noise density is usually the most
important noise parameter. For characterization the OP176 is
tested using an Audio Precision, System One. The input signal
to the Audio Precision must be amplified enough to measure
accurately. For the OP176 the noise is gained by approximately
1020 using the circuit shown in Figure 28. Any readings on the
Audio Precision must then be divided by the gain. In imple-
menting this test fixture, good supply bypassing is essential.

Figure 28. Noise Test

Upgrading "5534`' Sockets

The OP176 is a superior amplifier for upgrading existing
designs using the industry standard 5534. In most application
circuits, the OP176 can directly replace the 5534 without any
modifications to the surrounding circuitry. Like the 5534, the
OP176 follows the industry standard, single op amp pinout. The
difference between these two devices is the location of the null
pins and the 5534's compensation capacitor.

The 5534 normally requires a 22 pF capacitor between Pins 5
and 8 for stable operation. Since the OP176 is internally
compensated for unity gain operation, it does not require
external compensation. Nevertheless, if the 5534 socket already
includes a capacitor, the OP176 can be inserted without
removing it. Since the OP176's Pin 8 is a "NO CONNECT''
pin, there is no internal connection to that pin. Thus, the 22 pF
capacitor would be electrically connected through Pin 5 to the
internal nulling circuitry. With the other end left open, the
capacitor should have no effect on the circuit. However, to
avoid altogether any possibility for noise injection, it is recom-
mended that the 22 pF capacitor be cut out of the circuit
entirely.

If the original 5534 socket includes offset nulling circuitry, one
would find a 10 k

to 100 k

potentiometer connected between

Pins 1 and 8 with said potentiometer's wiper arm connected to
V+. In order to upgrade the socket to the OP176, this circuit
should be removed before inserting the OP176 for its offset
nulling scheme uses Pins 1 and 5. Whereas the wiper arm of the
5534 trimming potentiometer is connected to the positive
supply, the OP176's wiper arm is connected to the negative
supply. Directly substituting the OP176 into the original socket
would inject a large current imbalance into its input stage. In
this case, the potentiometer should be removed altogether, or, if
nulling is still required, the trimming potentiometer should be
rewired to match the nulling circuit as illustrated in Figure 29.

Figure 29. Offset Voltage Nulling Scheme

Input Overcurrent Protection

The maximum input differential voltage that can be applied to
the OP176 is determined by a pair of internal Zener diodes
connected across its inputs. They limit the maximum differen-
tial input voltage to

7.5 V. This is to prevent emitter-base

junction breakdown from occurring in the input stage of the
OP176 when very large differential voltages are applied.
However, in order to preserve the OP176's low input noise
voltage, internal resistances in series with the inputs were not
used to limit the current in the clamp diodes. In small signal
applications, this is not an issue; however, in applications where
large differential voltages can be inadvertently applied to the
device, large transient currents can flow through these diodes.
Although these diodes have been designed to carry a current of

5 mA, external resistors as shown in Figure 30 should be used

in the event that the OP176's differential voltage were to exceed

7.5 V.

Figure 30. Input Overcurrent Protection

OP176

OUT

P1 = 10k

TRIM RANGE = ±2mV

OP176

1.4k

50Hz /
300 mHz

\ 0 Hz
MKR:

5.4 Hz

10.0 µV /DIV

CH A: 80.0 µV FS

BW:

MKR: 15.9 µV/

OP176

OP37

OUTPUT

4.42k

909

100

490

100

OP176

REV. 0

Figure 33. Unity Gain Follower

Figure 34. Unity Gain Inverter

In inverting and noninverting applications, the feedback
resistance forms a pole with the source resistance and capaci-
tance (R

and C

) and the OP176's input capacitance (C

), as

shown in Figure 35. With R

and R

in the k

range, this pole

can create excess phase shift and even oscillation. A small
capacitor, C

, in parallel with R

eliminates this problem. By

setting R

+ C

) = R

, the effect of the feedback pole is

completely removed.

Figure 35. Compensating the Feedback Pole

Output Voltage Phase Reversal

Since the OP176's input stage combines bipolar transistors for
low noise and p-channel JFETs for high speed performance, the
output voltage of the OP176 may exhibit phase reversal if either
of its inputs exceeds the specified negative common-mode input
voltage. This might occur in some applications where a trans-
ducer, or a system, fault might apply very large voltages upon
the inputs of the OP176. Even though the input voltage range
of the OP176 is

10.5 V, an input voltage of approximately

13.5 V will cause output voltage phase reversal. In inverting
amplifier configurations, the OP176's internal 7.5 V clamping
diodes will prevent phase reversal; however, they will not
prevent this effect from occurring in noninverting applications.
For these applications, the fix is a 3.92 k

resistor in series

with the noninverting input of the device and is illustrated in
Figure 31.

Figure 31. Output Voltage Phase Reversal Fix

Overdrive Recovery

The overdrive recovery time of an operational amplifier is the
time required for the output voltage to recover to a rated output
level from a saturated condition. This recovery time is impor-
tant in applications where the amplifier must recover quickly
after a large abnormal transient event. The circuit shown in
Figure 32 was used to evaluate the OP176's overload recovery
time. The OP176 takes approximately 1

s to recover to V

OUT

+10 V and approximately 900 ns to recover to V

OUT

= 10 V.

Figure 32. Overload Recovery Time Test Circuit

High Speed Operation

As with most high speed amplifiers, care should be taken with
supply decoupling, lead dress, and component placement.
Recommended circuit configurations for inverting and
noninverting applications are shown in Figure 33 and Figure 34.

909

OUT

2.43k

10k

4Vp-p

@ 100Hz

OP176

+15V

10µF

0.1µF

OUT

15V

10µF

0.1µF

OP176

+15V

10µF

0.1µF

OUT

15V

10µF

0.1µF

OP176

10pF

4.99k

2.49k

4.99k

OUT

3.92k

OUT

IS OPTIONAL

OP176

OP176

REV. 0

Attention to Source Impedances Minimizes Distortion

Since the OP176 is a very low distortion amplifier, careful
attention should be given to source impedances seen by both
inputs. As with many FET-type amplifiers, the p-channel
JFETs in the OP176's input stage exhibit a gate-to-source
capacitance that varies with the applied input voltage. In an
inverting configuration, the inverting input is held at a virtual
ground and, as such, does not vary with input voltage. Thus,
since the gate-to-source voltage is constant, there is no distor-
tion due to input capacitance modulation. In noninverting
applications, however, the gate-to-source voltage is not
constant. The resulting capacitance modulation can cause
distortion above 1 kHz if the input impedance is > 2 k

and

unbalanced.

Figure 36 shows some guidelines for maximizing the distortion
performance of the OP176 in noninverting applications. The
best way to prevent unwanted distortion is to ensure that the
parallel combination of the feedback and gain setting resistors
(R

and R

) is less than 2 k

. Keeping the values of these

resistors small has the added benefits of reducing the thermal
noise of the circuit and dc offset errors. If the parallel combina-
tion of R

and R

is larger than 2 k

, then an additional

resistor, R

, should be used in series with the noninverting

input. The value of R

is determined by the parallel combina-

tion of R

and R

to maintain the low distortion performance of

the OP176. For a more generalized treatment on circuit
impedances and their effects on circuit distortion, please review
the section on Active Filters at the end of the Applications
section.

Driving Capacitive Loads

As with any high speed amplifier, care must be taken when
driving capacitive loads. The graph in Figure 14 shows the
OP176's overshoot versus capacitive load. The test circuit is a
standard noninverting voltage follower; it is this configuration
that places the most demand on an amplifier's stability. For
capacitive loads greater than 400 pF, overshoot exceeds 40%
and is roughly equivalent to a 45

phase margin. If the applica-

tion requires the OP176 to drive loads larger than 400 pF, then
external compensation should be used.

Figure 37 shows a simple circuit which uses an in-the-loop
compensation technique that allows the OP176 to drive any
capacitive load. The equations in the figure allow optimization
of the output resistor, R

, and the feedback capacitor, C

, for

optimal circuit stability. One important note is that the circuit
bandwidth is reduced by the feedback capacitor, C

, and is

given by:

BW =

Figure 37. In-the-Loop Compensation Technique for
Driving Capacitive Loads

APPLICATIONS USING THE OP176
A High Speed, Low Noise Differential Line Driver

The circuit of Figure 38 is a unique line driver widely used in
many applications. With

18 V supplies, this line driver can

deliver a differential signal of 30 V p-p into a 2.5 k

load. The

high slew rate and wide bandwidth of the OP176 combine to
yield a full power bandwidth of 130 kHz while the low noise
front end produces a referred-to-input noise voltage spectral
density of 15 nV/

. The circuit is capable of driving lower

impedance loads as well. For example, with a reduced output
level of 5 V rms (14 V p-p), the circuit exhibits a full-power
bandwidth of 190 kHz while driving a differential load of 249

The design is a transformerless, balanced transmission system
where output common-mode rejection of noise is of paramount
importance. Like the transformer-based design, either output
can be shorted to ground for unbalanced line driver applications
without changing the circuit gain of 1. Other circuit gains can
be set according to the equation in the diagram. This allows the
design to be easily set for noninverting, inverting, or differential
operation.

Figure 38. A High Speed, Low Noise Differential Line
Driver

R11
1k

10k

R12
1k

R10
50

 V

= V

A1, A2, A3 = OP176

GAIN =

SET R2, R4, R5 = R1 AND R6, R7, R8 = R3

R3
R1

OP176

OUT

= R

//R

IF R

//R

FOR MINIMUM DISTORTION

Figure 36. Balanced Input Impedance to Mininize
Distortion in Noninverting Amplifier Circuits

X =

OP176

OUT

WHERE R

= OPEN-LOOP OUTPUT RESISTANCE

(

)

(

)

[ ]

OP176

REV. 0

A Low Noise Microphone Preamplifier with a Phantom
Power Option

Figure 39 is an example of a circuit that combines the strengths
of the SSM2017 and the OP176 into a variable gain micro-
phone preamplifier with an optional phantom power feature.
The SSM2017's strengths lie in its low noise and distortion, and
gain flexibility/simplicity. However, rated only for 2 k

higher loads, this makes driving 600

loads somewhat limited

with the SSM2017 alone. A pair of OP176s are used in the
circuit as a high current output buffer (U2) and a DC servo
stage (U3). The OP176's high output current drive capability
provides a high level drive into 600

loads when operating

from

18 V supplies. For a complete treatment of the circuit

design details, the interested reader should consult application
note AN-242, available from Analog Devices.

This amplifier's performance is quite good over programmed
gain ranges of 2 to 2000. For a typical audio load of 600

THD + N at various gains and an output level of 10 V rms is
illustrated in Figure 40. For all but the very highest gain, the
THD + N is consistent and well below 0.01%, while the gain of
2000 becomes more limited by noise. The noise performance of
the circuit is exceptional with a referred-to-input noise voltage
spectral density of 1 nV/

at a circuit gain of 1000.

1.0

0.1

0.010

0.001

100

10k

20k

G = 2000

G = 200

G = 20

G = 4

18V

80kHz LPF

Figure 40. Low Noise Microphone Preamplifier THD + N
Performance at Various Gains (V

OUT

= 10 V rms and

= 600

)

Figure 39. A Low Noise Microphone Preamplifier

R10

100

+48V

6.81k

R8
6.81k

C8
47µF/
63V

PHANTOM POWER SUPPLY CONNECTIONS,
INTERLOCKED WITH +/V

(SEE NOTE 5).

TO MICROPHONE

IN

+IN

49.9

47µF/

63V

49.9

47µF/

63V

COMMON

2200µF/ 10V

10k

4.7nF/

FILM

8 1

SSM2017P

100pF

10k

33pF

OUTPUT

49.9

221k

20k

1µF FILM

R4
221k

1N458

OP176

1µF FILM

OUT COMMON

NOTES:
1) Z1Z4 1N752 (SEE TEXT).
2) C

INX

, C

LOW LEAKAGE ELECTROLYTIC TYPES (SEE TEXT).

3) GAIN = G = 2 x ((10k/R

) +1) (SEE TEXT).

4) ALL RESISTORS 1% METAL FILM.
5) DOTTED PHANTOM POWER RELATED COMPONENTS OPTIONAL (SEE TEXT).

+18V

18V

C6
0.1µF

C7
0.1µF

C3
100µF/25V

C4
100µF/25V

1N458

OP176

REV. 0

A Low Noise, +5 V/+10 V Reference

In many high resolution applications, voltage reference noise
can be a major contributor to overall system error. Monolithic
voltage references often exhibit too much wide band noise to be
used alone in these systems. Only through careful filtering and
buffering of these monolithic references can one realize wide-
band microvolt noise levels. The circuit illustrated in Figure 41
is an example of a low noise precision reference optimized for
both ac and dc performance around the OP176. With a +10 V
reference (the AD587), the circuit exhibits a 1 kHz spot output
noise spectral density < 10 nV/

. The reference output

voltage is selectable between 5 V and 10 V, depending only on
the selection of the monolithic reference. The output table
illustrated in the figure provides a selection of monolithic
references compatible with this circuit.

Figure 41. A Low Noise, +5 V/+10 V Reference

In operation, the basic reference voltage is set by U1, either a
5 V or 10 V 3-terminal reference chosen from the table. In this
case, the reference used is a 10 V buried Zener reference, but
all U1 IC types shown can plug into the pinout and can be
optionally trimmed. The stable 10 V from the reference is then
applied to the R1-C1-C2

noise filter, which uses electrolytic

capacitors for a low corner frequency. When electrolytic
capacitors are used for filtering, one must be cognizant of their
dc leakage current errors. Here, however, a dc bootstrap of C1
is used, so this capacitor sees only the small R2 dc drop as bias,
effectively lowering its leakage current to negligible levels. The
resulting low noise, dc-accurate output of the filter is then
buffered by a low noise, unity gain op amp using an OP176.
With the OP176's low V

and control of the source resistances,

the dc performance of this circuit is quite good and will not
compromise voltage reference accuracy and/or drift. Also, the
OP176 has a typical current limit of 50 mA, so it can provide
higher output currents when compared to a typical IC reference
alone.

A Differential ADC Driver

High performance audio sigma-delta ADCs, such as the stereo
16-bit AD1878 and the 18-bit AD1879, present challenging
design problems with regards to input interfacing. Because of
an internal switched capacitor input circuit, the ADC input
structure presents a difficult dynamic load to the drive amplifier
with fast transient input currents due to their 3 MHz ADC
sampling rate. Also, these ADCs inputs are differential with a
rated full-scale range of

6.3 V, or about 4.4 V rms. Hence, the

ADC interface circuit of Figure 42 is designed to accept a
balanced input signal to drive the low dynamic impedances seen
at the inputs of these ADCs. The circuit uses two OP176

Figure 42. A Balanced Driver Circuit for Sigma-Delta ADCs

amplifiers as inverting low-pass filters for their speed and high
output current drive. The outputs of the OP176s then drive the
differential ADC inputs through an RC network. This RC
network buffers the amplifiers against step changes at the ADC
sampling inputs using one differential (C3) and two common-
mode connected capacitors (C4 and C5). The 51

series

resistors isolate the OP176s from the heavily capacitive loads,
while the capacitors absorb the transient currents. Operating on

12 V supplies, this circuit exhibits a very low THD + N of

0.001% at 5 V rms outputs. For single-ended drive sources, a
third op amp unity gain inverter can be added between R2's (+)
input terminal and R4. For best results, short-lead, noninduc-
tive capacitors are suggested for C3, C4, and C5 (which are
placed close to the ADC), and 1% metal-film types for R1
through R6. For surface mount PCBs, these components can
be NPO ceramic chip capacitors and thin-film chip resistors.

100pF

5.76k

5.62k

C2 100pF

5.49k

5.62k

C4
0.01µF

C3
0.0047µF

C5
0.01µF

BALANCED

INPUTS

= AG, PIN 10 OR 18

TO
AD1878/
AD1879
SIGMA-
DELTA
ADC
L & R
INPUTS

U1, U2 = OP176

12V
ANALOG

(+)

()

NOTES
C1C5 = NPO CERAMIC, NON-INDUCTIVE,
C3-C5 CLOSE TO ADC
R1R6 = 1% METAL FILM

0.1µF

100µ/25V

+12V
ANALOG

COM

U1, U2

100µ/25V

(+)

USE
FOR
SINGLE-ENDED
INPUTS

OUTPUT TABLE

OUT

10V
10V
10V
10V
5V
5V
5V
5V

AD587
REF01
REF10
AD581
REF195
AD586
REF02
REF05

TOLERANCE
(+/mV)

5 TO 10
30 TO 100
30 TO 50
5 TO 30
2 TO 10
2.5 TO 20
15 TO 50
15 TO 25

OP176

+15V

100

10k

C4
0.1µF

C2
100µF/25V

TRIM

10k

C1
100µF/25V

100µF/25V

1.1k

100

R6
3.3

10µF/25V

OUT

REF
COMMON

(OPTIONAL)

OP176

REV. 0

An RIAA Phono Preamp

Figure 43 illustrates a simple phono preamplifier using RIAA
equalization. The OP176 is used here to provide gain and is
chosen for its low input voltage noise and high speed perfor-
mance. The feedback equalization network (R1, R2, C1, and
C2) forms a three time constant network, providing reasonably
accurate equalization with standard component values. The
input components terminate a moving magnet phono cartridge
as recommended by the manufacturer, the element values
shown being typical. When this ac coupled circuit is built with a
low noise bipolar input device such as the OP176, amplifier bias
current makes direct cartridge coupling difficult. This circuit
uses input and output capacitor coupling to minimize biasing
interactions.

Input ac coupling to the amplifier is provided via C5, and the
low frequency termination resistance, R

, is the parallel equiva-

lent of R6 and R7. R3 of the feedback network is ac grounded
via C4, a large value electrolytic. Additionally, this resistor is
set to a low value to minimize circuit noise from nonamplifier
sources. These design measures reduce the dc offset at the
output of the OP176 to a few millivolts. The output coupling
network of C3 and R4 is shown as suitable for wide band
response, but it can be set to a 7950

s time constant for use as

a 20 Hz rumble filter.

The 1 kHz gain ("G") of this circuit, controlled by R3, is
calculated as:

G (@ 1 kHz) = 0.101

1 + R1

For an R3 of 200

the circuit gain is just under 50

× (

34 dB),

and higher gains are possible by decreasing R3. For any value
of R3, the R5-C6 time constant should be equal to R3 and the
series equivalent of C1 and C2.

Using readily available standard values for network elements
(R1, R2, C1, and C2) makes the design easily reproducible and
inexpensive. These components are ideally high quality
precision types, for low equalization errors and minimum

parasitics. One percent metal-film resistors and two percent
film capacitors of polystyrene or polypropylene are recom-
mended. Using the suggested values, the frequency response
relative to the ideal RIAA characteristic is within

0.2 dB over

20 Hz20 kHz. Even tighter response can be achieved by using
the alternate values, shown in brackets "[ ]," with the trade-off
of a non off-the-shelf part.

As previously mentioned, the OP176 was chosen for three
reasons: (1) For optimal circuit noise performance, the
amplifier used should exhibit voltage and current noise densities
of 5 nV/

and 1 pA/

, respectively. (2) For high gain

accuracy, especially at high stage gains, the amplifier should
exhibit a gain bandwidth product in excess of 5 MHz. (3)
Equally important because of the 100% feedback through the
network at high frequencies, the amplifier must be unity gain
stable. With the OP176, the circuit exhibits low distortion over
the entire range, generally well below 0.01% at outputs levels of
5 V

rms using

18 V supplies. To achieve maximum perfor-

mance from this high gain, low level circuit, power supplies
should be well regulated and noise free, and care should be
taken with shielding and conductor layout.

Active Filter Circuits Using the OP176

A general active filter topology that lends itself to both high-pass
(HP) and low-pass (LP) filters is the well known Sallen-Key
(SK) VCVS (Voltage-Controlled, Voltage Source) architecture.
This filter type uses the op amp as a fixed gain voltage follower
at either unity or a higher gain. Discussed here are simplified 2-
pole, unity gain forms of these filters, which are attractive for
several reasons: One, at audio frequencies, using an amplifier
with a 10 MHz bandwidth such as the OP176, these filters
exhibit reasonably low sensitivities for unity gain and high
damping (low Q). Second, as voltage followers, they are also
inherently gain accurate within their pass band; hence, no gain
resistor scaling errors are generated. Third, they can also be
made "dc accurate," with output dc errors of only a few
millivolts. The specific filter response in terms of HP, LP and
damping is determined by the RC network around the op amp,
as shown in Figure 44a.

Figure 43. An RIAA Phono Preamplifier Circuit

100k

Ct
150pF

100

F/25V

MOVING
MAGNET
PICKUP

OP176

Rt = R6

| |

~ 50k

C1
0.03µF
2%

C2
0.01µF
2%

200

(34dB)

100

(40dB)

C4
1000µF/16V

100

F/25V

499

100k

C6
3nF

OUT

0.1µF

100µF

+18V

18V

100k

[97.6k

]

8.25k

[7.87k

]

OP176

REV. 0

High Pass Sections

Figure 44a illustrates the high-pass form of a 2-pole SK filter
using an OP176. For simplicity and practicality, capacitors C1
and C2

are set equal ("C"), and resistors R2 and R1

are

adjusted to a ratio, N, which provides the filter damping
coefficient,

, as per the design expressions. This high pass

design is begun with selection of standard capacitor values for
C1 and C2 and a calculation of N. The values for R1 and R2
are then determined from the following expressions:

FREQ

and

Figures 44a. Two-Pole Unity Gain HP/LP Active Filters

In this examples, circuit

(or 1/Q) is set equal to

, providing

a Butterworth (maximally flat) characteristic. The filter corner
frequency is normalized to 1 kHz, with resistor values shown in
both rounded and (exact) form. Various other 2-pole response
shapes are possible with appropriate selection of

, and fre-

quency can be easily scaled, using inversely proportional R or
C values for a given

. The 22 V/

s slew rate of the OP176 will

support 20 V p-p outputs above 100 kHz with low distortion.
The frequency response resulting with this filter is shown as the
dotted HP portion of Figure 45.

11k

(11.254k)

0.01µF

OUT

OP176

0.01µF

22k

(22.508k)

GIVEN:

FREQ

SET C1 = C2 = C

= =

N = =

R2
R1

R1 =

R2 = N x R1

COMP

(HIGH PASS)

IN ()

OUTPUT

1 kHz BW SHOWN

FREQ x C x N

Low Pass Sections

In the LP SK arrangement of Figure 44b, the R and C elements
are interchanged where the resistors are made equal. Here, the
ratio of C2/C1 ("M") is used to set the filter

, as noted.

Otherwise, this filter is similar to the HP section, and the
resulting 1 kHz LP response is shown in Figure 45. The design
begins with a choice of a standard capacitor value for C1 and a
calculation of M. This then forces a value of "M

C1" for C2.

Then, the value for R1 and R2 ("R") is calculated according to
the following equation:

FREQ

Figures 44b. Two-Pole Unity Gain HP/LP Active Filters

Figure 45. Relative Frequency Response of 2-Pole, 1 kHz
Butterworth LP (Left) and HP (Right) Active Filters

11k

(11.254k)

0.02µF

OUT

OP176

0.01µF

11k

(11.254k)

GIVEN:

FREQ

= =

M = =

C2
C1

C2 = M x C1

COMP

IN ()

OUTPUT

1 kHz BW SHOWN

CHOOSE C1

R =

FREQ x C1 x M

COMP

(LOW PASS)

100 50k

10k

10.000

30.00

70.00

50.00

10.00

20.00

40.00

60.00

0.0

FREQUENCY Hz

dBr

OP176

REV. 0

Passive Component Selection for Active Filters

The passive components suitable for active filters deserve more
than casual attention. Resistors should be 1%, low TC, metal-
film types of the RN55 or RN60 style. Capacitors should be 1%
or 2% film types preferably, such as polypropylene or polysty-
rene, or NPO (COG) ceramic for smaller values.

Active Filter Circuit Subtleties

In designing active filter circuits with the OP176, moderately
low values (10 k

or less) for R1 and R2 can be used to

minimize the effects of Johnson noise when critical. The
practical tradeoff is, of course, capacitor size and expense. DC
errors will result for larger values of resistance, unless compen-
sation for amplifier input bias current is used. To add bias
compensation in the HP filter section of Figure 42a, a feedback
compensation resistor equal to R2 can be used. This will
minimize bias current induced offset to the product of the
OP176's I

and R2. For an R2 of 25 k

, this produces a typical

compensated offset voltage of 50

V. Similar compensation is

applied to Figure 42b, using a resistance equal to R1+ R2.
Using dc compensation, filter output dc errors using the OP176
will be dominated by its V

, which is typically 1 mV or less. A

caveat here is that the additional resistors can increase noise
substantially. For example, a 10 k

resistor generates ~ 12 nV/

of noise and is about twice that of the OP176. These

resistors can be ac bypassed to eliminate their noise using a
simple shunt capacitor chosen such that its reactance (X

) is

much less than R at the lowest frequency of interest.

A more subtle form of ac degradation is also possible in these
filters, namely nonlinear input capacitance modulation. This
issue was previously covered for general cases in the section on
minimizing distortion. In active filter circuits, a fully compen-
sating network (for both dc and ac performance) can be used to
minimize this distortion. To be most effective, this network
(Z

COMP

) should include R1

through C2 as noted for either filter

type, of the same style and value as their counterparts in the
forward path. The effects of a Z

COMP

network on the THD + N

performance of two 1 kHz HP filters is illustrated in Figure 46.
One filter (A) is the example shown in Figure 44a (Curves A1
and A2), while the second (B) uses RC values scaled 10 times
upward in impedance (Curves B1 and B2). Both filters operate
with a 2 V rms input,

18 V supplies, 100 k

loading, and

analyzer bandwidth of 80 kHz.

Figure 46. THD + N (%) vs. Frequency for Various 1 kHz HP
Active Filters Illustrating the Effects of the Z

COMP

Network

Curves A1 and B1 show performance with Z

COMP

shorted,

while curves A2 and B2 illustrate operation with Z

COMP

active.

For the "A" example values, distortion in the pass band of
1 kHz20 kHz is below 0.001% compensated, and slightly
higher uncompensated. With the higher impedance "B" net-
work, there is a much greater difference between compensated
and uncompensated responses, underscoring the sensitivity to
higher impedances. Although the positive effect of Z

COMP

is seen

for both "A" and "B" cases, there is a buffering effect which
takes place with lower impedances. As case "A" shows, when
using larger capacitance values in the source, the amplifier's
nonlinear C-V input characteristics have less effect on the
signal.

Thus, to minimize the necessity for the complete Z

COMP

com-

pensation, effective filter designs should use the lowest capaci-
tive impedances practical, with an 0.01

F lower value limit as a

goal for lowest distortion (while lower values can certainly be
used, they may suffer higher distortion without the use of full
compensation). Since most designs are likely to use low relative
impedances for reasons of low noise and offset, the effects of
CM distortion may or may not actually be apparent to a given
application.

100 20k

0.010

0.0001

0.001

0.1

10 k

FREQUENCY Hz

THD +N %

OP176

REV. 0

OP176 SPICE Model

*
* Node Assignments
*

Noninverting Input

Inverting Input

Positive Supply

Negative Supply

Output

.SUBCKT OP176

*
* INPUT STAGE & POLE AT 100 MHz
*
R3

2.487

CIN 1

3.7E-12

CM1 1

7.5E-12

CM2 2

7.5E-12

320E-12

100E-3

IOS

1E-9

EOS 9

POLY(1)

(26,28)

0.2E-3

1.970

(10,0)

GN1 0

(13,0)

1E-3

GN2 0

(16,0)

1E-3

*
EREF 98

(28,0)

(99,0)

(50,0)

*
* VOLTAGE NOISE SOURCE
*
DN1 35

DEN

DN2 10

DEN

VN1 35

DC 2

VN2 0

DC 2

*
* CURRENT NOISE SOURCE
*
DN3 12

DIN

DN4 13

DIN

VN3 12

DC 2

VN4 0

DC 2

*
* CURRENT NOISE SOURCE
*
DN5 15

DIN

DN6 16

DIN

VN5 15

DC 2

VN6 0

DC 2

*
* GAIN STAGE & DOMINANT POLE AT 32 Hz
*
R7

1.243E6

4E-9

(5,6) 4.021E-1

1.35

20 18 DX

* POLE/ZERO PAIR AT 1.5 MHz/2.7 MHz
*
R8

1E3

1.25E3

47.2E-12

(18,28)

1E-3

*
* POLE AT 100 MHz
*
R10

1.59E-9

(21,28)

*
* POLE AT 100 MHz
*
R11

1.59E-9

(23,28)

*
* COMMON-MODE GAIN NETWORK WITH ZERO AT
1 kHz
*
R12

1E6

60E-12

R13

POLY(2)

(1,98) (2,98) 0 2.50 2.50

*
* POLE AT 100 MHz
*
R14

1.59E-9

(24,28)

*
* OUTPUT STAGE
*
R15

58.333E3

R16

58.333E3

1E-6

ISY

1.743E-3

R17

100

R18

100

1E-9

(27,29)

10E-3

(29,27)

10E-3

(99,27)

10E-3

(27,50)

10E-3

1.74

D10 50

*
* MODELS USED
*
.MODEL QX PNP(BF=5E5)
.MODEL DX D(IS=1E-12)
.MODEL DY D(IS=1E-15 BV=50)
.MODEL DZ D(IS=1E-15 BV=7.0)
.MODEL DEN D(IS=1E-12 RS=4.35K KF=1.95E-15 AF=1)
.MODEL DIN D(IS=1E-12 RS=268 KF=1.08E-15 AF=1)
.ENDS OP176

OP176

REV. 0

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead Plastic DIP (N-8)

PIN 1

0.280 (7.11)

0.240 (6.10)

SEATING
PLANE

0.060 (1.52)

0.015 (0.38)

0.130
(3.30)
MIN

0.210

(5.33)

MAX

0.160 (4.06)

0.115 (2.93)

0.430 (10.92)

0.348 (8.84)

0.022 (0.558)

0.014 (0.356)

0.070 (1.77)

0.045 (1.15)

0.100
(2.54)

BSC

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)

0.115 (2.93)

8-Lead Narrow-Body SO (SO-8)

0.0098 (0.25)

0.0075 (0.19)

0.0500 (1.27)

0.0160 (0.41)

0.0196 (0.50)

0.0099 (0.25)

x 45

PIN 1

0.1574 (4.00)

0.1497 (3.80)

0.2440 (6.20)

0.2284 (5.80)

0.0192 (0.49)

0.0138 (0.35)

0.0500

(1.27)

BSC

0.0688 (1.75)

0.0532 (1.35)

0.0098 (0.25)

0.0040 (0.10)

0.1968 (5.00)

0.1890 (4.80)

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: OP176

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: OP176