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Электронный компонент: HCPL-M601

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CAUTION: The small device geometries inherent to the design of this bipolar component increase the component's
susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken
in handling and assembly of this component to prevent damage and/or degradation which may be induced by
ESD.
Small Outline, 5 Lead, High
CMR, High Speed, Logic Gate
Optocouplers
Technical Data
HCPL-M600
HCPL-M601
HCPL-M611
Description
These small outline high CMR,
high speed, logic gate optocoup-
lers are single channel devices in
a five lead miniature footprint.
They are electrically equivalent to
the following Agilent
optocouplers (except there is no
output enable feature):
SO-5 Package
Standard DIP
SO-8 Package
HCPL-M600
6N137
HCPL-0600
HCPL-M601
HCPL-2601
HCPL-0601
HCPL-M611
HCPL-2611
HCPL-0611
The SO-5 JEDEC registered (MO-
155) package outline does not
require "through holes" in a PCB.
This package occupies
approximately one fourth the
footprint area of the standard
dual-in-line package. The lead
profile is designed to be com-
patible with standard surface
mount processes.
The HCPL-M600/01/11 optically
coupled gates combine a GaAsP
light emitting diode and an
integrated high gain photon
detector. The output of the
detector I.C. is an Open-collector
Schottky-clamped transistor. The
internal shield provides a
guaranteed common mode
transient immunity specification of
5,000 V/
s for the HCPL-M601,
and 10,000 V/
s for the HCPL-
M611.
This unique design provides
maximum ac and dc circuit
isolation while achieving TTL
compatibility. The optocoupler ac
and dc operational parameters are
guaranteed from -40
C to 85
C
allowing trouble free system
performance.
Features
Surface Mountable
Very Small, Low Profile
JEDEC Registered Package
Outline
Compatible with Infrared
Vapor Phase Reflow and
Wave Soldering Processes
Internal Shield for High
Common Mode Rejection
(CMR)
HCPL-M601: 10,000 V/
s at
V
CM
= 50 V
HCPL-M611: 15,000 V/
s at
V
CM
= 1000 V
High Speed: 10 Mbd
LSTTL/TTL Compatible
Low Input Current
Capability: 5 mA
Guaranteed ac and dc
Performance over
Temperature: -40
C to 85
C
Recognized under the
Component Program of U.L.
(File No. E55361) for
Dielectric Withstand Proof
Test Voltage of 2500 Vac, 1
Minute
2
The HCPL-M600/01/11 are
suitable for high speed logic
interfacing, input/output
buffering, as line receivers in
environments that conventional
line receivers cannot tolerate, and
are recommended for use in
extremely high ground or induced
noise environments.
Outline Drawing (JEDEC MO-155)
Applications
Isolated Line Receiver
Simplex/Multiplex Data
Transmission
Computer-Peripheral
Interface
Microprocessor System
Interface
Digital Isolation for A/D, D/A
Conversion
Switching Power Supply
Instrument Input/Output
Isolation
Ground Loop Elimination
Pulse Transformer
Replacement
Pin Location
(for reference only)
Schematic
7.2
(0.28)
0.9
(0.04)
2.5
(0.10)
1.3
(0.05)
0.3
(0.01)
0.5
(0.02)
4.4
(0.17)
HCPL-M601/11 SHIELD
6
5
4
1
3
USE OF A 0.1 F BYPASS CAPACITOR
MUST BE CONNECTED BETWEEN PINS
6 AND 4 (SEE NOTE 1).
IF
ICC
VCC
VO
GND
IO
+
TRUTH TABLE
(POSITIVE LOGIC)
LED
ON
OFF
OUTPUT
L
H
MXXX
XXX
6
5
4
3
1
7.0 0.2
(0.276 0.008)
2.5 0.1
(0.098 0.004)
0.102 0.102
(0.004 0.004)
VCC
VOUT
GND
CATHODE
ANODE
4.4 0.1
(0.173 0.004)
1.27
(0.050)
BSG
0.15 0.025
(0.006 0.001)
0.71
(0.028)
MIN.
0.4 0.05
(0.016 0.002)
3.6 0.1*
(0.142 0.004)
"Agilent" IS MARKED ON THE
UNDERSIDE OF THE PACKAGE
DIMENSIONS IN MILLIMETERS (INCHES)
* MAXIMUM MOLD FLASH ON EACH SIDE IS 0.15 mm (0.006)
7 MAX.
MAX. LEAD COPLANARITY
= 0.102 (0.004)
3
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Input Current, Low Level
I
FL
*
0
250
A
Input Current, High Level
I
FH
5
15
mA
Supply Voltage, Output
V
CC
4.5
5.5
V
Fan Out (R
L
= 1 k
)
N
5
TTL
Loads
Output Pull-Up Resistor
R
L
330
4,000
Operating Temperature
T
A
-40
85
C
* The off condition can also be guaranteed by ensuring that V
F
(off)
0.8 volts.
Absolute Maximum Ratings
(No Derating Required up to 85
C)
Storage Temperature .................................................... -55
C to +125
C
Operating Temperature .................................................. -40
C to +85
C
Forward Input Current - I
F
(see Note 2) ....................................... 20 mA
Reverse Input Voltage - V
R
................................................................. 5 V
Supply Voltage - V
CC
(1 Minute Maximum) ........................................ 7 V
Output Collector Current - I
O
........................................................ 50 mA
Output Collector Power Dissipation ............................................ 85 mW
Output Collector Voltage - V
O
............................................................ 7 V
(Selection for higher output voltages up to 20 V is available)
Infrared and Vapor Phase Reflow Temperature ....................... see below
Maximum Solder Reflow Thermal Profile.
(Note: Use of Non-Chlorine Activated Fluxes is Recommended.)
240
T = 115C, 0.3C/SEC
0
T = 100C, 1.5C/SEC
T = 145C, 1C/SEC
TIME MINUTES
TEMPERATURE C
220
200
180
160
140
120
100
80
60
40
20
0
260
1
2
3
4
5
6
7
8
9
10
11
12
4
Electrical Specifications
Over recommended temperature (T
A
= -40
C to 85
C) unless otherwise specified. (See note 1.)
Parameter
Symbol Min. Typ.* Max.
Units
Test Conditions
Fig.
Note
Input Threshold
I
TH
2
5
mA
V
CC
= 5.5 V, I
O
13 mA, 13
Current
V
O
= 0.6 V
High Level Output
I
OH
5.5
100
A
V
CC
= 5.5 V, V
O
= 5.5 V
1
Current
I
F
= 250
A
Low Level Output
V
OL
0.4
0.6
V
V
CC
= 5.5 V, I
F
= 5 mA,
2, 4,
Voltage
I
OL
(Sinking) = 13 mA
5, 13
High Level Supply
I
CCH
4
7.5
mA
V
CC
= 5.5 V, I
F
= 0 mA,
Current
Low Level Supply
I
CCL
6
10.5
V
CC
= 5.5 V, I
F
= 10 mA,
Current
Input Forward
V
F
1.4
1.75
V
T
A
= 25
C
3
Voltage
1.5
1.3
1.85
I
F
= 10 mA
Input Reverse
BV
R
5
I
R
= 10
A
Breakdown Voltage
Input Capacitance
C
IN
60
pF
V
F
= 0V, f = 1 MHz
Input Diode
V
F
/
T
A
-1.6
mV/
C
I
F
= 10 mA
12
Temperature
Coefficient
Input-Output
V
ISO
2500
V
RMS
RH
50%, t = 1 min.
3, 4
Insulation
Resistance
R
I-O
10
12
V
I-O
= 500 V
3
(Input-Output)
Capacitance
C
I-O
0.6
pF
f = 1 MHz
3
(Input-Output)
*All typicals at T
A
= 25
C, V
CC
= 5 V.
Insulation Related Specifications
Parameter
Symbol
Value
Units
Conditions
Min. External Air Gap
L(IO1)
5
mm
Measured from input terminals
(Clearance)
to output terminals
Min. External Tracking Path
L(IO2)
5
mm
Measured from input terminals
(Creepage)
to output terminals
Min. Internal Plastic Gap
0.08
mm
Through insulation distance
(Clearance)
conductor to conductor
Tracking Resistance
CTI
175
V
DIN IEC 112/VDE 0303 Part 1
Isolation Group (per DIN VDE 0109)
IIIa
Material Group DIN VDE 0109
5
Switching Specifications
Over recommended temperature (T
A
= -40
C to 85
C), V
CC
= 5 V, I
F
= 7.5 mA unless otherwise specified.
Device
Parameter
Symbol
HCPL- Min.
Typ.* Max. Unit
Test Conditions
Fig. Note
Propagation
t
PLH
20
48
75
ns
T
A
= 25
C
6, 7 5
Delay Time
to High
100
8
Output Level
Propagation
t
PHL
25
50
75
T
A
= 25
C
6, 7
6
Delay Time
to Low
100
R
L
= 350
8
Output Level
Propagation
t
PSK
40
10,
Delay Skew
11
Pulse Width |t
PHL
- t
PLH
|
3.5
35
C
L
= 15 pF
9
10
Distortion
Output Rise
t
rise
24
Time
10
(10%-90%)
Output Fall
t
fall
10
Time
10
(10%-90%)
Common
|CM
H
|
M600
10,000
V/
s V
CM
= 10 V
V
O(min)
= 2 V
11
7, 9
M601 5,000 10,000
V
CM
= 50 V
M611 10,000 15,000
V
CM
= 1000 V
Common
|CM
H
|
M600
10,000
V
CM
= 10 V
V
O(max)
= 0.8 V 11
8, 9
M601 5,000 10,000
V
CM
= 50 V
M611 10,000 15,000
V
CM
= 1000 V
*All typicals at T
A
= 25
C, V
CC
= 5 V.
Notes:
1. Bypassing of the power supply line is required with a 0.1
F ceramic disc capacitor adjacent to each optocoupler. The total lead
length between both ends of the capacitor and the isolator pins should not exceed 10 mm.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current
does not exceed 20 mA.
3. Device considered a two terminal device: pins 1 and 3 shorted together, and pins 4, 5 and 6 shorted together.
4. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage
3000 V
RMS
for 1 second
(Leakage detection current limit, I
I-O
5
A).
5. The t
PLH
propagation delay is measured from 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the
rising edge of the output pulse.
6. The t
PHL
propagation delay is measured from 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the
falling edge of the output pulse.
7. CM
H
is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic
state (i.e., V
OUT
> 2.0 V).
8. CM
L
is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic
state (i.e., V
OUT
> 0.8 V).
9. For sinusoidal voltages, (|dV
CM
|/dt)
max
=
f
CM
V
CM(p-p)
.
10. See application section; "Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew" for more information.
11. t
PSK
is equal to the worst case difference in t
PHL
and/or t
PLH
that will be seen between units at any given temperature within
the worst case operating condition range.
Mode
Transient
Immunity at
High Output
Level
Mode
Transient
Immunity at
Low Output
Level
R
L
= 350
I
F
= 7.5 mA
T
A
= 25
C
R
L
= 350
I
F
= 0 mA
T
A
= 25
C