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Электронный компонент: HDMP-1636

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711
HDMP-1636 Transceiver
HDMP-1646 Transceiver
Features
IEEE 802.3z Gbit Ethernet
Compatible, Supports 1250
MBd Gigabit Ethernet
Based on X3T11 "10 Bit
Specification"
Low Power Consumption
Transmitter and Receiver
Functions Incorporated onto
a Single IC
Two Package Sizes
Available:
 10 mm PQFP (HDMP-1636)
14 mm PQFP (HDMP-1646)
10-Bit Wide Parallel TTL
Compatible I/Os
Single +3.3 V Power Supply
5-Volt Tolerant I/Os
2 KV ESD Protection
Applications
1250 MBd Gigabit Ethernet
Interface
High Speed Proprietary
Interface
Backplane Serialization
Bus Extender
Description
The HDMP-1636/46 transceiver is
a single silicon bipolar integrated
circuit packaged in a plastic QFP
package. It provides a low-cost,
low-power physical layer solution
for 1250 MBd Gigabit Ethernet or
proprietary link interfaces. It
Gigabit Ethernet Transceiver Chip
Preliminary Technical Data
provides complete Serialize/
Deserialize for copper transmis-
sion, incorporating both the
Gigabit Ethernet transmit and
receive functions into a single
device.
This chip is used to build a high
speed interface (as shown in
Figure 1) while minimizing board
space, power and cost. It is
compatible with the IEEE 802.3z
specification.
The transmitter section accepts
10-bit wide parallel TTL data and
multiplexes this data into a high
speed serial data stream. The
parallel data is expected to be
8B/10B encoded data, or equiv-
alent. This parallel data is latched
into the input register of the
transmitter section on the rising
edge of the 125 MHz reference
clock (used as the transmit byte
clock).
The transmitter section's PLL
locks to this user supplied 125
MHz byte clock. This clock is
then multiplied by 10, to gener-
ate the 1250 MHz serial signal
clock used to generate the high
speed output. The high speed
outputs are capable of interfacing
directly to copper cables for
electrical transmission or to a
separate fiber optic module for
optical transmission.
The receiver section accepts a
serial electrical data stream at
1250 MBd and recovers the
original 10-bit wide parallel data.
The receiver PLL locks onto the
incoming serial signal and
recovers the high speed serial
clock and data. The serial data is
converted back into 10-bit
parallel data, recognizing the
8B/10B comma character to
establish byte alignment.
The recovered parallel data is
presented to the user at TTL
compatible outputs. The receiver
section also recovers two 62.5
MHz receiver byte clocks which
are 180 degrees out of phase
with each other. The parallel data
is properly aligned with the rising
edge of alternating clocks.
For test purposes, the transceiver
provides for on-chip local loop-
back functionality, controlled
through an external input pin.
Additionally, the byte
(5/97)
712
DOUT
TX
PLL/CLOCK
GENERATOR
REFCLK
DIN
RXCAP0
RXCAP1
RBC0
RBC1
BYTSYNC
ENBYTSYNC
OUTPUT
DRIVER
INTERNAL
TX CLOCKS
INPUT
LATCH
DATA BYTE
RX[0-9]
TXCAP1
TXCAP0
DATA BYTE
TX[0-9]
INTERNAL
RX CLOCKS
LOOPEN
INTERNAL
LOOPBACK
OUTPUT
SELECT
FRAME
MUX
RX
PLL/CLOCK
RECOVERY
INPUT
SELECT
FRAME
DEMUX
AND
BYTE SYNC
INPUT
SAMPLER
HDMP-16x6
PROTOCOL DEVICE
SERIAL DATA OUT
RECEIVER SECTION
PLL
TRANSMITTER SECTION
BYTSYNC
ENBYTSYNC
REFCLK
SERIAL DATA IN
PLL
Figure 1. Typical Application Using the HDMP-16x6.
Figure 2. HDMP-16x6 Transceiver Block Diagram.
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synchronization feature may be
disabled. This may be useful in
proprietary applications which
use alternative methods to align
the parallel data.
HDMP-1636/46 Block
Diagram
The HDMP-1636/46 was
designed to transmit and receive
10-bit wide parallel data over a
single high-speed line. The
parallel data applied to the trans-
mitter is expected to be encoded
per the Gigabit Ethernet specifi-
cation, which uses an 8B/10B
encoding scheme with special
reserve characters for link
management purposes. In order
to accomplish this task, the
HDMP-1636/46 incorporates the
following:
TTL Parallel I/O's
High Speed Phase Lock Loops
Clock Generation/Recovery
Circuitry
Parallel to Serial Converter
High Speed Serial Clock and
Data Recovery Circuitry
Comma Character Recognition
Circuitry
Byte Alignment Circuitry
Serial to Parallel Converter
INPUT LATCH
The transmitter accepts 10-bit
wide TTL parallel data at inputs
TX[0..9]. The user-provided
reference clock signal, REFCLK,
is also used as the transmit byte
clock. The TX[0..9] and REFCLK
signals must be properly aligned,
as shown in Figure 3.
TX PLL/CLOCK GENERATOR
The transmitter Phase Lock Loop
and Clock Generator (TX PLL/
CLOCK GENERATOR) block is
responsible for generating all
internal clocks needed by the
transmitter section to perform its
functions. These clocks are based
on the supplied reference byte
clock (REFCLK). REFCLK is
used as both the frequency
reference clock for the PLL and
the transmit byte clock for the
incoming data latches. It is
expected to be 125 MHz and
properly aligned to the incoming
parallel data (see Figure 3). This
clock is then multiplied by 10 to
generate the 1250 MHz clock
necessary for the high speed
serial outputs.
FRAME MUX
The FRAME MUX accepts the 10-
bit wide parallel data from the
INPUT LATCH. Using internally
generated high speed clocks, this
parallel data is multiplexed into
the 1250 MBd serial data stream.
The data bits are transmitted
sequentially, from the least
significant bit (TX[0]) to the
most significant bit (TX[9]).
OUTPUT SELECT
The OUTPUT SELECT block
provides for an optional internal
loopback of the high speed serial
signal, for testing purposes.
In normal operation, LOOPEN is
set low and the serial data stream
is placed at +/- DOUT. When
wrap-mode is activated by setting
LOOPEN high, the +/- DOUT
pins are held static at logic 1 and
the serial output signal is
internally wrapped to the INPUT
SELECT box of the receiver
section.
INPUT SELECT
The INPUT SELECT block
determines whether the signal at
+/- DIN or the internal loop-back
serial signal is used. In normal
operation, LOOPEN is set low
and the serial data is accepted at
+/- DIN. When LOOPEN is set
high, the high speed serial signal
is internally looped-back from the
transmitter section to the
receiver section. This feature
allows for loop back testing
exclusive of the transmission
medium.
RX PLL/CLOCK RECOVERY
The RX PLL/CLOCK RECOVERY
block is responsible for frequency
and phase locking onto the
incoming serial data stream and
recovering the bit and byte
clocks. An automatic locking
feature allows the Rx PLL to lock
onto the input data stream
without external controls. It does
this by continually frequency
locking onto the 125 MHz clock,
and then phase locking onto the
input data stream. An internal
signal detection circuit monitors
the presence of the input, and
invokes the phase detection as
the data stream appears. Once bit
locked, the receiver generates the
high speed sampling clock at
1250 MHz for the input sampler,
and recovers the two 62.5 Mhz
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HDMP-1636/46 (Transmitter Section)
Timing Characteristics
T
A
= 0
C to +60
C, V
CC
= 3.15 V to 3.45 V
Symbol
Parameter
Units
Min.
Typ.
Max.
t
setup
Setup Time
nsec
2
t
hold
Hold Time
nsec
1
t_txlat
[1]
Transmitter Latency
nsec
TBD
bits
TBD
Note:
1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered
by the rising edge of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by
the rising edge of the first bit transmitted).
receiver byte clocks
(RBC1/RBC0). These clocks are
180 degrees out of phase with
each other, and are alternately
used to clock the 10-bit parallel
output data.
INPUT SAMPLER
The INPUT SAMPLER is respon-
sible for converting the serial
input signal into a re-timed serial
bit stream. In order to accom-
plish this, it uses the high speed
serial clock recovered from the
RX PLL/CLOCK RECOVERY
block. This serial bit stream is
sent to the FRAME DEMUX and
BYTE SYNC block.
FRAME DEMUX AND BYTE
SYNC
The FRAME DEMUX AND BYTE
SYNC block is responsible for
restoring the 10-bit parallel data
from the high speed serial bit
stream. This block is also
responsible for recognizing the
comma character (or a K28.5
character) of positive disparity
(0011111xxx). When recognized,
the FRAME DEMUX AND BYTE
SYNC block works with the RX
PLL/CLOCK RECOVERY block to
properly align the receive byte
clocks to the parallel data. When
a comma character is detected
and realignment of the receiver
byte clocks (RBC1/RBC0) is
necessary, these clocks are
stretched, not slivered, to the
next possible correct alignment
position. These clocks will be
fully aligned by the start of the
second 2-byte ordered set. The
second comma character
received shall be aligned with the
rising edge of RBC1. Comma
characters should not be trans-
mitted in consecutive bytes to
allow the receiver byte clocks to
maintain their proper recovered
frequencies.
OUTPUT DRIVERS
The OUTPUT DRIVERS present
the 10-bit parallel recovered data
byte properly aligned to the
receive byte clocks (RBC1/RBC0),
as shown in Figure 5. These
output data buffers provide TTL
compatible signals.
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Figure 3. Transmitter Section Timing.
Figure 4. Transmitter Latency.
,,
,
DATA
DATA
TX[0]-TX[9]
tSETUP
tHOLD
REFCLK
,
DATA
,
,
,
DATA
DATA
1.4 V
2.0 V
0.8 V
,,
DATA BYTE B
DATA BYTE C
TX[0]-TX[9]
DATA BYTE A
DOUT
,,
1.4 V
DATA BYTE B
t_TXLAT
T5
T6
T7
T8
T9
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T0
T1
T2
T3
T4
T5
REFCLK