ASM1232LP/LPS
Alliance Semiconductor
2575 Augustine Drive . Santa Clara, CA 95054 . Tel: 408.855.4900 . Fax: 408.855.4999 . www.alsc.com
Notice: The information in this document is subject to change without notice
January 2005
rev 1.5
5V P Power Supply Monitor and Reset Circuit
General Description
The ASM1232LP/LPS is a fully integrated microprocessor
supervisor. It can halt and restart a "hung-up" microprocessor,
restart a microprocessor after a power failure. It has a
watchdog timer and external reset override.
A precision temperature-compensated reference and
comparator circuits monitor the 5V, V
CC
input voltage status.
During power-up or when the V
CC
power supply falls outside
selectable tolerance limits, both RESET and RESET become
active. When V
CC
rises above the threshold voltage, the reset
signals remain active for an additional 250ms minimum,
allowing the power supply and system microprocessor to
stabilize. The trip point tolerance signal, TOL, selects the trip
level tolerance to be either 5% or 10%.
Each device has both a push-pull, active HIGH reset output
and an open drain active LOW reset output. A debounced
manual reset input, PBRST, activates the reset outputs for a
minimum period of 250ms.
There is a watchdog timer to stop and restart a microprocessor
that is "hung-up". The watchdog timeouts periods are
selectable: 150ms, 610ms and 1200ms. If the ST input is not
strobed LOW before the time-out period expires, a reset is
generated.
Devices are available in 8-pin DIP, 16-pin SO and compact 8-
pin MicroSO packages.
Key Features
5V supply monitor
Selectable watchdog period
Debounce manual push-button reset input
Precision temperature-compensated voltage reference
and comparator.
Power-up, power-down and brown out detection
250ms minimum reset time
Active LOW open drain reset output and active HIGH
push-pull output
Selectable trip point tolerance: 5% or 10%
Low-cost surface mount packages: 8-pin/16-pin SO, 8-pin
DIP and 8-pin Micro SO packages
Wide operating temperature -40C to +85C (N suffixed
devices)
Applications
Microprocessor Systems
Computers
Controllers
Portable Equipment
Intelligent Instuments
Automotive Systems
Typical Operating Circuit
Block Diagram
ASM1232LP/LPS
ST
RESET
GND
TD
TOL
I/O
RESET
P
10k
+5V
Tolerance Selection
Reference
Push Button
Voltage Sense
Watchdog Transition
Reset &
Debounce
Comparators
Detector
Watchdog Timer
+
-
RESET
RESET
PBRST
ST
TD
TOL
V
CC
GND
40k
V
CC
ASM1232LP/LPS
ASM1232LP/LPS
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Notice: The information in this document is subject to change without notice
5V P Power Supply Monitor and Reset Circuit
January 2005
rev 1.5
Pin Configuration
Pin Description
Pin #
8-Pin Package
Pin #
16-Pin Package
Pin
Name
Function
1
2
PBRST
Debounced manual pushbutton RESET input.
2
4
TD
Watchdog time delay selection. (t
TD
= 150ms for TD = GND, t
TD
= 610ms
for TD=Open, and t
TD
= 1200ms for TD = V
CC
).
3
6
TOL
Selects 5% (TOL connected to GND) or 10% (TOL connected to V
CC
)
trip point tolerance.
4
8
GND
Ground.
5
9
RESET
Active HIGH reset output. RESET is active:
1. If V
CC
falls below the reset voltage trip point.
2. If PBRST is LOW.
3. If ST is not strobed LOW before the timeout period set by TD expires.
4. During power-up.
6
11
RESET
Active LOW reset output. (See RESET).
7
13
ST
Strobe input.
8
15
V
CC
5V power.
-
1,3,5,7,
10,12,14,16
NC
No internal connection.
1
2
3
4
5
6
7
8
PBRST
TD
TOL
GND
V
CC
ST
RESET
RESET
1
2
3
4
5
6
7
8
PBRST
TD
TOL
GND
V
CC
ST
RESET
RESET
ASM1232LPS
9
10
11
12
13
14
15
16
NC
NC
NC
NC
NC
NC
NC
NC
ASM1232LPU
DIP/SO/MicroSO
SO
ASM1232LP
ASM1232LPS-2
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Notice: The information in this document is subject to change without notice
5V P Power Supply Monitor and Reset Circuit
ASM1232LP/LPS
January 2005
rev 1.5
Detailed Description
The ASM1232LP/LPS monitors the microprocessor or
microcontroller power supply and generates reset signal,
both active HIGH and Active LOW, that halt processor
operation whenever the power supply voltage levels are
outside a predetermined tolerance.
RESET and RESET outputs
RESET is an active HIGH signal developed by a CMOS
push-pull output stage and is the logical opposite to RESET.
RESET is an active LOW signal. It is developed with an open
drain driver. A pull up resistor of typical value 10k
to 50k is
required to connect with the output.
Trip Point Tolerance Selection
The TOL input is used to determine the level V
CC
can vary
below 5V without asserting a reset. With TOL conected to
V
CC
, RESET and RESET become active whenever V
CC
falls
below 4.5V. RESET and RESET become active when the
V
CC
falls below 4.75V if TOL is connected to ground.
After V
CC
has risen above the trip point set by TOL, RESET
and RESET remain active for a minimum time period of
250ms. On power-down, once V
CC
falls below the reset
threshold RESET stays LOW and is guaranteed to be 0.4V or
less until V
CC
drops below 1.2V. The active HIGH reset signal
is valid down to a V
CC
level of 1.2V also.
Application Information
Manual Reset Operation
Push-button switch input, PBRST, allows the user to override
the internal trip point detection circuits and issue reset
signals. The pushbutton input is debounced and is pulled
HIGH through an internal 40k
resistor.
Tolerance
Select
Tolerance
TRIP Point Voltage
(V)
Min
Nom
Max
TOL = V
CC
10%
4.25
4.37
4.49
TOL = GND
5%
4.5
4.62
4.74
~~
~~~~
V
OH
V
OL
t
RPU
RESET
RESET
V
CCTP
(MIN)
V
CCTP
(MAX)
V
CCTP
t
R
V
CC
Figure 1: Timing Diagram : Power Up
~ ~
~~
~~
V
OH
V
OL
V
CCTP
(MAX)
V
CCTP
V
CCTP
(MIN)
RESET
RESET
t
F
V
CC
t
RPD
Figure 2: Timing Diagram : Power Down
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Notice: The information in this document is subject to change without notice
5V P Power Supply Monitor and Reset Circuit
ASM1232LP/LPS
January 2005
rev 1.5
When PBRST is held LOW for the minimum time t
PB
, both
resets become active and remain active for a minimum time
period of 250ms after PBRST returns HIGH.
The debounced input is guaranteed to recognize pulses
greater than 20ms. No external pull-up resistor is required,
since PBRST is pulled HIGH by an internal 40k
resistor.
The PBRST can be driven from a TTL or CMOS logic line or
shorted to ground with a mechanical switch.
Watchdog Timer and ST Input
A watchdog timer stops and restarts a microprocessor that is
"hung-up". The P must toggle the ST input within a set
period (as selectable through TD input) to verify proper
software execution. If the ST is not toggled low within the
minimum timeout period, reset signals become active. In
power-up after the supply voltage returns to an in-tolerance
condition, the reset signal remains active for 250ms
minimum, allowing the power supply and system
microprocessor to stabilize. ST pulses as short as 20ns can
be detected.
Timeouts periods of approximately 150ms, 610ms or
1,200ms are selected through the TD pin.
The watchdog timer can not be disabled. It must be strobed
with a high-to-low transition to avoid watchdog timeout and
reset.
TD Voltage level
Watchdog Time-out Period
(ms)
Min
Nom
Max
GND
62.5
150
250
Floating
250
610
1000
V
CC
500
1200
2000
~ ~
~ ~
~ ~
V
OH
V
OL
RESET
RESET
PBRST
t
PB
t
PDLY
V
IH
t
RST
Figure 3: Timing Diagram: Pushbutton Reset
PBRST
TD
TOL
GND
V
CC
ST
RESET
RESET
1
2
3
4
5
6
7
8
P
RESET
5V
ASM1232LP/LPS
Figure 4: Application Circuit: Pushbutton Reset
~ ~
Valid
Valid
Invalid
ST
RESET
t
RST
t
ST
t
TD
(min)
t
TD
(max)
Strobe
Strobe
Strobe
Figure 5: Timing Diagram: Strobe Input
Note: ST is ignored whenever a reset is active
PBRST
T
D
TOL
GND
V
CC
ST
RESET
1
2
3
4
5
6
7
8
P
RESET
5V
ASM1232 LP/LPS
Figure 6: Application Circuit: Watchdog Timer
Decoder
Address
Bus
MREQ
10k
V
IL
I/O
ASM1232LP/LPS
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Notice: The information in this document is subject to change without notice
5V P Power Supply Monitor and Reset Circuit
January 2005
rev 1.5
Absolute Maximum Ratings
DC Electrical Characteristics
Unless otherwise stated, 4.5V <= V
CC
<= 5.5V and over the operating temperature range of 0C to 70C (-40C to +85C. for N devices). All
voltages are referenced to ground.
Parameter
Min
Max
Unit
Voltage on V
CC
-0.5
7
V
Voltage on ST, TD
-0.5
V
CC
+ 0.5
V
Voltage on PBRST, RESET, RESET
-0.5
V
CC
+ 0.5
V
Operating Temperature Range (N suffixed devices)
-40
+85
C
Operating Temperature Range (others)
0
70
C
Soldering Temperature (for 10 sec)
+260
C
Storage Temperature
-55
+125
C
ESD rating
HBM
MM
2
200
KV
V
Note:
1. Voltages are measured with respect to ground
2. These are stress ratings only and functional implication is not implied. Exposure to absolute maximum ratings for extended
periods may affect device reliability.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Supply Voltage
V
CC
4.5
5.5
V
ST and PBRST Input High Level
V
IH
2
V
CC
+ 0.3
V
ST and PBRST Input Low Level
V
IL
-0.3
0.8
V
V
CC
Trip Point (T
OL
= GND)
V
CCTP
4.50
4.62
4.74
V
V
CC
Trip Point (T
OL
= V
CC
)
V
CCTP
4.25
4.37
4.49
V
Watchdog Timeout Period
t
TD
T
D
= GND
62.5
150
250
ms
Watchdog Timeout Period
t
TD
T
D
= VCC
500
1200
2000
ms
Watchdog Timeout Period
t
TD
T
D
Floating
250
610
1000
ms
Output Voltage
V
OH
I=-500A, Note 3
V
CC
- 0.5
V
CC
- 0.1
V
Output Current
I
OH
Output = 2.4V, Note 2
-8
-10
mA
Output Current
I
OL
Output = 0.4V
10
mA
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