Altera Corporation

March 2003, ver. 1.1

Data Sheet

DS-CYCONFIG-1.1

Features

1- and 4-Mbit flash memory devices that serially configure Cyclone

FPGAs

Easy-to-use four-pin interface

Low cost, low pin count and non-volatile memory

Low current during configuration and near-zero standby mode
current

3.3-V operation

Available in 8-pin small outline integrated circuit (SOIC) package

Enables the Nios

processor to access unused flash memory through

active serial (AS) memory interface

Re-programmable memory with more than 100,000 erase/program
cycles

Programming support with ByteBlaster

II download cable

Additional programming support with the Altera

Programming

Unit (APU) and programming hardware from BP Microsystems,
System General, and other vendors

Software design support with the Altera Quartus

II development

system for Windows-based PCs as well as Sun SPARC station and
HP 9000 Series 700/800

Delivered with the memory array erased (all the bits set to

)

Figure 1

shows the Altera serial configuration device 8-pin SOIC package

and its pin-out diagram.

Figure 1. Altera Serial Configuration Device Package Pin-Out Diagram

Whenever the term "serial configuration device(s)" is used in
this document, it refers to Altera EPCS1 and EPCS4 devices.

DCLK

ASDI

GND

nCS

DATA

EPCS1 or

EPCS4 Device

Serial Configuration

Devices

(EPCS1 & EPCS4)

Altera Corporation

Serial Configuration Devices (EPCS1 & EPCS4) Data Sheet

Functional
Description

With SRAM-based devices such as Cyclone FPGAs, configuration data
must be reloaded each time the system initializes, or when a new
configuration is needed. Serial configuration devices are flash memory
devices with a serial interface that can store configuration data for a
Cyclone device and reload the data to the device upon power-up or
reconfiguration.

Table 1

lists the serial configuration devices.

Table 2

lists the serial configuration device used with each Cyclone FPGA

and the configuration file size.

Note to

Table 2

(1)

These are preliminary, uncompressed file sizes.

With the new data-decompression feature in the Cyclone FPGA family,
designers can use smaller serial configuration devices to configure larger
Cyclone FPGAs. Serial configuration devices cannot be cascaded.

See

AN 250: Configuring Cyclone FPGAs

for more information regarding

the Cyclone FPGA decompression feature in AS mode.

The serial configuration devices are designed to configure Cyclone FPGAs
and cannot configure other existing device families.

Figure 2

shows the

serial configuration device block diagram.

Table 1. Serial Configuration Devices (3.3-V Operation)

Device

Memory Size (Bits)

EPCS1

1,048,576

EPCS4

4,194,304

Table 2. Serial Configuration Device for Cyclone Devices

Cyclone Device

Configuration

File Size

(Mbits)

(1)

Serial Configuration Device

EPCS1

EPCS4

EP1C3

0.628

EP1C4

0.925

EP1C6

1.167

EP1C12

2.324

EP1C20

3.559

Altera Corporation

Serial Configuration Devices (EPCS1 & EPCS4) Data Sheet

Figure 2. Serial Configuration Device Block Diagram

Accessing
Memory in
Serial
Configuration
Devices

A designer can access the unused memory locations of the serial
configuration device through the Nios processor and SOPC Builder to
store/retrieve data or configuration files. SOPC Builder is an Altera tool
for creating bus-based (especially microprocessor-based) systems in
Altera devices. SOPC Builder assembles library components like
processors and memories into custom microprocessor systems.

SOPC Builder includes an interface core specifically for the serial
configuration device. Using this core, a designer can create a system with
a Nios embedded processor that allows software access to any memory
location within the serial configuration device.

For more information on accessing memory within the serial
configuration device, contact Altera Applications.

Control

Logic

I/O Shift

Memory

Array

Status Register

Address Counter

Decode Logic

Data Buffer

nCS

DCLK

DATA

ASDI

Serial Configuration Device

Altera Corporation

Serial Configuration Devices (EPCS1 & EPCS4) Data Sheet

Pin Description

As shown in

Figure 1

, the serial configuration device is an 8-pin device.

The control pins on the serial configuration device are: serial data output
(

DATA

), active serial data input (

ASDI

), serial clock (

DCLK

), and chip select

(

nCS

Table 3

shows the serial configuration device's pin descriptions.

Programming
& Configuration
File Support

The Quartus II design software provides programming support for serial
configuration devices. After selecting the serial configuration device, the
Quartus II software automatically generates the Programmer Object File
(.pof) to program the device. The software allows users to select the
appropriate serial configuration device density that most efficiently stores
the configuration data for a selected Cyclone FPGA.

Serial configuration devices are programmed using the APU with the
appropriate programming adapter (PLMSEPC-8) via the Quartus II
software or the ByteBlaster II download cable via the Quartus II software.
In addition, many third-party programmers, such as BP Microsystems
and System General, offer programming hardware that supports serial
configuration devices.

Table 3. Serial Configuration Device Pin Description

Pin Name

Pin Number

Pin Type

Description

DATA

Output

DATA

output signal transfers the data serially out of the serial

configuration device into the Cyclone FPGA during
read/configuration operation. During a read/configuration operation,

the serial configuration device is enabled by pulling

nCS

low. The

DATA

signal transitions on the falling edge of

DCLK

ASDI

Input

Active serial data input signal is used to transfer data serially into the
serial configuration device. It receives the data that should be

programmed into the serial configuration device. Values register on
the rising edge of

DCLK

nCS

Input

Active low chip select input signal toggles at the beginning and end
of a valid instruction. When this signal is high, the device is

deselected and the

DATA

signal is tri-stated. When the signal is low,

it enables the device and puts the device in an active mode. After

power up, the serial configuration device requires a falling edge on
the

nCS

signal before beginning any operation.

DCLK

Input

DCLK

is provided by the Cyclone FPGA. This signal provides the

timing of the serial interface. The data presented at

ASDI

are latched

in to the serial configuration device, at the rising edge of

DCLK

. Data

on the

DATA

pin changes after the falling edge of

DCLK

and is latched

into the Cyclone FPGA on the rising edge.

VCC

3, 7, 8

Power

Power pins connect to 3.3 V.

GND

Ground

Ground pin.

Altera Corporation

Serial Configuration Devices (EPCS1 & EPCS4) Data Sheet

During in-system programming of a serial configuration device via the
ByteBlaster II download cable, the cable pulls

nCONFIG

low to reset the

Cyclone device and overrides the 10-k pull-down resistors on the
Cyclone device's

nCE

pin (see

Figure 5

). The download cable then uses the

four interface pins (

DATA

nCS

ASDI

, and

DCLK

) to program the serial

configuration device memory. Once the programming is complete, the
download cable releases the serial configuration device's four interface
pins and the Cyclone device's

nCE

pin, and pulses

nCONFIG

to start

configuration.

Figure 3

shows the timing waveform for write operation to the serial

configuration device.

Figure 3. Write Operation Timing

nCS

DCLK

ASDI

DATA

NCSH

DSU

NCSSU

CSH

Bit

Bit 0

Bit

High Impedance

Электронный компонент: EPCS4SI8N

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