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Электронный компонент: S2104

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1
S2104
QUAD FIBRE CHANNEL DEVICE
July 14, 1999 / Revision C
S2104
QUAD FIBRE CHANNEL DEVICE
DEVICE
SPECIFICATION
MAC
(ASIC)
S2004
QUAD
FIBRE
CHANNEL
INTERFACE
MAC
(ASIC)
MAC
(ASIC)
MAC
(ASIC)
TO SERIAL BACKPLANE
S2104
FC INTERFACE
SERIAL BP DRIVER
Figure 1. Typical Quad Fibre Channel Application
FEATURES
1062 MHz (Fibre Channel) operating rate
- 1/2 Rate Operation
Quad Transmitter with phase-locked loop (PLL)
clock synthesis from low speed reference
Quad Receiver PLL provides clock and data
recovery
Internally series terminated TTL outputs
Low-jitter serial PECL interface
Individual local loopback control
JTAG 1149.1 Boundary scan on low speed I/O
signals
Interfaces with coax, twinax, or fiber optics
Single +3.3V supply, 2.5 W power dissipation
Compact 23mm x 23mm 208 TBGA package
APPLICATIONS
Workstation
Frame buffer
Switched networks
Data broadcast environments
Proprietary extended backplanes
GENERAL DESCRIPTION
The S2104 facilitates high-speed serial transmission
of data in a variety of applications including Fibre
Channel, serial backplanes, and proprietary point to
point links. The chip provides four separate trans-
ceivers which can be operated individually for a data
capacity of >4 Gbps.
Each bi-directional channel provides parallel to serial
and serial to parallel conversion, clock generation/
recovery, and framing. The on-chip transmit PLL
synthesizes the high-speed clock from a low-speed
reference. The on-chip quad receive PLL is used for
clock recovery and data re-timing on the four inde-
pendent data inputs. The transmitter and receiver
each support differential PECL-compatible I/O for
copper or fiber optic component interfaces with ex-
cellent signal integrity. Local loopback mode allows
for system diagnostics. The chip requires a 3.3V
power supply and dissipates 2.5 watts.
Figure 1 shows the S2104 and S2004 in a Fibre
Channel application. Figure 2 combines the S2104
with a crosspoint switch to demonstrate a serial
backplane application. Figure 3 is the input/output
diagram. Figures 4 and 5 show the transmit and
receive block diagrams, respectively.
2
QUAD FIBRE CHANNEL DEVICE
S2104
July 14, 1999 / Revision C
Figure 2. Typical Backplane Application
MAC
(ASIC)
S2004
ATM
Fibre
Channel
Etc.
MAC
(ASIC)
MAC
(ASIC)
MAC
(ASIC)
Crosspoint
Switch
S2016
S2025
MAC
(ASIC)
S2004
S2104
S2104
ATM
Fibre
Channel
Etc.
MAC
(ASIC)
MAC
(ASIC)
MAC
(ASIC)
MAC
(ASIC)
S2004
ATM
Fibre
Channel
Etc.
MAC
(ASIC)
MAC
(ASIC)
MAC
(ASIC)
MAC
(ASIC)
S2004
S2104
S2104
ATM
Fibre
Channel
Etc.
ATM
Fibre
Channel
Etc.
MAC
(ASIC)
MAC
(ASIC)
MAC
(ASIC)
BACKPLANE SIGNAL GROUP
3
S2104
QUAD FIBRE CHANNEL DEVICE
July 14, 1999 / Revision C
Figure 3. S2104 Input/Output Diagram
REFCLK
TMODE
RATE
RESET
TCLKO
TXAP/N
TXBP/N
TXCP/N
TXDP/N
RXAP/N
RXBP/N
RXCP/N
RXDP/N
DINA[0:9]
10
DINB[0:9]
10
DINC[0:9]
10
DIND[0:9]
10
TBCA
TBCB
TBCC
TBCD
10
RBC1/0A
10
RBC1/0B
10
RBC1/0C
10
RBC1/0D
DOUTA[0:9]
DOUTB[0:9]
DOUTC[0:9]
DOUTD[0:9]
TESTMODE
TESTMODE1
CLKSEL
COM_DETA
COM_DETB
COM_DETC
COM_DETD
CMODE
LPENA
LPENB
LPENC
LPEND
TRS
TMS
TCK
TDI
TDO
4
QUAD FIBRE CHANNEL DEVICE
S2104
July 14, 1999 / Revision C
Figure 4. Transmitter Block Diagram
TMODE
10
DINA[0:9]
10
Shift
Reg
10
DINB[0:9]
10
Shift
Reg
TBCB
10
DINC[0:9]
10
Shift
Reg
TBCC
10
DIND[0:9]
10
Shift
Reg
TBCD
DIN PLL
10x/20x
REFCLK
CLKSEL
RATE
REFCLK
TCLKO
FIFO
(input)
FIFO
(input)
FIFO
(input)
FIFO
(input)
TBCA
TXAP
TXAN
TXABP
TXBP
TXBN
TXBBP
TXCP
TXCN
TXCBP
TXDP
TXDN
TXDBP
TMODE
0 1
0 1
0 1
0 1
5
S2104
QUAD FIBRE CHANNEL DEVICE
July 14, 1999 / Revision C
Figure 5. Receiver Block Diagram
DOUT CRU
Serial-
Parallel
DOUT CRU
Serial-
Parallel
COM_DETA
DOUTA[0:9]
RXAP
RXAN
LPENA
RXBP
RXBN
LPENB
COM_DETB
DOUTB[0:9]
Q
FIFO
(output)
DOUT CRU
Serial-
Parallel
COM_DETD
DOUTD[0:9]
RXDP
RXDN
LPEND
DOUT CRU
Serial-
Parallel
COM_DETC
DOUTC[0:9]
RXCP
RXCN
LPENC
TXDBP
TXCBP
TXBBP
TXABP
REFCLK
10
10
10
10
RBC1/0B
2
RBC1/0C
2
RBC1/0D
2
CMODE
RATE
FIFO
(output)
FIFO
(output)
FIFO
(output)
10
10
10
10
TMODE
RBC1/0A
2