1
S3032
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
April 18, 2000 / Revision E
BiCMOS LVPECL CLOCK GENERATOR
DEVICE
SPECIFICATION
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
S3032
FEATURES
Complies with Bellcore and ITU-T
specifications
On-chip high-frequency PLLs for clock
generation and clock recovery
Supports 155.52 Mbit/s (OC-3) and 622.08
Mbit/s (OC-12)
Selectable reference frequencies of 19.44,
38.88, 51.84 or 77.76 MHz
Interface to both LVPECL and LVTTL logic
Simple interface with 3.3V or 5V optical modules
Directly compatible with 3.3V or 5V network
interface devices
8-bit LVTTL data path
Compact 10 mm 64 PQFP package
Diagnostic loopback mode
Low jitter LVPECL serial interface
Single 3.3 V supply
APPLICATIONS
SONET/SDH-based transmission systems
SONET/SDH modules
SONET/SDH test equipment
ATM over SONET/SDH
Section repeaters
Add Drop Multiplexers (ADM)
Broad-band cross-connects
Fiber optic terminators
Fiber optic test equipment
Figure 1. System Block Diagram
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
S3032
GENERAL DESCRIPTION
The S3032 SONET/SDH transceiver chip is a fully
integrated serialization/deserialization SONET OC-12
(622.08 Mbit/s) and OC-3 (155.52 Mbit/s) interface de-
vice. The chip performs all necessary serial-to-parallel
and parallel-to-serial functions in conformance with
SONET/SDH transmission standards. The device is
suitable for SONET-based ATM applications. Figure
1 shows a typical network application.
On-chip clock synthesis is performed by the high-
frequency phase-locked loop on the S3032
transceiver chip allowing the use of a slower external
transmit clock reference. Clock recovery is performed
on the device by synchronizing its on-chip VCO directly
to the incoming data stream. The S3032 also per-
forms SONET/SDH frame detection. The chip can be
used with a 19.44, 38.88, 51.84 or 77.76 MHz refer-
ence clock, in support of existing system clocking
schemes.
The low jitter LVPECL interface guarantees compli-
ance with the bit-error rate requirements of the
Bellcore and ITU-T standards. The S3032 is pack-
aged in a 10 mm 64 PQFP, offering designers a small
package outline.
S3032
SONET/SDH
Transceiver
Network
Interface
Processor
Network
Interface
Processor
S3032
SONET/SDH
Transceiver
OTX
ORX
OTX
ORX
8
8
8
8
2
S3032
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
April 18, 2000 / Revision E
SONET OVERVIEW
Synchronous Optical Network (SONET) is a stan-
dard for connecting one fiber system to another at
the optical level. SONET, together with the Synchro-
nous Digital Hierarchy (SDH) administered by the
ITU-T, forms a single international standard for fiber
interconnect between telephone networks of differ-
ent countries. SONET is capable of accommodating
a variety of transmission rates and applications.
The SONET standard is a layered protocol with four
separate layers defined. These are:
Photonic
Section
Line
Path
Figure 2 shows the layers and their functions. Each
of the layers has overhead bandwidth dedicated to
administration and maintenance. The photonic layer
simply handles the conversion from electrical to opti-
cal and back with no overhead. It is responsible for
transmitting the electrical signals in optical form over
the physical media. The section layer handles the
transport of the framed electrical signals across the
optical cable from one end to the next. Key functions
of this layer are framing, scrambling, and error moni-
toring. The line layer is responsible for the reliable
transmission of the path layer information stream
carrying voice, data, and video signals. Its main
functions are synchronization, multiplexing, and reli-
able transport. The path layer is responsible for the
actual transport of services at the appropriate signal-
ing rates.
Data Rates and Signal Hierarchy
Table 1 contains the data rates and signal designations
of the SONET hierarchy. The lowest level is the basic
SONET signal referred to as the synchronous transport
signal level-1 (STS-1). An STS-
N signal is made up
of
N byte-interleaved STS-1 signals. The optical
counterpart of each STS-
N signal is an optical carrier
level-
N signal (OC-N). The S3032 chip supports OC-3
and OC-12 rates (155.52 and 622.08 Mbit/s).
Frame and Byte Boundary Detection
The SONET/SDH fundamental frame format for
STS-12 consists of 36 transport overhead bytes fol-
lowed by Synchronous Payload Envelope (SPE)
bytes. This pattern of 36 overhead and 1044 SPE bytes
is repeated nine times in each frame. Frame and byte
boundaries are detected using the A1 and A2 bytes
found in the transport overhead. (See Figure 3.)
For more details on SONET operations, refer to the
Bellcore SONET standard document.
Elec.
ITU-T
Optical Data Rate (Mbit/s)
STS-1
OC-1
51.84
STS-3
STM-1
OC-3
155.52
STS-12
STM-4
OC-12
622.08
STS-24
STM-8
OC-24
1244.16
STS-48 STM-16
OC-48 2488.32
Table 1. SONET Signal Hierarchy
Figure 2. SONET Structure
Figure 3. STS12/OC12 Frame Format
0 bps
End Equipment
Payload to
SPE mapping
Maintenance,
protection,
switching
Optical
transmission
Scrambling,
framing
Fiber Cable
End Equipment
Section layer
Photonic layer
Line layer
Path layer
Path layer
Section layer
Photonic layer
Line layer
Layer Overhead
(Embedded Ops
Channel)
Functions
576 Kbps
192 Kbps
9 Rows
12 A1
Bytes
12 A2
Bytes
A1 A1
A1 A1
A2 A2
A2 A2
Transport Overhead 36 Columns
36 x 9 = 324 bytes
Synchronous Payload Envelope 1044 Columns
1044 x 9 = 9396 bytes
125
sec
v
v
3
S3032
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
April 18, 2000 / Revision E
S3032 OVERVIEW
The S3032 transceiver implements SONET/SDH se-
rialization/deserialization, transmission, and frame
detection/recovery functions. The block diagram in
Figure 4 shows the basic operation of the chip. This
chip can be used to implement the front end of
SONET equipment, which consists primarily of the
serial transmit interface and the serial receive inter-
face. The chip handles all the functions of these two
elements, including parallel-to-serial and serial-to-par-
allel conversion, clock generation and recovery, and
system timing. The system timing circuitry consists
of management of the data stream, framing, and
clock distribution throughout the front end.
The S3032 is divided into a transmitter section and a
receiver section. The sequence of operations is as
follows:
Transmitter Operations:
1. 8-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Receiver Operations:
1. Clock and data recovery from serial input
2. Frame detection
3. Serial-to-parallel conversion
4. 8-bit parallel output
Internal clocking and control functions are transpar-
ent to the user. Details of data timing can be seen in
Figures 8 through 14.
Figure 4. S3032 Transceiver Functional Block Diagram
1:8 SERIAL-
TO-PARALLEL
TIMING
GEN
M
U
X
CLOCK
RECOVERY
TESTEN
RSDP/N
FRAME
BYTE
DETECT
DLEB
OOF
FP
POUT[7:0]
8
BACKUP
REFERENCE
GEN
POCLK
8
PIN[7:0]
8:1 PARALLEL-
TO-SERIAL
TSDP/N
PICLK
TIMING
GEN
PCLK
CLOCK
SYNTHESIZER
RSTB
D
TESTEN
MODE 0
MODE 1
CAP1
CAP2
Transmitter
Receiver
TSCLKP/N
LLEB
SLPTIME
REFCLKP/N
TTLREF
SDPECL
AMCC
CONGO (S1201) POS/ATM SONET Mapper
AMCC
NILE (S1202) ATM SONET Mapper
Suggested Interface Devices
4
S3032
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
April 18, 2000 / Revision E
S3032 TRANSCEIVER
FUNCTIONAL DESCRIPTION
TRANSMITTER OPERATION
The S3032 transceiver chip performs the serializing
stage in the processing of a transmit SONET STS-3
or STS-12 bit serial data stream. It converts the 8-bit
parallel 19.44 or 77.76 Mbps data stream into bit
serial format at 155.52 or 622.08 Mbit/sec.
A high-frequency bit clock can be generated from a
19.44, 38.88, 51.84 or 77.76 MHz frequency refer-
ence by using an integral frequency synthesizer
consisting of a phase-locked loop circuit with a di-
vider in the loop.
Diagnostic loopback is provided (transmitter to re-
ceiver). See Other Operating Modes on page 7.
Clock Synthesizer
The clock synthesizer, shown in the block diagram in
Figure 4, is a monolithic PLL that generates the se-
rial output clock phase synchronized with the input
reference clock (REFCLKP/N or TTLREF).
The REFCLKP/N input must be generated from an
LVPECL crystal oscillator which has a frequency ac-
curacy that meets the value stated in Table 8 in
order for the TSCLK frequency to have the same
accuracy required for operation in a SONET system.
Lower accuracy crystal oscillators may be used in
applications less demanding than SONET/SDH.
TTLREF must be at logic "one" if REFCLKP/N are
used.
For TTL reference operation, the TTLREF input
should be driven with an LVTTL crystal oscillator
output with the ppm accuracy specified in Table 8 for
SONET compliance. In this mode, REFCLKP should
be connected to LVPECL "High" and REFCLKN
should be tied to LVPECL "Low."
The on-chip PLL consists of a phase detector, which
compares the phase relationship between the VCO out-
put and the REFCLKP/N input, a loop filter which converts
the phase detector output into a smooth DC voltage,
and a VCO, whose frequency is varied by this voltage.
The loop filter generates a VCO control voltage
based on the average DC level of the phase discrimi-
nator output pulses. The loop filter's corner frequency
is optimized to minimize output phase jitter.
Timing Generation
The timing generation function, seen in Figure 4,
provides a byte rate version of the transmit serial
clock. This circuitry also provides an internally generated
load signal, which transfers the PIN[7:0] data from
the parallel input register to the serial shift register.
The PCLK output is a byte rate version of transmit
serial clock at 19.44 or 77.76 MHz. PCLK is intended
for use as a byte speed clock for upstream multiplex-
ing and overhead processing circuits. Using PCLK
for upstream circuits will ensure a stable frequency
and phase relationship between the data coming into
and leaving the S3032 device.
Parallel-to-Serial Converter
The parallel-to-serial converter shown in Figure 4 is
comprised of two byte-wide registers. The first regis-
ter latches the data from the PIN[7:0] bus on the
rising edge of PICLK. The second register is a paral-
lel loadable shift register which takes its parallel
input from the first register.
The load signal, which latches the data from the par-
allel to the serial shift register, has a fixed
relationship to PCLK. If PICLK is tied to PCLK, the
PIN[7:0] data latched into the parallel register will
meet the timing specifications with respect to the
load signal. If PICLK is not tied to PCLK, the delay
must meet the timing requirements shown in Figure 9.
Table 2. Reference Frequency Options
Table 3. Reference Jitter Limits
d
n
a
B
y
c
n
e
u
q
e
r
F
k
c
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l
C
e
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e
f
e
R
m
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m
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x
a
M
r
e
t
t
i
J
g
n
i
t
a
r
e
p
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e
d
o
M
z
H
M
5
o
t
z
H
k
2
1
s
m
r
s
p
4
1
2
1
S
T
S
z
H
M
1
o
t
z
H
k
2
1
s
m
r
s
p
6
5
3
S
T
S
* Only valid in SLP mode.
E
D
O
M
]
0
:
1
[
K
C
O
L
C
E
C
N
E
R
E
F
E
R
Y
C
N
E
U
Q
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R
F
G
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I
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A
R
E
P
O
E
D
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M
0
0
z
H
M
4
4
.
9
1
2
1
-
S
T
S
1
0
z
H
M
8
8
.
8
3
2
1
-
S
T
S
0
1
z
H
M
4
8
.
1
5
2
1
-
S
T
S
1
1
z
H
M
6
7
.
7
7
2
1
-
S
T
S
C
N
0
z
H
M
4
4
.
9
1
3
-
S
T
S
C
N
1
z
H
M
8
8
.
8
3
3
-
S
T
S
0
C
N
z
H
M
4
8
.
1
5
3
-
S
T
S
1
C
N
z
H
M
6
7
.
7
7
*
3
-
S
T
S
5
S3032
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
April 18, 2000 / Revision E
The loop filter transfer function is optimized to en-
able the PLL to track the jitter, yet tolerate the
minimum transition density expected in a received
SONET data signal. This transfer function yields the
typical capture time stated in Table 8 for random
incoming NRZ data. A single external clean-up ca-
pacitor is utilized as part of the loop filter.
The total loop dynamics of the clock recovery PLL
yield a jitter tolerance which exceeds the minimum
tolerance proposed for SONET equipment by the
Bellcore TA-NWT-000253 standard, shown in Figure 5.
Lock Detect
The S3032 contains a lock detect circuit which monitors
the integrity of the serial data inputs. If the received
serial data fails the run length or frequency test, the PLL
will be forced to lock to the local reference clock. This
will maintain the correct frequency of the POCLK output
under loss of signal or loss of lock conditions. If the serial
data inputs have a run length of 80-bit times with no
transitions, the PLL will be declared out of lock. In
addition, if the recovered clock frequency deviates from
the local reference clock frequency by more than the
specified ppm, the PLL will also be declared out of lock.
The lock detect circuit will poll the input data stream in
an attempt to reacquire lock to data. If the recovered
clock frequency is determined to be within the specified
ppm and the run length check indicates valid data, the
PLL will be declared in lock and the lock detect output
will go active. The deassertion of SDPECL will also
cause an out-of-lock condition. (See Table 8).
Backup Reference Generator
The backup reference generator seen in Figure 4
provides backup reference clock signals to the clock
recovery block when the clock recovery block de-
tects a loss of signal condition. It contains a counter
that divides the clock output from the clock recovery
block down to the same frequency as the reference
clock, REFCLKP/N.
Figure 5. Clock Recovery Jitter Tolerance
25k 65k
250k
6.5k
300
30
0.15
1.5
15
Jitter Frequency (Hz)
Jitter
Amplitude
(Ul p-p)
Minimum proposed
tolerance
(TA-NWT-000253)
OC-12
OC-3
RECEIVER OPERATION
The S3032 transceiver chip provides the first stage
of digital processing of a receive SONET STS-3 or
STS-12 bit-serial stream. It converts the bit-serial
155.52 or 622.08 Mbit/sec data stream into a 19.44
or 77.76 Mbps 8-bit parallel data format.
Clock recovery is performed on the incoming
scrambled NRZ data stream. A 19.44, 38.88, 51.84
or 77.76 MHz reference clock is required for phase
locked loop start-up and proper operation under loss
of signal conditions. An integral prescaler and phase
locked loop circuit is used to multiply this reference
to the nominal bit rate.
Clock Recovery
Clock recovery, as shown in the block diagram in
Figure 4, generates a clock that is at the same fre-
quency as the incoming data bit rate at the RSD
input or, in loopback, the transmitter data output. The
clock is phase aligned by a PLL so that it samples
the data in the center of the data eye pattern.
The phase relationship between the edge transitions
of the data and those of the generated clock are
compared by a phase/frequency discriminator. Out-
put pulses from the discriminator indicate the
required direction of phase corrections. These
pulses are smoothed by an integral loop filter. The
output of the loop filter controls the frequency of the
Voltage Controlled Oscillator (VCO), which gener-
ates the recovered clock.
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