1
S3044
SONET/SDH/ATM OC-48 1:16 RECEIVER
November 22, 1999 / Revision F
BiCMOS LVPECL CLOCK GENERATOR
DEVICE
SPECIFICATION
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
S3044
FEATURES
Micro-power Bipolar technology
Complies with Bellcore and ITU-T
specifications
Supports 2.488 GHz (OC-48)
Interface to both LVPECL and TTL logic
16-bit LVPECL data path
Compact 80 PQFP/TEP package
Diagnostic loopback mode
Line loopback
Signal detect input
Low jitter LVPECL interface
Single 3.3V supply
APPLICATIONS
SONET/SDH-based transmission systems
SONET/SDH modules
SONET/SDH test equipment
ATM over SONET/SDH
Section repeaters
Add drop multiplexers (ADM)
Broad-band cross-connects
Fiber optic terminators
Fiber optic test equipment
Figure 1. System Block Diagram
SONET/SDH/ATM OC-48 1:16 RECEIVER
S3044
GENERAL DESCRIPTION
The S3044 SONET/SDH Demux chip is a fully inte-
grated deserialization SONET OC-48 (2.488 GHz) in-
terface device. The chip performs all necessary
serial-to-parallel and framing functions in conform-
ance with SONET/SDH transmission standards. The
device is suitable for SONET-based ATM applica-
tions. Figure 1 shows a typical network application.
The low jitter LVPECL interface guarantees compli-
ance with the bit-error rate requirements of the
Bellcore and ITU-T standards. The S3044 is pack-
aged in a 80 PQFP/TEP, offering designers a small
package outline.
Network Interface
Processor
Network Interface
Processor
S3043
Tx
S3044
Rx
S3044
Rx
S3043
Tx
OTX
ORX
OTX
ORX
16
16
16
16
S3040
S3040
S3044
SONET/SDH/ATM OC-48 1:16 RECEIVER
2
November 22, 1999 / Revision F
The sequence of operations of the S3044 is as follows:
Receiver Operations:
1. Serial input
2. Serial-to-parallel conversion
3. Frame detection
4. 16-bit parallel output
Internal clocking and control functions are transpar-
ent to the user. Details of data timing can be seen in
Figures 7 through 9. Internal clocking and control
functions are transparent to the user.
S3044 OVERVIEW
The S3044 receiver implements SONET/SDH
deserialization and frame detection functions. The
block diagram in Figure 2 shows the basic opera-
tion of the chip. This chip can be used to implement
the front end of SONET equipment, which consists
primarily of the serial transmit interface and the se-
rial receive interface. The chip includes
serial-to-parallel conversion and system timing. The
system timing circuitry consists of management of
the datastream, framing, and clock distribution
throughout the front end.
Figure 2. S3044 Functional Block Diagram
1:16 SERIAL
TO PARALLEL
TIMING
GEN
M
U
X
RSDP/N
FRAME
BYTE
DETECT
DLEB
OOF
FP
LLCLKP/N
OVREF
LLDP/N
POUT[15:0]
16
RSCLKP/N
LSCLKP/N
2
2
2
LSDP/N
8
2
SDPECL
M
U
X
POCLKP/N
2
1
2
2
D
D
D
LLEB
RSTB
SEARCH
FRAMEN
KILLRXCLK
RX155MCKP/N
2
Vbb
Suggested Interface Devices
AMCC S3040 Clock Recovery Device
AMCC S3043 OC-48 Transmitter
3
S3044
SONET/SDH/ATM OC-48 1:16 RECEIVER
November 22, 1999 / Revision F
SONET OVERVIEW
Synchronous Optical Network (SONET) is a standard
for connecting one fiber system to another at the opti-
cal level. SONET, together with the Synchronous
Digital Hierarchy (SDH) administered by the ITU-T,
forms a single international standard for fiber inter-
connect between telephone networks of different
countries. SONET is capable of accommodating a
variety of transmission rates and applications.
The SONET standard is a layered protocol with four
separate layers defined. These are:
Photonic
Section
Line
Path
Figure 3 shows the layers and their functions. Each of
the layers has overhead bandwidth dedicated to ad-
ministration and maintenance. The photonic layer
simply handles the conversion from electrical to opti-
cal and back with no overhead. It is responsible for
transmitting the electrical signals in optical form over
the physical media. The section layer handles the
transport of the framed electrical signals across the
optical cable from one end to the next. Key functions
of this layer are framing, scrambling, and error moni-
toring. The line layer is responsible for the reliable
transmission of the path layer information stream car-
rying voice, data, and video signals. Its main functions
are synchronization, multiplexing, and reliable trans-
port. The path layer is responsible for the actual trans-
port of services at the appropriate signaling rates.
Data Rates and Signal Hierarchy
Table 1 contains the data rates and signal designa-
tions of the SONET hierarchy. The lowest level is the
basic SONET signal referred to as the synchronous
transport signal level-1 (STS-1). An STS-
N signal is
made up of
N byte-interleaved STS-1 signals. The
optical counterpart of each STS-
N signal is an opti-
cal carrier level-
N signal (OC-N). The S3044 chip
supports OC-48 rate (2.488 Gbps).
Frame and Byte Boundary Detection
The SONET/SDH fundamental frame format for STS-48
consists of 144 transport overhead bytes followed by
Synchronous Payload Envelope (SPE) bytes. This
pattern of 144 overhead and 4176 SPE bytes is re-
peated nine times in each frame. Frame and byte
boundaries are detected using the A1 and A2 bytes
found in the transport overhead. (See Figure 4.)
For more details on SONET operations, refer to the
Bellcore SONET standard document.
Table 1. SONET Signal Hierarchy
Figure 3. SONET Structure
Figure 4. STS-48/OC-48 Frame Format
0 bps
End Equipment
Payload to
SPE mapping
Maintenance,
protection,
switching
Optical
transmission
Scrambling,
framing
Fiber Cable
End Equipment
Section layer
Photonic layer
Line layer
Path layer
Path layer
Section layer
Photonic layer
Line layer
Layer Overhead
(Embedded Ops
Channel)
Functions
576 Kbps
192 Kbps
9 Rows
48 A1
Bytes
48 A2
Bytes
A1 A1
A1 A1
A2 A2
A2 A2
Transport Overhead 144 Columns
144 x 9 = 1296 bytes
Synchronous Payload Envelope 4176 Columns
4176 x 9 = 37,584 bytes
125
sec
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2
S3044
SONET/SDH/ATM OC-48 1:16 RECEIVER
4
November 22, 1999 / Revision F
RECEIVER OPERATION
The S3044 receiver chip provides the first stage of
digital processing of a receive SONET STS-48 bit-
serial stream. It converts the bit-serial 2.488 Gbps
data stream into a 155.52 Mbyte/sec byte-serial data
format. A loopback mode is provided for diagnostic
loopback (transmitter to receiver). A Line Loopback
(receiver to transmitter) is also provided.
Frame and Byte Boundary Detection
The Frame and Byte Boundary Detection circuitry
searches the incoming data for three consecutive A1
bytes followed immediately by one A2 byte. Framing
pattern detection is enabled and disabled by the
FRAMEN input. Detection is enabled by a rising edge
on OOF when FRAMEN is active. It is disabled when
a framing pattern is detected. When framing pattern
detection is enabled, the framing pattern is used to
locate byte and frame boundaries in the incoming data
stream (RSD or looped transmitter data). During this
time, the parallel data bus (POUT [15:0]) will not
contain valid data. The timing generator block takes
the located byte boundary and uses it to block the
incoming data stream into bytes for output on the
parallel output data bus (POUT[15:0]). The frame
boundary is reported on the frame pulse (FP) output
when any 32-bit pattern matching the framing pat-
tern is detected on the incoming data stream. When
framing pattern detection is disabled, the byte bound-
ary is frozen to the location found when detection
was previously enabled. Only framing patterns
aligned to the fixed byte boundary are indicated on
the FP output.
The probability that random data in an STS-48
stream will generate the 32-bit framing pattern is ex-
tremely small. It is highly improbable that a mimic
pattern would occur within one frame of data. There-
fore, the time to match the first frame pattern and to
verify it with down-stream circuitry, at the next occur-
rence of the pattern, is expected to be less than the
required 250
s, even for extremely high bit error
rates.
Serial to Parallel Converter
The Serial to Parallel Converter consists of three
16-bit registers. The first is a serial-in, parallel-out
shift register, which performs the serial to parallel
conversion. The second is an 16-bit internal holding
register, which transfers data from the serial to par-
allel register on byte boundaries as determined by
the frame and byte boundary detection block. On the
falling edge of the free running POCLK, the data in
the holding register is transferred to an output hold-
ing register which drives POUT[15:0].
OTHER OPERATING MODES
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input
is active, a loopback from the transmitter to the re-
ceiver at the serial data rate can be set up for diag-
nostic purposes. The differential serial output clock
and data from the transmitter (LSCLK and LSD) is
routed to the serial-to-parallel block in place of the
normal data stream (RSCLK and RSD).
Line Loopback
The Line Loopback circuitry consists of alternate
clock and data output drivers. When LLEB is active,
it enables the Line Loopback output data and clock
(LLD and LLCLK), and a receive-to-transmit
loopback can be established at the serial data rate.
5
S3044
SONET/SDH/ATM OC-48 1:16 RECEIVER
November 22, 1999 / Revision F
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Table 2. Input Pin Assignment and Description
S3044
SONET/SDH/ATM OC-48 1:16 RECEIVER
6
November 22, 1999 / Revision F
Table 3. Output Pin Assignment and Description
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7
S3044
SONET/SDH/ATM OC-48 1:16 RECEIVER
November 22, 1999 / Revision F
Table 4. Common Pin Assignment and Description
e
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N
G
L
T
T
V
L
D
N
G
1
2
d
n
u
o
r
G
L
T
T
D
H
T
0
2
e
d
o
i
D
l
a
m
r
e
h
T
C
N
,
8
5
,
7
5
,
0
6
,
9
5
0
7
,
5
6
d
e
t
c
e
n
n
o
C
t
o
N
S3044
SONET/SDH/ATM OC-48 1:16 RECEIVER
8
November 22, 1999 / Revision F
1
2
3
4
5
6
7
8
9
10
11
21
22
23
24
25
26
27
28
29
62
61
48
47
46
45
44
43
42
41
S3044
80 PQFP/TEP
COREVCC
COREGND
LVPECLVCC
LVPECLGND
POCLKN
POCLKP
POUTP15
POUTP14
POUTP13
POUTP12
POUTP11
POUTP10
POUTP9
POUTP8
LVPECLVCC
DLEB
RSTB
SEARCH
LVPECLVCC
LVPECLGND
RX155MCKP
RX155MCKN
FP
OVREF
POUTP0
POUTP1
LVTTLGND
LLEB
30
31
32
POUTP2
POUTP3
POUTP4
64
63
LVPECL
GND
LSDN
LSDP
LVPECL
VCC
LVPECL
GND
NC
LLCLKP
LLCLKN
LVPECL
VCC
LVPECLGND
NC
LVPECL
VCC
LVPECL
VCC
LVPECLGND
LLDP
12
13
LVPECLGND
RSDP
RSDN
LVPECLVCC
LVPECLGND
RSCLKP
RSCLKN
COREVCC
COREGND
COREVCC
COREGND
COREVCC
14
15
16
COREGND
TOP VIEW
LVTTLVCC
LLDN
LVPECLGND
LVPECLVCC
KILLRXCLK
OOF
FRAMEN
THD
SDPECL
LVPECL
VCC
LVPECL
GND
LSCLKP
LSCLKN
NC
NC
NC
NC
POUTP5
POUTP6
POUTP7
LVPECLGND
17
18
19
20
33
34
35
36
37
38
39
40
60
59
58
57
56
55
54
53
52
51
50
49
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
Figure 5. S3044 Pinout
9
S3044
SONET/SDH/ATM OC-48 1:16 RECEIVER
November 22, 1999 / Revision F
Figure 6. 80 PQFP/TEP Package
Device
S3044
1.25 W
2.1C/W
Max Package Power
jc
26C/W
ja
Table 5. Thermal Management
Note: The S3044 package is equipped with an embedded conductive heatsink on the bottom (board side). Active circuitry
and vias should not appear in the area immediately under the package. This heatsink is electrically biased to the Vee
potential of the S3044. For optimum thermal management, a foil surface at ground (or Vee if other than ground) is
recommended immediately under the package, and connected with multiple vias to the internal plane(s) of similar potential.
Thermally conductive epoxy or other conductive interposer can be used to establish a good thermal dissipation path.
TOP VIEW
BOTTOM VIEW
S3044
SONET/SDH/ATM OC-48 1:16 RECEIVER
10
November 22, 1999 / Revision F
s
r
e
t
e
m
a
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a
P
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p
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a
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c
c
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5
.
0
-
c
c
V
5
2
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0
-
V
0
0
1
.
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c
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5
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V
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1
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il
-
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V
F
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g
a
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l
a
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r
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f
f
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0
6
3
0
0
8
V
m
0
0
1
.
e
n
il
-
o
t
-
e
n
il
V
E
L
G
N
I
S
T
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t
u
p
t
u
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l
a
i
r
e
S
L
M
C
g
n
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w
S
w
o
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g
n
i
w
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e
g
a
t
l
o
V
d
e
d
n
e
-
e
l
g
n
i
S
0
8
1
0
0
4
V
m
0
0
1
.
e
n
il
-
o
t
-
e
n
il
Table 6. Low Swing Differential CML Output DC Characteristics
s
r
e
t
e
m
a
r
a
P
n
o
i
t
p
i
r
c
s
e
D
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p
y
T
x
a
M
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t
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n
U
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n
o
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t
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d
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o
C
V
F
F
I
D
N
I
g
n
i
w
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e
g
a
t
l
o
V
t
u
p
n
I
l
a
i
t
n
e
r
e
f
f
i
D
0
0
3
0
0
2
1
V
m
.
3
1
e
r
u
g
i
F
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e
S
V
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L
G
N
I
S
N
I
g
n
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w
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d
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d
n
E
-
e
l
g
n
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S
t
u
p
n
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l
a
i
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n
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r
e
f
f
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D
0
5
1
0
0
6
V
m
.
3
1
e
r
u
g
i
F
e
e
S
R
F
F
I
D
e
c
n
a
t
s
i
s
e
R
t
u
p
n
I
l
a
i
t
n
e
r
e
f
f
i
D
0
8
0
0
1
0
2
1
Table 7. Internally Biased Differential LVPECL Input DC Characteristics
Table 9. Single Ended LVPECL Input DC Characteristics
s
r
e
t
e
m
a
r
a
P
n
o
i
t
p
i
r
c
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x
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C
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g
a
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E
P
V
L
c
c
V
0
3
.
2
-
c
c
V
1
4
4
.
1
-
V
V
H
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g
a
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c
c
V
0
5
2
.
1
-
c
c
V
0
7
5
.
0
-
V
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g
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B
C
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P
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c
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2
.
1
-
c
c
V
8
.
0
-
V
.
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p
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g
a
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P
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L
c
c
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0
0
0
.
2
-
c
c
V
5
2
.
0
-
V
V
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g
a
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c
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2
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-
c
c
V
5
0
.
0
-
V
V
F
F
I
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N
I
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n
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g
a
t
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V
t
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f
f
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0
0
3
0
0
2
1
V
m
.
3
1
e
r
u
g
i
F
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S
V
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L
G
N
I
S
N
I
g
n
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w
S
d
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d
n
E
-
e
l
g
n
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S
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n
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l
a
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r
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f
f
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D
0
5
1
0
0
6
V
m
.
3
1
e
r
u
g
i
F
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e
S
R
F
F
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c
n
a
t
s
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e
R
t
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l
a
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t
n
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r
e
f
f
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D
0
8
0
0
1
0
2
1
Table 8. Externally Biased Differential LVPECL Input DC Characteristics
11
S3044
SONET/SDH/ATM OC-48 1:16 RECEIVER
November 22, 1999 / Revision F
s
r
e
t
e
m
a
r
a
P
n
o
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p
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c
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2
.
2
-
c
c
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0
5
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1
-
V
0
2
2
d
n
a
c
c
V
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2
8
,
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o
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0
3
1
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N
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c
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0
2
.
1
-
c
c
V
5
6
.
0
-
V
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2
2
d
n
a
c
c
V
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2
8
,
D
N
G
o
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0
3
1
D
N
G
o
t
F
E
R
V
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s
a
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a
t
l
o
V
c
c
V
0
8
.
1
-
c
c
V
0
2
.
1
-
V
r
e
v
o
s
t
i
m
il
e
t
u
l
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s
b
A
n
e
v
i
g
a
t
A
.
e
r
u
t
a
r
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p
m
e
t
s
k
c
a
r
t
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E
R
V
O
e
r
u
t
a
r
e
p
m
e
t
V
H
O
V
d
n
a
L
O
:
Table 10. Single Ended LVPECL Output DC Characteristics
Table 11. Low Speed Differential LVPECL Input DC Characteristics
Table 12. Low Speed Differential LVPECL Output DC Characteristics
s
r
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t
e
m
a
r
a
P
n
o
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t
p
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c
c
V
0
.
2
-
c
c
V
5
.
0
-
V
V
H
I
h
g
i
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E
P
V
L
c
c
V
2
.
1
-
c
c
V
3
.
0
-
V
V
F
F
I
D
N
I
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n
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a
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t
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I
.
f
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0
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V
m
.
3
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m
.
3
1
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d
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l
g
n
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S
0
5
5
0
5
9
V
m
0
2
2
d
n
a
D
N
G
o
t
0
0
1
e
n
il
-
o
t
-
e
n
il
V
F
F
I
D
T
U
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w
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g
a
t
l
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V
t
u
p
t
u
O
.
f
f
i
D
0
0
1
1
0
0
9
1
V
m
0
2
2
d
n
a
D
N
G
o
t
0
0
1
e
n
il
-
o
t
-
e
n
il
V
H
O
e
g
a
t
l
o
V
h
g
i
H
t
u
p
t
u
O
c
c
V
5
1
.
1
-
c
c
V
0
6
.
0
-
V
0
2
2
d
n
a
D
N
G
o
t
0
0
1
e
n
il
-
o
t
-
e
n
il
V
L
O
e
g
a
t
l
o
V
w
o
L
t
u
p
t
u
O
c
c
V
5
9
.
1
-
c
c
V
0
5
.
1
-
V
0
2
2
d
n
a
D
N
G
o
t
0
0
1
e
n
il
-
o
t
-
e
n
il
OVREF =
V
OH
+ V
OL
2
120mV
S3044
SONET/SDH/ATM OC-48 1:16 RECEIVER
12
November 22, 1999 / Revision F
l
o
b
m
y
S
n
o
i
t
p
i
r
c
s
e
D
n
i
M
p
y
T
x
a
M
t
i
n
U
s
n
o
i
t
i
d
n
o
C
V
H
I
e
g
a
t
l
o
V
h
g
i
H
t
u
p
n
I
0
.
2
V
L
T
T
C
C
V
V
L
T
T
C
C
x
a
M
=
V
L
I
e
g
a
t
l
o
V
w
o
L
t
u
p
n
I
0
.
0
8
.
0
V
V
L
T
T
C
C
x
a
M
=
I
H
I
t
n
e
r
r
u
C
h
g
i
H
t
u
p
n
I
0
5
A
V
N
I
V
4
.
2
=
I
L
I
t
n
e
r
r
u
C
w
o
L
t
u
p
n
I
0
0
5
-
A
V
N
I
V
5
.
0
=
V
H
O
e
g
a
t
l
o
V
h
g
i
H
t
u
p
t
u
O
2
.
2
V
V
H
I
n
i
M
=
V
L
I
x
a
M
=
I
H
O
A
0
0
1
-
=
V
L
O
e
g
a
t
l
o
V
w
o
L
t
u
p
t
u
O
5
.
0
V
V
H
I
n
i
M
=
V
L
I
x
a
M
=
I
oL
A
m
4
=
Table 13. LVTTL Input/Output DC Characteristics
13
S3044
SONET/SDH/ATM OC-48 1:16 RECEIVER
November 22, 1999 / Revision F
r
e
t
e
m
a
r
a
P
n
i
M
p
y
T
x
a
M
s
t
i
n
U
e
r
u
t
a
r
e
p
m
e
T
e
g
a
r
o
t
S
5
6
-
0
5
1
C
D
N
G
o
t
t
c
e
p
s
e
R
h
t
i
w
c
c
V
n
o
e
g
a
t
l
o
V
5
.
0
-
0
.
5
+
V
n
i
P
t
u
p
n
I
L
C
E
P
V
L
y
n
a
n
o
e
g
a
t
l
o
V
0
c
c
V
V
n
i
P
t
u
p
n
I
L
T
T
V
L
y
n
a
n
o
e
g
a
t
l
o
V
5
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0
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5
.
5
+
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8
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4
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2
-
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5
.
5
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Table 14. Absolute Maximum Ratings
Table 15. Recommended Operating Conditions
1. Add 70mA for loopback active.
Table 16. Power Consumption
r
e
t
e
m
a
r
a
P
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p
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3
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p
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O
ESD Ratings
The S3044 is rated to the following ESD voltages based on the human body
model:
1. All pins are rated at or above 2000 V except pin 61, pin 62, pin 68, and pin 69.
S3044
SONET/SDH/ATM OC-48 1:16 RECEIVER
14
November 22, 1999 / Revision F
Table 17. AC Receiver Timing Characteristics
Figure 7. Output Timing Diagram
Figure 8. Receiver Input Timing Diagram
Notes on High-Speed LVPECL Input Timing:
1.
Timing is measured from the cross-over point of the reference signal to the cross-over point of the input.
l
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Figure 9. LLD Output Timing
tS POUT
tP POUT
tH POUT
POCLKP
POUT[15:0], FP
tSRSD
tHRSD
RSDP/N
RSCLKP
tPLLD
LLD
LLCLKP
1. 20% to 80%; 330
to GND.
2. 20% to 80%; 100
line-to line.
15
S3044
SONET/SDH/ATM OC-48 1:16 RECEIVER
November 22, 1999 / Revision F
RECEIVER FRAMING
Figure 10 shows a typical reframe sequence in
which a byte realignment is made. The frame and
byte boundary detection is enabled by the rising
edge of OOF. Both boundaries are recognized upon
receipt of the first A2 byte. The third A2 byte is the
first data byte to be reported with the correct byte
alignment on the outgoing data bus (POUT[15:0]).
Concurrently, the frame pulse is set high for one
POCLK cycle.
The frame and byte boundary detection block is acti-
vated by the rising edge of OOF, and stays active until
the first FP pulse.
Figure 11 shows the frame and byte boundary detection
activation by a rising edge of OOF, and deactivated by
the first FP pulse.
Figure 12 shows the frame and byte boundary detec-
tion activation by a rising edge of OOF, and deacti-
vated by the FRAMEN input.
Figure 10. Frame and Byte Detection
1. Range of input to output delay can be 1.5 to 2.5 POCLK cycles.
A1
A1
A1
A2
A2
A2
A2
A2
Note 1
A1, A1
A1, A1
A1, A1
A2, A2
A2, A2
Invalid Data
Valid Data
RECOVERED
CLOCK/
REFCLK
OOF
SERDATI
POUT[15:0]
POCLK
FP
S3044
SONET/SDH/ATM OC-48 1:16 RECEIVER
16
November 22, 1999 / Revision F
Figure 11. OOF Timing (FRAMEN = 1)
Figure 12. FRAMEN Timing
Figure 13. Differential Voltage Measurement
BOUNDARY DETECTION ENABLED
OOF
FP
SEARCH
BOUNDARY DETECTION ENABLED
OOF
FP
SEARCH
FRAMEN
V SINGLE
Single-ended
swing
V DIFF
2X Single-ended
swing
=
17
S3044
SONET/SDH/ATM OC-48 1:16 RECEIVER
November 22, 1999 / Revision F
Vcc -0.70V
(DC AVG)
Vcc -0.70V
(DC AVG)
S3042/44
RSDP/N
RSCLKP/N
+5V
330
330
100
.01
F
.01
F
+3.3V
Z
0
=50
Z
0
=50
+5V
S3040
SERDATOP/N
SERCLKOP/N
+3.3V
S3042/44
RSDP/N
RSCLKP/N
.01
F
Vcc -0.70V
(DC AVG)
.01
F
100
Vcc -0.70V
(DC AVG)
Z
0
=50
Z
0
=50
Figure 14. +5V Differential PECL Driver to S3044 Input AC Coupled Termination
Figure 15. S3040 to S3042/S3044 Terminations
+3.3V
S3043
LLCLKP/N
LLDP/N
+3.3V
100
S3044
LLCLKP/N
LLDP/N
Z
0
=50
Z
0
=50
Figure 16. S3044 to S3043 Terminations
S3044
SONET/SDH/ATM OC-48 1:16 RECEIVER
18
November 22, 1999 / Revision F
+3.3V
220
130
82
S3044
POUTP
+3.3V
Vcc
LVPECL
Z
0
=50
Figure 17. Single-Ended PECL Output Termination
Figure 18. Alternative Single-Ended PECL Output Termination
Figure 19. Single-Ended PECL Output Termination
+3.3V
220
Z
0
=50
50
0.1
F
S3044
POUTP
+3.3V
LVPECL
+3.3V
5600
510
S3044
OVREF
+3.3V
LVPECL
Z
0
=50
19
S3044
SONET/SDH/ATM OC-48 1:16 RECEIVER
November 22, 1999 / Revision F
+3.3V
S3044
LSDP/N
LSCLKP/N
+3.3V
100
S3043
LSDP/N
LSCLKP/N
Z
0
=50
Z
0
=50
Figure 20. S3043 to S3044 for Diagnostic Loopback
Figure 21. Single-Ended LVPECL Driver to S3044 Input
AC Coupled Termination
Vcc -0.70V
(DC AVG)
Vcc -0.70V
(DC AVG)
S3044
RSDP/N
RSCLKP/N
Vcc
300
.01
F
.01
F
+3.3V
60
Single-Ended
Driver
Z
0
=50
Figure 22. Differential LVPECL Termination
+3.3V
LVPECL
Differential Input
+3.3V
100
220
220
POCLKP/N
Z
0
=50
Z
0
=50
S3044
SONET/SDH/ATM OC-48 1:16 RECEIVER
20
November 22, 1999 / Revision F
X XXXX X
Prefix Device Package
S3044
SONET/SDH/ATM OC-48 1:16 RECEIVER
C
E
R T I F I E
D
IS
O 9001
AMCC is a registered trademark of Applied Micro Circuits Corporation.
Copyright 1999 Applied Micro Circuits Corporation
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.
AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey
any license under its patent rights nor the rights of others.
AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE
FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Applied Micro Circuits Corporation
6290 Sequence Drive, San Diego, CA 92121
Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885
http://www.amcc.com
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Ordering Information
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