Publication# 23579

Rev: C Amendment/+6

Issue Date: November 15, 2004

Am29LV320D

32 Megabit (4 M x 8-Bit/2 M x 16-Bit)
CMOS 3.0 Volt-only, Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

Secured Silicon (SecSi

Sector)

-- 64 Kbyte Sector Size; Replacement/substitute

devices (such as Mirrorbit

) have 256 bytes.

-- Factory locked and identifiable: 16 bytes (8

words) available for secure, random factory
Electronic Serial Number; verifiable as factory
locked through autoselect function.
ExpressFlash option allows entire sector to be
available for factory-secured data

-- Customer lockable: Can be programmed once

and then permanently locked after being
shipped from AMD

Zero Power Operation
-- Sophisticated power management circuits

reduce power consumed during inactive
periods to nearly zero.

Package options
-- 48-pin TSOP
-- 48-ball FBGA

Sector Architecture
-- Eight 8 Kbyte sectors
-- Sixty-three 64 Kbyte sectors

Top or bottom boot block

Manufactured on 0.23 µm process
technology

Compatible with JEDEC standards
-- Pinout and software compatible with

single-power-supply flash standard

PERFORMANCE CHARACTERISTICS

High performance
-- Access time as fast 90 ns
-- Program time: 7µs/word typical utilizing

Accelerate function

Ultra low power consumption (typical
values)
-- 2 mA active read current at 1 MHz
-- 10 mA active read current at 5 MHz
-- 200 nA in standby or automatic sleep mode

Minimum 1 million erase cycles guaranteed
per sector

20 Year data retention at 125°C
-- Reliable operation for the life of the system

SOFTWARE FEATURES

Supports Common Flash Memory Interface
(CFI)

Erase Suspend/Erase Resume
-- Suspends erase operations to allow

programming in non-suspended sectors

Data# Polling and Toggle Bits
-- Provides a software method of detecting the

status of program or erase cycles

Unlock Bypass Program command
-- Reduces overall programming time when

issuing multiple program command sequences

HARDWARE FEATURES

Any combination of sectors can be erased

Ready/Busy# output (RY/BY#)
-- Hardware method for detecting program or

erase cycle completion

Hardware reset pin (RESET#)
-- Hardware method of resetting the internal

state machine to the read mode

WP#/ACC input pin
-- Write protect (WP#) function allows protection

of two outermost boot sectors, regardless of
sector protect status

-- Acceleration (ACC) function provides

accelerated program times

Sector protection
-- Hardware method of locking a sector, either

in-system or using programming equipment,
to prevent any program or erase operation
within that sector

-- Temporary Sector Unprotect allows changing

data in protected sectors in-system

Am29LV320D

November 15, 2004

GENERAL DESCRIPTION

T he A m 2 9 LV 3 2 0 D i s a 3 2 m e g a b i t, 3 . 0

volt-only flash memory device, organized as

2,097,152 words of 16 bits each or 4,194,304

bytes of 8 bits each. Word mode data appears

on DQ0DQ15; byte mode data appears on

DQ0DQ7. The device is designed to be pro-

grammed in-system with the standard 3.0 volt

supply, and can also be programmed in

standard EPROM programmers.
The device is available with an access time of

90 or 120 ns. The devices are offered in 48-pin

TSOP and 48-ball FBGA packages. Standard

control pins--chip enable (CE#), write enable

(WE#), and output enable (OE#)--control nor-

mal read and write operations, and avoid bus

contention issues.

The device requires only a single 3.0 volt

power supply for both read and write func-

tions. Internally generated and regulated volt-

ages are provided for the program and erase

operations.

Am29LV320D Features

The SecSi

Sector (Secured Silicon) is an

extra sector capable of being permanently

locked by AMD or customers. The SecSi Indi-

cator Bit (DQ7) is permanently set to a 1 if the

part is factory locked, and set to a 0 if cus-

tomer lockable. This way, customer lockable

parts can never be used to replace a factory

locked part. Note that the Am29LV320D has

a SecSi Sector size of 64 Kbytes. AMD de-

vices designated as replacements or sub-

stitutes, such as the Am29LV320M, have

256 bytes. This should be considered dur-

ing system design.
Factory locked parts provide several options.

The SecSi Sector may store a secure, random

16 byte ESN (Electronic Serial Number), cus-

tomer code (programmed through AMD's Ex-

p r e ssF l a sh s e rv ic e), or bo th . C us to m er

Lockable parts may utilize the SecSi Sector as

bonus space, reading and writing like any other

flash sector, or may permanently lock their own

code there.
The device offers complete compatibility with

the JEDEC single-power-supply Flash com-

mand set standard. Commands are written to

the command register using standard micro-

processor write timings. Reading data out of

the device is similar to reading from other Flash

or EPROM devices.

The host system can detect whether a program

or erase operation is complete by using the de-

vice status bits: RY/BY# pin, DQ7 (Data# Poll-

ing) and DQ6/DQ2 (toggle bits). After a

program or erase cycle is completed, the device

automatically returns to the read mode.
The sector erase architecture allows mem-

ory sectors to be erased and reprogrammed

without affecting the data contents of other

sectors. The device is fully erased when

shipped from the factory.

Hardware data protection measures include

a low V

detector that automatically inhibits

write operations during power transitions. The

hardware sector protection feature disables

both program and erase operations in any com-

bination of the sectors of memory. This can be

achieved in-system or via programming equip-

ment.
The device offers two power-saving features.

When addresses are stable for a specified

amount of time, the device enters the auto-

matic sleep mode. The system can also place

the device into the standby mode. Power con-

sumption is greatly reduced in both modes.

November 15, 2004

Am29LV320D

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7

Special Package Handling Instructions .................................... 8

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 11

Table 1. Am29LV320D Device Bus Operations ..............................11

Word/Byte Configuration ........................................................ 11
Requirements for Reading Array Data ................................... 11
Writing Commands/Command Sequences ............................ 12

Accelerated Program Operation .......................................... 12
Autoselect Functions ........................................................... 12

Standby Mode ........................................................................ 12
Automatic Sleep Mode ........................................................... 13
RESET#: Hardware Reset Pin ............................................... 13
Output Disable Mode .............................................................. 13

Table 2. Top Boot Sector Addresses (Am29LV320DT) ..................13
Table 3. Top Boot SecSi

Sector Addresses................................ 14

Table 4. Bottom Boot Sector Addresses (Am29LV320DB) .............15
Table 5. Bottom Boot SecSi

Sector Addresses .......................... 16

Autoselect Mode ..................................................................... 16

Table 6. Autoselect Codes (High Voltage Method) ........................16

Sector/Sector Block Protection and Unprotection .................. 17

Table 7. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection .............................................................17
Table 8. Bottom Boot Sector/Sector Block
Addresses for Protection/Unprotection ...........................................17

Write Protect (WP#) ................................................................ 18
Temporary Sector Unprotect .................................................. 18

Figure 1. Temporary Sector Unprotect Operation........................... 18
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 19

SecSi

Sector (Secured Silicon) Flash Memory Region ....... 20

Factory Locked: SecSi Sector Programmed
and Protected at the Factory ............................................... 20
Customer Lockable: SecSi Sector NOT Programmed
or Protected at the Factory .................................................. 20

Figure 3. SecSi Sector Protect Verify.............................................. 21

Hardware Data Protection ...................................................... 21

Low VCC Write Inhibit ......................................................... 21
Write Pulse "Glitch" Protection ............................................ 21
Logical Inhibit ...................................................................... 21
Power-Up Write Inhibit ......................................................... 21

Common Flash Memory Interface (CFI) . . . . . . . 21

Table 9. CFI Query Identification String .......................................... 22
Table 10. System Interface String................................................... 22
Table 11. Device Geometry Definition ............................................ 23
Table 12. Primary Vendor-Specific Extended Query ...................... 24

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 25

Reading Array Data ................................................................ 25
Reset Command ..................................................................... 25
Autoselect Command Sequence ............................................ 25

Table 13. Autoselect Codes ............................................................25

Enter SecSi

Sector/Exit SecSi Sector

Command Sequence .............................................................. 26
Byte/Word Program Command Sequence ............................. 26

Unlock Bypass Command Sequence .................................. 26

Figure 4. Program Operation ......................................................... 27

Chip Erase Command Sequence ........................................... 27
Sector Erase Command Sequence ........................................ 27
Erase Suspend/Erase Resume Commands ........................... 28

Figure 5. Erase Operation.............................................................. 28

Command Definitions ............................................................. 29

Table 14. Am29LV320D Command Definitions ............................. 29

Write Operation Status . . . . . . . . . . . . . . . . . . . . 30

DQ7: Data# Polling ................................................................. 30

Figure 6. Data# Polling Algorithm .................................................. 30

RY/BY#: Ready/Busy# ............................................................ 31
DQ6: Toggle Bit I .................................................................... 31

Figure 7. Toggle Bit Algorithm........................................................ 31

DQ2: Toggle Bit II ................................................................... 32
Reading Toggle Bits DQ6/DQ2 ............................................... 32
DQ5: Exceeded Timing Limits ................................................ 32
DQ3: Sector Erase Timer ....................................................... 32

Table 15. Write Operation Status ................................................... 33

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 34

Figure 8. Maximum Negative Overshoot Waveform ...................... 34
Figure 9. Maximum Positive Overshoot Waveform........................ 34

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 34
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 10. I

CC1

Current vs. Time (Showing Active and

Automatic Sleep Currents) ............................................................. 36
Figure 11. Typical I

CC1

vs. Frequency ............................................ 36

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 12. Test Setup.................................................................... 37
Table 16. Test Specifications ......................................................... 37
Figure 13. Input Waveforms and Measurement Levels ................. 37

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 14. Read Operation Timings ............................................... 38
Figure 15. Reset Timings ............................................................... 39

Word/Byte Configuration (BYTE#) ............................................. 40

Figure 16. BYTE# Timings for Read Operations............................ 40
Figure 17. BYTE# Timings for Write Operations............................ 40

Erase and Program Operations ................................................. 41

Figure 18. Program Operation Timings.......................................... 42
Figure 19. Chip/Sector Erase Operation Timings .......................... 43
Figure 20. Data# Polling Timings (During Embedded Algorithms). 44
Figure 21. Toggle Bit Timings (During Embedded Algorithms)...... 45
Figure 22. DQ2 vs. DQ6................................................................. 45

Temporary Sector Unprotect ..................................................... 46

Figure 23. Temporary Sector Unprotect Timing Diagram .............. 46
Figure 24. Accelerated Program Timing Diagram .......................... 46
Figure 25. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 47

Alternate CE# Controlled Erase and Program Operations ........ 48

Figure 26. Alternate CE# Controlled Write
(Erase/Program) Operation Timings .............................................. 49

Erase And Programming Performance . . . . . . . 50
Latchup Characteristics . . . . . . . . . . . . . . . . . . . 50
TSOP and BGA Package Capacitance . . . . . . . . 50
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 51
FBD048--48-ball Fine-Pitch Ball Grid Array (FBGA)
6 x 12 mm package ................................................................... 51
TS 048--48-Pin Standard TSOP ............................................... 52
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 53

Am29LV320D

November 15, 2004

ORDERING INFORMATION
Standard Products

AMD standard products are available in several packages and operating ranges. The order number

(Valid Combination) is formed by a combination of the following:

Valid Combinations

Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local
AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.

Am29LV32

TEMPERATURE RANGE
I =

Industrial

(40

C to +85

F =

Industrial

(40

C to +85

C) with Pb-free package

C = Commercial

C to +70

D = Commercial

C to +70

C) with Pb-free package

= Automotive In-Cabin (-40

C to +105

= Automotive In-Cabin (-40

C to +105

°C

) with Pb-free package

PACKAGE TYPE
E

= 48-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 048)

= 48-ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 12 mm package (FBD048)

SPEED OPTION
See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE
T

= Top boot sector

= Bottom boot sector

DEVICE NUMBER/DESCRIPTION
Am29LV320D
32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS Boot Sector Flash Memory
3.0 Volt-only Read, Program and Erase

Valid Combinations for

TSOP Packages

Speed

(Ns)

Range

AM29LV320DT90R,
AM29LV320DB90R

EC, EI,

ED, EF

3.0 3.6V

Am29LV320DT90,
Am29LV320DB90

2.7 3.6V

AM29LV320DT120,
AM29LV320DB120

120

2.7 3.6V

Am29LV320DT120
Am29LV320DB120

EV, EY

120

2.7 3,6V

Valid Combinations for FBGA Packages

Order Number

Package Marking

AM29LV320DT90,
AM29LV320DB90

WMC,W

MI,

WMD,

WMF

L320DT90V,
L320DB90V

C, I,

D, F

AM29LV320DT120,
AM29LV320DB120

L320DT12V,
L320DB12V

Am29LV320DT120
Am29LV320DB120

WNV

L320DT12V
L320DB12V

V, Y

November 15, 2004

Am29LV320D

DEVICE BUS OPERATIONS

This section describes the requirements and

use of the device bus operations, which are ini-

tiated through the internal command register.

The command register itself does not occupy

any addressable memory location. The register

is a latch used to store the commands, along

with the address and data information needed

to execute the command. The contents of the

machine. The state machine outputs dictate the

function of the device.

Table 1

lists the device

bus operations, the inputs and control levels

they require, and the resulting output. The fol-

lowing subsections describe each of these oper-

ations in further detail.

Table 1. Am29LV320D Device Bus Operations

Legend: L = Logic Low = V

, H = Logic High = V

, V

= 11.512.5 V, V

= 11.512.5 V, X = Don't Care, SA

= Sector Address, A

= Address In, D

= Data In, D

OUT

= Data Out

Notes:
1. Addresses are A20:A0 in word mode (BYTE# = V

), A20:A-1 in byte mode (BYTE# = V

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See

"Sector/Sector Block Protection and Unprotection" on page 17

3. If WP#/ACC = V

, the two outermost boot sectors remain protected. If WP#/ACC = V

, the two outermost boot

sector protection depends on whether they were last protected or unprotected using the method described in

"Sector/Sector Block Protection and Unprotection" on page 17

. If WP#/ACC = V

, all sectors are unprotected.

4. D

or D

OUT

as required by command sequence, data polling, or sector protection algorithm.

Word/Byte Configuration

The BYTE# pin controls whether the device

data I/O pins operate in the byte or word con-

figuration. If the BYTE# pin is set at logic `1',

the device is in word configuration, DQ0DQ15

are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic `0', the device is

in byte configuration, and only data I/O pins

DQ0DQ7 are active and controlled by CE# and
O E # . T he d a ta I/ O p i n s D Q 8 D Q 1 4 a r e

tri-stated, and the DQ15 pin is used as an input

for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the sys-

tem must drive the CE# and OE# pins to V

CE# is the power control and selects the de-

vice. OE# is the output control and gates array

data to the output pins. WE# should remain at

. The BYTE# pin determines whether the de-

vice outputs array data in words or bytes.

Operation

CE# OE#

RESET

WP#/AC

Addresses

(Note 2)

DQ0

DQ7

DQ8DQ15

BYTE

= V

BYTE#

= V

Read

L/H

OUT

DQ8DQ14

= High-Z,

DQ15 = A-1

Write

(Note 3)

(Note 4) (Note 4)

Accelerated Program

(Note 4) (Note 4)

Standby

0.3 V

High-Z

Output Disable

L/H

High-Z

Reset

L/H

High-Z

Sector Protect (Note 2)

L/H

SA, A6 = L,

A1 = H, A0 = L

(Note 4)

Sector Unprotect
(Note 2)

(Note 3)

SA, A6 = H,

A1 = H, A0 = L

(Note 4)

Temporary Sector
Unprotect

(Note 3)

(Note 4) (Note 4)

High-Z

Am29LV320D

November 15, 2004

The internal state machine is set for reading

array data upon device power-up, or after a

hardware reset. This ensures that no spurious

alteration of the memory content occurs during

the power transition. No command is necessary

in this mode to obtain array data. Standard mi-

croprocessor read cycles that assert valid ad-

dresses on the device address inputs produce

valid data on the device data outputs. The de-

vice remains enabled for read access until the

command register contents are altered.

See

"Requirements for Reading Array Data" on

page 11

for more information. Refer to the AC

Read-Only Operations table for timing specifi-

cations and to

Figure 14, on page 38

for the

timing diagram. I

CC1

in the DC Characteristics

table represents the active current specification

for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence

(which includes programming data to the de-

vice and erasing sectors of memory), the sys-

tem must drive WE# and CE# to V

, and OE#

to V

For program operations, the BYTE# pin deter-

mines whether the device accepts program

data in bytes or words. Refer to

"Word/Byte

Configuration" on page 11

for more informa-

tion.
The device features an Unlock Bypass mode

to facilitate faster programming. Once the de-

vice enters the Unlock Bypass mode, only two

write cycles are required to program a word or

byte, instead of four. The

"Word/Byte Configu-

ration" on page 11

section contains details on

programming data to the device using both

standard and Unlock Bypass command se-

quences.

An erase operation can erase one sector, multi-

ple sectors, or the entire device.

Table 2, on

page 13

through

Table 5, on page 16

indicate

the address space that each sector occupies. A

"sector address" is the address bits required to

uniquely select a sector.
I

CC2

in the DC Characteristics table represents

the active current specification for the write

mode. The

"AC Characteristics" on page 38

sec-

tion contains timing specification tables and

timing diagrams for write operations.

Accelerated Program Operation
The device offers accelerated program opera-

tions through the ACC function. This is one of

two functions provided by the WP#/ACC pin.

This function is primarily intended to allow

faster manufacturing throughput at the factory.

If the system asserts V

on this pin, the device

automatically enters the aforementioned Un-

lock Bypass mode, temporarily unprotects any

protected sectors, and uses the higher voltage

on the pin to reduce the time required for pro-

gram operations. The system would use a

two-cycle program command sequence as re-

quired by the Unlock Bypass mode. Removing

from the WP#/ACC pin returns the device

to normal operation. Note that the WP#/ACC

pin must not be at V

for operations other

than accelerated programming, or device dam-

age may result. In addition, the WP#/ACC pin

must not be left floating or unconnected; incon-

sistent behavior of the device may result.

Autoselect Functions
If the system writes the autoselect command

sequence, the device enters the autoselect

mode. The system can then read autoselect

codes from the internal register (which is sepa-

rate from the memory array) on DQ7DQ0.

Standard read cycle timings apply in this mode.

Refer to the

"Autoselect Mode" on page 16

and

"Autoselect Command Sequence" on page 25

sections for more information.
I

CC6

and I

CC7

in the DC Characteristics table

r epresent the curr ent sp ecifications for

read-while-program and read-while-erase, re-

spectively.

Standby Mode

When the system is not reading or writing to

the device, it can place the device in the

standby mode. In this mode, current consump-

tion is greatly reduced, and the outputs are

placed in the high impedance state, indepen-

dent of the OE# input.
The device enters the CMOS standby mode

when the CE# and RESET# pins are both held

at V

± 0.3 V. (Note that this is a more re-

stricted voltage range than V

.) If CE# and RE-

SET# are held at V

, but not within V

± 0.3

V, the device is in the standby mode, but the

standby current is greater. The device requires

standard access time (t

) for read access when

the device is in either of these standby modes,

before it is ready to read data.

If the device is deselected during erasure or

programming, the device draws active current

until the operation is completed.
I

CC3

in the DC Characteristics table represents

the standby current specification.

November 15, 2004

Am29LV320D

Automatic Sleep Mode

The automatic sleep mode minimizes Flash de-

vice energy consumption. The device automati-

cally enables this mode when addresses remain

stable for t

ACC

+ 30 ns. The automatic sleep

mode is independent of the CE#, WE#, and

OE# control signals. Standard address access

timings provide new data when addresses are

changed. While in sleep mode, output data is

latched and always available to the system. I

CC4

in the

"DC Characteristics" on page 35

table

represents the automatic sleep mode current

specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method

of resetting the device to reading array data.

When the RESET# pin is driven low for at least

a period of t

, the device immediately termi-

nates any operation in progress, tristates all

output pins, and ignores all read/write com-

mands for the duration of the RESET# pulse.

The device also resets the internal state ma-

chine to reading array data. The operation that

was interrupted should be reinitiated once the

device is ready to accept another command se-

quence, to ensure data integrity.

Current is reduced for the duration of the RE-

SET# pulse. When RESET# is held at V

±0.3

V, the device draws CMOS standby current

CC4

). If RESET# is held at V

but not within

±0.3 V, the standby current is greater.

The RESET# pin may be tied to the system

reset circuitry. A system reset would thus also

reset the Flash memory, enabling the system to

read the boot-up firmware from the Flash

memory.
If RESET# is asserted during a program or

erase operation, the RY/BY# pin remains a "0"

(busy) until the internal reset operation is com-

plete, which requires a time of t

READY

(during

Embedded Algorithms). The system can thus

monitor RY/BY# to determine whether the

reset operation is complete. If RESET# is as-

serted when a program or erase operation is

not executing (RY/BY# pin is "1"), the reset op-

eration is completed within a time of t

READY

(not

during Embedded Algorithms). The system can

read data t

after the RESET# pin returns to

Refer to the AC Characteristics tables for RE-

SET# parameters and to

Figure 15, on page 39

for the timing diagram.

Output Disable Mode

When the OE# input is at V

, output from the

device is disabled. The output pins are placed in

the high impedance state.

Table 2. Top Boot Sector Addresses (Am29LV320DT) (Sheet 1 of 2)

Sector

Sector Address

A20A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

SA0

000000xxx

64/32

000000h00FFFFh

000000h07FFFh

SA1

000001xxx

64/32

010000h01FFFFh

008000h0FFFFh

SA2

000010xxx

64/32

020000h02FFFFh

010000h17FFFh

SA3

000011xxx

64/32

030000h03FFFFh

018000h01FFFFh

SA4

000100xxx

64/32

040000h04FFFFh

020000h027FFFh

SA5

000101xxx

64/32

050000h05FFFFh

028000h02FFFFh

SA6

000110xxx

64/32

060000h06FFFFh

030000h037FFFh

SA7

000111xxx

64/32

070000h07FFFFh

038000h03FFFFh

SA8

001000xxx

64/32

080000h08FFFFh

040000h047FFFh

SA9

001001xxx

64/32

090000h09FFFFh

048000h04FFFFh

SA10

001010xxx

64/32

0A0000h0AFFFFh

050000h057FFFh

SA11

001011xxx

64/32

0B0000h0BFFFFh

058000h05FFFFh

SA12

001100xxx

64/32

0C0000h0CFFFFh

060000h067FFFh

SA13

001101xxx

64/32

0D0000h0DFFFFh

068000h06FFFFh

SA14

001110xxx

64/32

0E0000h0EFFFFh

070000h077FFFh

SA15

001111xxx

64/32

0F0000h0FFFFFh

078000h07FFFFh

SA16

010000xxx

64/32

100000h10FFFFh

080000h087FFFh

SA17

010001xxx

64/32

110000h11FFFFh

088000h08FFFFh

SA18

010010xxx

64/32

120000h12FFFFh

090000h097FFFh

Am29LV320D

November 15, 2004

Note: The address range is A20:A-1 in byte mode (BYTE#=V

) or A20:A0 in word mode (BYTE#=V

Table 3. Top Boot SecSi

Sector Addresses

SA19

010011xxx

64/32

130000h13FFFFh

098000h09FFFFh

SA20

010100xxx

64/32

140000h14FFFFh

0A0000h0A7FFFh

SA21

010101xxx

64/32

150000h15FFFFh

0A8000h0AFFFFh

SA22

010110xxx

64/32

160000h16FFFFh

0B0000h0B7FFFh

SA23

010111xxx

64/32

170000h17FFFFh

0B8000h0BFFFFh

SA24

011000xxx

64/32

180000h18FFFFh

0C0000h0C7FFFh

SA25

011001xxx

64/32

190000h19FFFFh

0C8000h0CFFFFh

SA26

011010xxx

64/32

1A0000h1AFFFFh

0D0000h0D7FFFh

SA27

011011xxx

64/32

1B0000h1BFFFFh

0D8000h0DFFFFh

SA28

011100xxx

64/32

1C0000h1CFFFFh

0E0000h0E7FFFh

SA29

011101xxx

64/32

1D0000h1DFFFFh

0E8000h0EFFFFh

SA30

011110xxx

64/32

1E0000h1EFFFFh

0F0000h0F7FFFh

SA31

011111xxx

64/32

1F0000h1FFFFFh

0F8000h0FFFFFh

SA32

100000xxx

64/32

200000h20FFFFh

100000h107FFFh

SA33

100001xxx

64/32

210000h21FFFFh

108000h10FFFFh

SA34

100010xxx

64/32

220000h22FFFFh

110000h117FFFh

SA35

100011xxx

64/32

230000h23FFFFh

118000h11FFFFh

SA36

100100xxx

64/32

240000h24FFFFh

120000h127FFFh

SA37

100101xxx

64/32

250000h25FFFFh

128000h12FFFFh

SA38

100110xxx

64/32

260000h26FFFFh

130000h137FFFh

SA39

100111xxx

64/32

270000h27FFFFh

138000h13FFFFh

SA40

101000xxx

64/32

280000h28FFFFh

140000h147FFFh

SA41

101001xxx

64/32

290000h29FFFFh

148000h14FFFFh

SA42

101010xxx

64/32

2A0000h2AFFFFh

150000h157FFFh

SA43

101011xxx

64/32

2B0000h2BFFFFh

158000h15FFFFh

SA44

101100xxx

64/32

2C0000h2CFFFFh

160000h167FFFh

SA45

101101xxx

64/32

2D0000h2DFFFFh

168000h16FFFFh

SA46

101110xxx

64/32

2E0000h2EFFFFh

170000h177FFFh

SA47

101111xxx

64/32

2F0000h2FFFFFh

178000h17FFFFh

SA48

110000xxx

64/32

300000h30FFFFh

180000h187FFFh

SA49

110001xxx

64/32

310000h31FFFFh

188000h18FFFFh

SA50

110010xxx

64/32

320000h32FFFFh

190000h197FFFh

SA51

110011xxx

64/32

330000h33FFFFh

198000h19FFFFh

SA52

110100xxx

64/32

340000h34FFFFh

1A0000h1A7FFFh

SA53

110101xxx

64/32

350000h35FFFFh

1A8000h1AFFFFh

SA54

110110xxx

64/32

360000h36FFFFh

1B0000h1B7FFFh

SA55

110111xxx

64/32

370000h37FFFFh

1B8000h1BFFFFh

SA56

111000xxx

64/32

380000h38FFFFh

1C0000h1C7FFFh

SA57

111001xxx

64/32

390000h39FFFFh

1C8000h1CFFFFh

SA58

111010xxx

64/32

3A0000h3AFFFFh

1D0000h1D7FFFh

SA59

111011xxx

64/32

3B0000h3BFFFFh

1D8000h1DFFFFh

SA60

111100xxx

64/32

3C0000h3CFFFFh

1E0000h1E7FFFh

SA61

111101xxx

64/32

3D0000h3DFFFFh

1E8000h1EFFFFh

SA62

111110xxx

64/32

3E0000h3EFFFFh

1F0000h1F7FFFh

SA63

111111000

8/4

3F0000h3F1FFFh

1F8000h1F8FFFh

SA64

111111001

8/4

3F2000h3F3FFFh

1F9000h1F9FFFh

SA65

111111010

8/4

3F4000h3F5FFFh

1FA000h1FAFFFh

SA66

111111011

8/4

3F6000h3F7FFFh

1FB000h1FBFFFh

SA67

111111100

8/4

3F8000h3F9FFFh

1FC000h1FCFFFh

SA68

111111101

8/4

3FA000h3FBFFFh

1FD000h1FDFFFh

SA69

111111110

8/4

3FC000h3FDFFFh

1FE000h1FEFFFh

SA70

111111111

8/4

3FE000h3FFFFFh

1FF000h1FFFFFh

Table 2. Top Boot Sector Addresses (Am29LV320DT) (Sheet 2 of 2)

Sector

Sector Address

A20A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

Sector Address

A20A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

111111xxx

64/32

3F0000h3FFFFFh

1F8000h1FFFFFh

November 15, 2004

Am29LV320D

Table 4. Bottom Boot Sector Addresses (Am29LV320DB) (Sheet 1 of 2)

Sector

Sector Address

A20A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

SA0

000000000

8/4

000000h-001FFFh

000000h000FFFh

SA1

000000001

8/4

002000h-003FFFh

001000h001FFFh

SA2

000000010

8/4

004000h-005FFFh

002000h002FFFh

SA3

000000011

8/4

006000h-007FFFh

003000h003FFFh

SA4

000000100

8/4

008000h-009FFFh

004000h004FFFh

SA5

000000101

8/4

00A000h-00BFFFh

005000h005FFFh

SA6

000000110

8/4

00C000h-00DFFFh

006000h006FFFh

SA7

000000111

8/4

00E000h-00FFFFh

007000h007FFFh

SA8

000001xxx

64/32

010000h-01FFFFh

008000h00FFFFh

SA9

000010xxx

64/32

020000h-02FFFFh

010000h017FFFh

SA10

000011xxx

64/32

030000h-03FFFFh

018000h01FFFFh

SA11

000100xxx

64/32

040000h-04FFFFh

020000h027FFFh

SA12

000101xxx

64/32

050000h-05FFFFh

028000h02FFFFh

SA13

000110xxx

64/32

060000h-06FFFFh

030000h037FFFh

SA14

000111xxx

64/32

070000h-07FFFFh

038000h03FFFFh

SA15

001000xxx

64/32

080000h-08FFFFh

040000h047FFFh

SA16

001001xxx

64/32

090000h-09FFFFh

048000h04FFFFh

SA17

001010xxx

64/32

0A0000h-0AFFFFh

050000h057FFFh

SA18

001011xxx

64/32

0B0000h-0BFFFFh

058000h05FFFFh

SA19

001100xxx

64/32

0C0000h-0CFFFFh

060000h067FFFh

SA20

001101xxx

64/32

0D0000h-0DFFFFh

068000h06FFFFh

SA21

001110xxx

64/32

0E0000h-0EFFFFh

070000h077FFFh

SA22

001111xxx

64/32

0F0000h-0FFFFFh

078000h07FFFFh

SA23

010000xxx

64/32

100000h-10FFFFh

080000h087FFFh

SA24

010001xxx

64/32

110000h-11FFFFh

088000h08FFFFh

SA25

010010xxx

64/32

120000h-12FFFFh

090000h097FFFh

SA26

010011xxx

64/32

130000h-13FFFFh

098000h09FFFFh

SA27

010100xxx

64/32

140000h-14FFFFh

0A0000h0A7FFFh

SA28

010101xxx

64/32

150000h-15FFFFh

0A8000h0AFFFFh

SA29

010110xxx

64/32

160000h-16FFFFh

0B0000h0B7FFFh

SA30

010111xxx

64/32

170000h-17FFFFh

0B8000h0BFFFFh

SA31

011000xxx

64/32

180000h-18FFFFh

0C0000h0C7FFFh

SA32

011001xxx

64/32

190000h-19FFFFh

0C8000h0CFFFFh

SA33

011010xxx

64/32

1A0000h-1AFFFFh

0D0000h0D7FFFh

SA34

011011xxx

64/32

1B0000h-1BFFFFh

0D8000h0DFFFFh

SA35

011100xxx

64/32

1C0000h-1CFFFFh

0E0000h0E7FFFh

SA36

011101xxx

64/32

1D0000h-1DFFFFh

0E8000h0EFFFFh

SA37

011110xxx

64/32

1E0000h-1EFFFFh

0F0000h0F7FFFh

SA38

011111xxx

64/32

1F0000h-1FFFFFh

0F8000h0FFFFFh

SA39

100000xxx

64/32

200000h-20FFFFh

100000h107FFFh

SA40

100001xxx

64/32

210000h-21FFFFh

108000h10FFFFh

SA41

100010xxx

64/32

220000h-22FFFFh

110000h117FFFh

SA42

100011xxx

64/32

230000h-23FFFFh

118000h11FFFFh

SA43

100100xxx

64/32

240000h-24FFFFh

120000h127FFFh

SA44

100101xxx

64/32

250000h-25FFFFh

128000h12FFFFh

SA45

100110xxx

64/32

260000h-26FFFFh

130000h137FFFh

SA46

100111xxx

64/32

270000h-27FFFFh

138000h13FFFFh

SA47

101000xxx

64/32

280000h-28FFFFh

140000h147FFFh

SA48

101001xxx

64/32

290000h-29FFFFh

148000h14FFFFh

SA49

101010xxx

64/32

2A0000h-2AFFFFh

150000h157FFFh

SA50

101011xxx

64/32

2B0000h-2BFFFFh

158000h15FFFFh

SA51

101100xxx

64/32

2C0000h-2CFFFFh

160000h167FFFh

SA52

101101xxx

64/32

2D0000h-2DFFFFh

168000h16FFFFh

Am29LV320D

November 15, 2004

Note: The address range is A20:A-1 in byte mode (BYTE#=V

) or A20:A0 in word mode (BYTE#=V

Table 5. Bottom Boot SecSi

Sector Addresses

Autoselect Mode

The autoselect mode provides manufacturer

and device identification, and sector protection

verification, through identifier codes output on

DQ7DQ0. This mode is primarily intended for

programming equipment to automatically

match a device to be programmed with its cor-

responding programming algorithm. However,

the autoselect codes can also be accessed

in-system through the command register.

When using programming equipment, the au-

toselect mode requires V

(11.5 V to 12.5 V)

on address pin A9. Address pins A6, A1, and A0

must be as shown in

Table 6, on page 16

. In

addition, when verifying sector protection, the

sector address must appear on the appropriate

highest order address bits (see

Table 2, on

page 13

through

Table 5, on page 16

Table 6,

on page 16

shows the remaining address bits

that are don't care. When all necessary bits are

set as required, the programming equipment

may then read the corresponding identifier

code on DQ7DQ0.
To access the autoselect codes in-system, the

host system can issue the autoselect command

v i a t he c o m m a n d r e g is t e r, a s sh o w n in

Table 14, on page 29

. This method does not re-

quire V

. Refer to the

"Autoselect Command

Sequence" on page 25

section for more infor-

mation.

Table 6. Autoselect Codes (High Voltage Method)

Legend: T = Top Boot Block, B = Bottom Boot Block, L = Logic Low = V

, H = Logic High = V

, SA = Sector

Address, X = Don't care.

SA53

101110xxx

64/32

2E0000h-2EFFFFh

170000h177FFFh

SA54

101111xxx

64/32

2F0000h-2FFFFFh

178000h17FFFFh

SA55

111000xxx

64/32

300000h-30FFFFh

180000h187FFFh

SA56

110001xxx

64/32

310000h-31FFFFh

188000h18FFFFh

SA57

110010xxx

64/32

320000h-32FFFFh

190000h197FFFh

SA58

110011xxx

64/32

330000h-33FFFFh

198000h19FFFFh

SA59

110100xxx

64/32

340000h-34FFFFh

1A0000h1A7FFFh

SA60

110101xxx

64/32

350000h-35FFFFh

1A8000h1AFFFFh

SA61

110110xxx

64/32

360000h-36FFFFh

1B0000h1B7FFFh

SA62

110111xxx

64/32

370000h-37FFFFh

1B8000h1BFFFFh

SA63

111000xxx

64/32

380000h-38FFFFh

1C0000h1C7FFFh

SA64

111001xxx

64/32

390000h-39FFFFh

1C8000h1CFFFFh

SA65

111010xxx

64/32

3A0000h-3AFFFFh

1D0000h1D7FFFh

SA66

111011xxx

64/32

3B0000h-3BFFFFh

1D8000h1DFFFFh

SA67

111100xxx

64/32

3C0000h-3CFFFFh

1E0000h1E7FFFh

SA68

111101xxx

64/32

3D0000h-3DFFFFh

1E8000h1EFFFFh

SA69

111110xxx

64/32

3E0000h-3EFFFFh

1F0000h1F7FFFh

SA70

111111xxx

64/32

3F0000h-3FFFFFh

1F8000h1FFFFFh

Sector Address

A20A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

000000xxx

64/32

000000h-00FFFFh

00000h-07FFFh

Table 4. Bottom Boot Sector Addresses (Am29LV320DB) (Sheet 2 of 2)

Sector

Sector Address

A20A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

Description

CE# OE# WE#

A20

A12

A11

A10

DQ8 to DQ15

DQ7

DQ0

BYTE#

= V

BYTE#

= V

Manufacturer ID: AMD

01h

Device ID: Am29LV320D

22h

F6 (T), F9h (B)

Sector Protection

Verification

01h (protected),

00h (unprotected)

SecSi

Sector Indicator

Bit (DQ7)

99h (factory locked),

19h (not factory

locked)

November 15, 2004

Am29LV320D

Sector/Sector Block Protection and
Unprotection

The hardware sector protection feature disables

both program and erase operations in any sec-

tor. The hardware sector unprotection feature

re-enables both program and erase operations

in previously protected sectors. Sector protec-

tion/unprotection can be implemented via two

methods.
(Note: For the following discussion, the term

"sector" applies to both sectors and sector

blocks. A sector block consists of two or more

adjacent sectors that are protected or unpro-

tected at the same time (see

Table 7, on

page 17

and

Table 8, on page 17

Table 7. Top Boot Sector/Sector Block

Addresses for Protection/Unprotection

Table 8. Bottom Boot Sector/Sector Block

Addresses for Protection/Unprotection

Sector Protection and unprotection requires V

on the RESET# pin only, and can be imple-

mented either in-system or via programming

equipment.

Figure 2, on page 19

shows the al-

gorithms and

Figure 25, on page 47

shows the

timing diagram. This method uses standard mi-

croprocessor bus cycle timing. For sector un-

protect, all unprotected sectors must first be

protected prior to the first sector unprotect

write cycle.
The sector unprotect algorithm unprotects all

sectors in parallel. All previously protected sec-

tors must be individually re-protected. To

change data in protected sectors efficiently, the

temporary sector unprotect function is avail-

able. See

"Temporary Sector Unprotect" on

page 18

The alternate method intended only for pro-

gramming equipment, and requires V

on ad-

d r e s s p i n A 9 a n d O E # . Th i s m e t h o d i s

Sector / Sector

Block

A20A12

Sector/Sector Block

Size

SA0-SA3

000000XXX,

000001XXX,

000010XXX

000011XXX

256 (4x64) Kbytes

SA4-SA7

0001XXXXX

256 (4x64) Kbytes

SA8-SA11

0010XXXXX

256 (4x64) Kbytes

SA12-SA15

0011XXXXX

256 (4x64) Kbytes

SA16-SA19

0100XXXXX

256 (4x64) Kbytes

SA20-SA23

0101XXXXX

256 (4x64) Kbytes

SA24-SA27

0110XXXXX

256 (4x64) Kbytes

SA28-SA31

0111XXXXX

256 (4x64) Kbytes

SA32-SA35

1000XXXXX

256 (4x64) Kbytes

SA36-SA39

1001XXXXX

256 (4x64) Kbytes

SA40-SA43

1010XXXXX

256 (4x64) Kbytes

SA44-SA47

1011XXXXX

256 (4x64) Kbytes

SA48-SA51

1100XXXXX

256 (4x64) Kbytes

SA52-SA55

1101XXXXX

256 (4x64) Kbytes

SA56-SA59

1110XXXXX

256 (4x64) Kbytes

SA60-SA62

111100XXX,

111101XXX,

111110XXX

192 (3x64) Kbytes

SA63

111111000

8 Kbytes

SA64

111111001

8 Kbytes

SA65

111111010

8 Kbytes

SA66

111111011

8 Kbytes

SA67

111111100

8 Kbytes

SA68

111111101

8 Kbytes

SA69

111111110

8 Kbytes

SA70

111111111

8 Kbytes

Sector / Sector

Block

A20A12

Sector/Sector Block

Size

SA70-SA67

111111XXX,

111110XXX,

111101XXX,

111100XXX

256 (4x64) Kbytes

SA66-SA63

1110XXXXX

256 (4x64) Kbytes

SA62-SA59

1101XXXXX

256 (4x64) Kbytes

SA58-SA55

1100XXXXX

256 (4x64) Kbytes

SA54-SA51

1011XXXXX

256 (4x64) Kbytes

SA50-SA47

1010XXXXX

256 (4x64) Kbytes

SA46-SA43

1001XXXXX

256 (4x64) Kbytes

SA42-SA39

1000XXXXX

256 (4x64) Kbytes

SA38-SA35

0111XXXXX

256 (4x64) Kbytes

SA34-SA31

0110XXXXX

256 (4x64) Kbytes

SA30-SA27

0101XXXXX

256 (4x64) Kbytes

SA26-SA23

0100XXXXX

256 (4x64) Kbytes

SA22SA19

0011XXXXX

256 (4x64) Kbytes

SA18-SA15

0010XXXXX

256 (4x64) Kbytes

SA14-SA11

0001XXXXX

256 (4x64) Kbytes

SA10-SA8

000011XXX,

000010XXX,

000001XXX

192 (3x64) Kbytes

SA7

000000111

8 Kbytes

SA6

000000110

8 Kbytes

SA5

000000101

8 Kbytes

SA4

000000100

8 Kbytes

SA3

000000011

8 Kbytes

SA2

000000010

8 Kbytes

SA1

000000001

8 Kbytes

SA0

000000000

8 Kbytes

Am29LV320D

November 15, 2004

compatible with programmer routines written

for earlier 3.0 volt-only AMD flash devices. For

detailed information, contact an AMD represen-

tative.

The device is shipped with all sectors unpro-

tected. AMD offers the option of programming

and protecting sectors at its factory prior to

shipping the device through AMD's Express-

FlashTM Service. Contact an AMD representative

for details.
It is possible to determine whether a sector is

protected or unprotected. See

"Autoselect

Mode" on page 16

for details.

Write Protect (WP#)

The Write Protect function provides a hardware

method of protecting certain boot sectors with-

out using V

. This function is one of two pro-

vided by the WP#/ACC pin.

If the system asserts V

on the WP#/ACC pin,

the device disables program and erase func-

tions in the two "outermost" 8 Kbyte boot sec-

tors independently of whether those sectors

were protected or unprotected using the

method described in

"Sector/Sector Block Pro-

tection and Unprotection" on page 17

. The two

outermost 8 Kbyte boot sectors are the two

sectors containing the lowest addresses in a

bottom-boot-configured device, or the two sec-

tors containing the highest addresses in a

top-boot-configured device.

If the system asserts V

on the WP#/ACC pin,

the device reverts to whether the two outer-

most 8K Byte boot sectors were last set to be

protected or unprotected. That is, sector pro-

tection or unprotection for these two sectors

depends on whether they were last protected

or unprotected using the method described in

"Sector/Sector Block Protection and Unprotec-

tion" on page 17

Note that the WP#/ACC pin must not be left

floating or unconnected; inconsistent behavior

of the device may result.

Temporary Sector Unprotect

This feature allows temporary unprotection of

previously protected sectors to change data

in-system. The Sector Unprotect mode is acti-

vated by setting the RESET# pin to V

(11.5 V

12.5 V). During this mode, formerly pro-

tected sectors can be programmed or erased by

selecting the sector addresses. Once V

is re-

moved from the RESET# pin, all the previously

protected sectors are protected again.

Figure 1,

on page 18

shows the algorithm, and

Figure

23, on page 46

shows the timing diagrams, for

this feature.

Figure 1. Temporary Sector Unprotect

Operation

START

Perform Erase or

Program

RESET# = V

Temporary Sector

Unprotect Completed

(Note 2)

RESET# = V

(Note 1)

Notes:
1. All protected sectors unprotected (If WP#/ACC =

, outermost boot sectors remain protected).

2. All previously protected sectors are protected

once again.

Am29LV320D

November 15, 2004

SecSi

Sector (Secured Silicon) Flash

Memory Region

The Secured Silicon Sector (SecSi Sector) fea-

ture provides a Flash memory region that en-

ables permanent part identification through an

Electronic Serial Number (ESN). The SecSi Sec-

tor uses a SecSi Sector Indicator Bit (DQ7) to

indicate whether or not the SecSi Sector is

locked when shipped from the factory. This bit

is permanently set at the factory and cannot be

changed, which prevents cloning of a factory

locked part. This ensures the security of the

ESN once the product is shipped to the field.

Note that the Am29LV320D has a SecSi

Sector size of 64 Kbytes. AMD devices des-

ignated as replacements or substitutes,

such as the Am29LV320M, have 256 bytes.

This should be considered during system

design.
AMD offers the device with the SecSi Sector ei-

ther factory locked or customer lockable. The

factory-locked version is always protected

when shipped from the factory, and has the

SecSi Sector Indicator Bit permanently set to a

"1." The customer-lockable version is shipped

with the SecSi Sector unprotected, allowing

customers to utilize the that sector in any man-

ner they choose. The customer-lockable ver-

s io n ha s t he S e cS i Se ct or In di ca to r B i t

permanently set to a "0." Thus, the SecSi Sec-

tor Indicator Bit prevents customer-lockable

devices from being used to replace devices that

are factory locked.

The system accesses the SecSi Sector through

a command sequence (see

"Enter SecSi

Sec-

tor/Exit SecSi Sector Command Sequence" on

page 26

). After the system writes the Enter

SecSi Sector command sequence, it may read

the SecSi Sector by using the addresses nor-

mally occupied by the boot sectors. This mode

of operation continues until the system issues

the Exit SecSi Sector command sequence, or

until power is removed from the device. On

power-up, or following a hardware reset, the

device reverts to sending commands to the

boot sectors.

Factory Locked: SecSi Sector Programmed

and Protected at the Factory
In a factory locked device, the SecSi Sector is

protected when the device is shipped from the

factory. The SecSi Sector cannot be modified in

any way. The device is available prepro-

grammed with one of the following:

A random, secure ESN only

Customer code through the ExpressFlash

service

Both a random, secure ESN and customer

code through the ExpressFlash service.

In devices that have an ESN, a Bottom Boot de-

vice has the 16-byte (8-word) ESN in sector 0

at addresses 00000h0000Fh in byte mode (or

00000h00007h in word mode). In the Top

Boot device the ESN is in sector 63 at ad-

dresses 3F0000h3F000Fh in byte mode (or

1F8000h1F8007h in word mode). Note that in

upcoming top boot versions of this device, the

ESN is located in sector 70 at addresses

3 F E 0 0 0 h 3 F E 0 0 F h i n b y t e m o d e ( o r

1FF000h1FF007h in word mode).
Customers may opt to have their code pro-

grammed by AMD through the AMD Express-

Flash service. AMD programs the customer's

code, with or without the random ESN. The de-

vices are then shipped from AMD's factory with

the SecSi Sector permanently locked. Contact

an AMD representative for details on using

AMD's ExpressFlash service.

Customer Lockable: SecSi Sector NOT

Programmed or Protected at the Factory
The customer lockable version allows the SecSi

Sector to be programmed once and then per-

manently locked after it ships from AMD. Note

that the Am29LV320D has a SecSi Sector

size of 64 Kbytes. AMD devices designated

as replacements or substitutes, such as

the Am29LV320M, have 256 bytes. This

should be considered during system de-

sign. Additionally, note the change in the

location of the ESN in upcoming top boot

factory locked devices. Note that the accel-

erated programming (ACC) and unlock bypass

functions are not available when programming

the SecSi Sector.
The SecSi Sector area can be protected using

the following procedures:

Write the three-cycle Enter SecSi Region

command sequence, and then follow the

in-system sector protect algorithm as shown

Figure 2, on page 19

, except that RESET#

may be at either V

or V

. This allows

in-system protection of the SecSi Sector

without raising any device pin to a high volt-

age. Note that this method is only applicable

to the SecSi Sector.

To verify the protect/unprotect status of the

SecSi Sector, follow the algorithm shown in

Figure 3, on page 21

November 15, 2004

Am29LV320D

Once the SecSi Sector is locked and verified,

the system must write the Exit SecSi Sector

Region command sequence to return to reading

and writing the remainder of the array.

The SecSi Sector protection must be used with

caution since, once protected, there is no pro-

cedure available for unprotecting the SecSi

Sector area and none of the bits in the SecSi

Sector memory space can be modified in any

way.

Figure 3. SecSi Sector Protect Verify

Hardware Data Protection

The command sequence requirement of unlock

cycles for programming or erasing provides

data protection against inadvertent writes (re-

fer to

Table 14, on page 29

for command defi-

nitions). In addition, the following hardware

data protection measures prevent accidental

erasure or programming, which might other-

wise be caused by spurious system level signals

during V

power-up and power-down transi-

tions, or from system noise.

Low V

Write Inhibit

When V

is less than V

LKO

, the device does not

accept any write cycles. This protects data dur-

ing V

power-up and power-down. The com-

mand register and all internal program/erase

circuits are disabled, and the device resets to

the read mode. Subsequent writes are ignored

until V

is greater than V

LKO

. The system must

provide the proper signals to the control pins to

prevent unintentional writes when V

C C

greater than V

LKO

Write Pulse "Glitch" Protection
Noise pulses of less than 5 ns (typical) on OE#,

CE# or WE# do not initiate a write cycle.

Logical Inhibit
Write cycles are inhibited by holding any one of

OE# = V

, CE# = V

or WE# = V

. To initiate

a write cycle, CE# and WE# must be a logical

zero while OE# is a logical one.

Power-Up Write Inhibit
If WE# = CE# = V

and OE# = V

during

power up, the device does not accept com-

mands on the rising edge of WE#. The internal

state machine is automatically reset to the read
mode on power-up.

COMMON FLASH MEMORY
INTERFACE (CFI)

The Common Flash Interface (CFI) specification

outlines device and host system software inter-

rogation handshake, which allows specific ven-

dor-specified software algorithms to be used

for entire families of devices. Software support

can then be device-independent, JEDEC ID-in-

dependent, and forward- and backward-com-

patible for the specified flash device families.

Flash vendors can standardize their existing in-

terfaces for long-term compatibility.
This device enters the CFI Query mode when

the system writes the CFI Query command,

98h, to address 55h in word mode (or address

AAh in byte mode), any time the device is

ready to read array data. The system can read

CFI information at the addresses given in

Table 9, on page 22

through

Table 12, on

page 24

. To terminate reading CFI data, the

system must write the reset command.

The system can also write the CFI query com-

mand when the device is in the autoselect

mode. The device enters the CFI query mode,

and the system can read CFI data at the ad-

dresses given in

Table 9, on page 22

through

Table 12, on page 24

. The system must write

the reset command to return the device to the

reading array data.
For further information, please refer to the CFI

Specification and CFI Publication 100, available

v i a t h e Wo r l d W i d e We b a t

http://www.amd.com/flash/cfi. Alternatively,

contact an AMD representative for copies of

these documents.

Write 60h to

any address

Write 40h to SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

START

RESET# =

or V

Wait 1

Read from SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

If data = 00h,

SecSi Sector is

unprotected.

If data = 01h,

SecSi Sector is

protected.

Remove V

or V

from RESET#

Write reset

command

SecSi Sector

Protect Verify

complete

November 15, 2004

Am29LV320D

COMMAND DEFINITIONS

Writing specific address and data commands or

sequences into the command register initiates

device operations.

Table 14, on page 29

defines

the valid register command sequences. Note

that writing incorrect address and data values

or writing them in the improper sequence may

place the device in an unknown state. A reset

command is required to return the device to

normal operation.
All addresses are latched on the falling edge of

WE# or CE#, whichever happens later. All data

is latched on the rising edge of WE# or CE#,

whichever happens first. Refer to the AC Char-

acteristics section for timing diagrams.

Reading Array Data

The device is automatically set to reading array

data after device power-up. No commands are

required to retrieve data. The device is ready to

read array data after completing an Embedded

Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend

command, the device enters the erase-sus-

pend-read mode, after which the system can

read data from any non-erase-suspended sec-

tor. After completing a programming operation

in the Erase Suspend mode, the system may

once again read array data with the same ex-

ception. See

"Erase Suspend/Erase Resume

Commands" on page 28

for more information.

The system must issue the reset command to

return the device to the read (or erase-sus-

pend-read) mode if DQ5 goes high during an

active program or erase operation, or if the de-

vice is in the autoselect mode. See the next

section,

"Reset Command

, for more informa-

tion.
See also

"Requirements for Reading Array

Data" on page 11

for more information. The

Read-Only Operations table provides the read

parameters, and

Figure 14, on page 38

shows

the timing diagram.

Reset Command

Writing the reset command resets the device to

the read or erase-suspend-read mode. Address

bits are don't cares for this command.
The reset command may be written between

the sequence cycles in an erase command se-

quence before erasing begins. This resets the

device to which the system was writing to the

read mode. Once erasure begins, however, the

device ignores reset commands until the opera-

tion is complete.
The reset command may be written between

the sequence cycles in a program command se-

quence before programming begins. This resets

the device to which the system was writing to

the read mode. If the program command se-

quence is written to a sector that is in the Erase

Suspend mode, writing the reset command re-

turns the device to the erase-suspend-read

mode. Once programming begins, however, the

device ignores reset commands until the opera-

tion is complete.
The reset command may be written between

the sequence cycles in an autoselect command

sequence. Once in the autoselect mode, the

reset command must be written to return to

the read mode. If the device entered the au-

toselect mode while in the Erase Suspend

mode, writing the reset command returns the

device to the erase-suspend-read mode.
If DQ5 goes high during a program or erase op-

eration, writing the reset command returns the

d evice to the rea d m ode (or era se-sus-

pend-read mode if the device was in Erase Sus-

pend).

Autoselect Command Sequence

The autoselect command sequence allows the

host system to read several identifier codes at

specific addresses:

Table 13. Autoselect Codes

Table 14, on page 29

shows the address and

data requirements. This method is an alterna-

tive to that shown in

Table 6, on page 16

which is intended for PROM programmers and

requires V

on address pin A9. The autoselect

command sequence may be written to an ad-

dress within sector that is either in the read or

erase-suspend-read mode. The autoselect

command may not be written while the device

is actively programming or erasing.
The autoselect command sequence is initiated

by first writing two unlock cycles. This is fol-

lowed by a third write cycle that contains the

autoselect command. The device then enters

the autoselect mode. The system may read at

any address any number of times without initi-

ating another autoselect command sequence.
The system must write the reset command to

retu rn to the rea d m ode (or e ra se-su s-

pend-read mode if the device was previously in

Erase Suspend).

Identifier Code

Address

Manufacturer ID

00h

Device ID

01h

SecSi Sector Factory Protect

03h

Sector Group Protect Verify

(SA)02h

Am29LV320D

November 15, 2004

Enter SecSi

Sector/Exit SecSi Sector

Command Sequence

The SecSi Sector region provides a secured

data area containing a random, sixteen-byte

electronic serial number (ESN). The system can

access the SecSi Sector region by issuing the

three-cycle Enter SecSi Sector command se-

quence. The device continues to access the

SecSi Sector region until the system issues the

four-cycle Exit SecSi Sector command se-

quence. The Exit SecSi Sector command se-

quence returns the device to normal operation.

Table 14, on page 29

shows the address and

data requirements for both command se-

quences. Note that the ACC function and unlock

bypass modes are not available when the de-

vice enters the SecSi Sector. See also

"SecSi

Sector (Secured Silicon) Flash Memory Region"

on page 20

for further information.

Byte/Word Program Command Sequence

The system may program the device by word or

byte, depending on the state of the BYTE# pin.

Programming is a four-bus-cycle operation. The

program command sequence is initiated by

writing two unlock write cycles, followed by the

program set-up command. The program ad-

dress and data are written next, which in turn

initiate the Embedded Program algorithm. The

system is not required to provide further con-

trols or timings. The device automatically pro-

vides internally generated program pulses and

verifies the programmed cell margin.

Table 14,

on page 29

shows the address and data re-

quirements for the byte program command se-

quence. Note that the autoselect, SecSi Sector,

and CFI modes are unavailable while a pro-

gramming operation is in progress.
When the Embedded Program algorithm is

complete, the device then returns to the read

mode and addresses are no longer latched. The

system can determine the status of the pro-

gram operation by using DQ7, DQ6, or RY/BY#.

Refer to

"Write Operation Status" on page 30

for information on these status bits.
Any commands written to the device during the

Embedded Program Algorithm are ignored.

Note that a hardware reset immediately ter-

minates the program operation. The program

command sequence should be reinitiated once

the device returns to the read mode, to ensure

data integrity.

Programming is allowed in any sequence and

across sector boundaries. A bit cannot be

programmed from "0" back to a "1." At-

tempting to do so may cause the device to set

DQ5 = 1, or cause the DQ7 and DQ6 status bits

to indicate the operation was successful. How-

ever, a succeeding read shows that the data is

still "0." Only erase operations can convert a

"0" to a "1."

Unlock Bypass Command Sequence
The unlock bypass feature allows the system to

program bytes or words to the device faster

than using the standard program command se-

quence. The unlock bypass command sequence

is initiated by first writing two unlock cycles.

This is followed by a third write cycle containing

the unlock bypass command, 20h. The device

then enters the unlock bypass mode. A two-cy-

cle unlock bypass program command sequence

is all that is required to program in this mode.

The first cycle in this sequence contains the un-

lock bypass program command, A0h; the sec-

ond cycle contains the program address and

data. Additional data is programmed in the

same manner. This mode dispenses with the

initial two unlock cycles required in the stan-

dard program command sequence, resulting in

faster total programming time.

Table 14, on

page 29

shows the requirements for the com-

mand sequence.

During the unlock bypass mode, only the Un-

lock Bypass Program and Unlock Bypass Reset

commands are valid. To exit the unlock bypass

mode, the system must issue the two-cycle un-

lock bypass reset command sequence. The first

cycle must contain the data 90h. The second

cycle need only contain the data 00h. The de-

vice then re turns to the read mode.
The device offers accelerated program opera-

tions through the WP#/ACC pin. When the sys-

tem asserts V

on the WP#/ACC pin, the

device automatically enters the Unlock Bypass

mode. The system may then write the two-cy-

cle Unlock Bypass program command se-

quence. The device uses the higher voltage on

the WP#/ACC pin to accelerate the operation.

Note that the WP#/ACC pin must not be at V

any operation other than accelerated program-

ming, or device damage may result. In addi-

tion, the WP#/ACC pin must not be left floating

or unconnected; inconsistent behavior of the

device may result.

Figure 4, on page 27

illustrates the algorithm

for the program operation. Refer to the table

"Erase and Program Operations" on page 41

for

parameters, and

Figure 18, on page 42

for tim-

ing diagrams.

November 15, 2004

Am29LV320D

Figure 4. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip

erase command sequence is initiated by writing

two unlock cycles, followed by a set-up com-

mand. Two additional unlock write cycles are

then followed by the chip erase command,

which in turn invokes the Embedded Erase al-

gorithm. The device does not require the sys-

t e m t o p r e p r o g ra m p r i o r t o e ra s e . T h e

Embedded Erase algorithm automatically pre-

programs and verifies the entire memory for an

all zero data pattern prior to electrical erase.

The system is not required to provide any con-

trols or timings during these operations.

Table 14, on page 29

shows the address and

data requirements for the chip erase command

sequence. Note that the autoselect, SecSi Sec-

tor, and CFI modes are unavailable while an

erase operation is in progress.

When the Embedded Erase algorithm is com-

plete, the device returns to the read mode and

addresses are no longer latched. The system

can determine the status of the erase operation

by using DQ7, DQ6, DQ2, or RY/BY#. Refer to

"Write Operation Status" on page 30

for infor-

mation on these status bits.

Any commands written during the chip erase

operation are ignored. However, note that a

hardware reset immediately terminates the

erase operation. If that occurs, the chip erase

command sequence should be reinitiated once

the device returns to reading array data, to en-

sure data integrity.

Figure 5, on page 28

illustrates the algorithm

for the erase operation. Refer to table

"Erase

and Program Operations" on page 41

for pa-

rameters, and

Figure 19, on page 43

section for

timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The

sector erase command sequence is initiated by

writing two unlock cycles, followed by a set-up

command. Two additional unlock cycles are

written, and are then followed by the address

of the sector to be erased, and the sector erase

command.

Table 14, on page 29

shows the ad-

dress and data requirements for the sector

erase command sequence. Note that the au-

toselect, SecSi Sector, and CFI modes are un-

a vailable while an erase operation is in

progress.
The device does not require the system to pre-

program prior to erase. The Embedded Erase

algorithm automatically programs and verifies

the entire memory for an all zero data pattern

prior to electrical erase. The system is not re-

quired to provide any controls or timings during

these operations.

After the command sequence is written, a sec-

tor erase time-out of 50 µs occurs. During the

time-out period, additional sector addresses

and sector erase commands may be written.

Loading the sector erase buffer may be done in

any sequence, and the number of sectors may

be from one sector to all sectors. The time be-

tween these additional cycles must be less than

50 µs, otherwise the last address and com-

mand may not be accepted, and erasure may

begin. It is recommended that processor inter-

rupts be disabled during this time to ensure all

commands are accepted. The interrupts can be

re-enabled after the last Sector Erase com-

mand is written. Any command other than

Sector Erase or Erase Suspend during the

START

Write Program

Command Sequence

Data Poll

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

Note: See

Table 14, on page 29

for program

command sequence.

Am29LV320D

November 15, 2004

time-out period resets the device to the

read mode. The system must rewrite the com-

mand sequence and any additional addresses

and commands.
The system can monitor DQ3 to determine if

the sector erase timer timed out (See the sec-

tion

"DQ3: Sector Erase Timer" on page 32

.).

The time-out begins from the rising edge of the

final WE# pulse in the command sequence.
When the Embedded Erase algorithm is com-

plete, the device returns to reading array data

and addresses are no longer latched. The sys-

tem can determine the status of the erase op-

eration by reading DQ7, DQ6, DQ2, or RY/BY#

in the erasing sector. Refer to

"Write Operation

Status" on page 30

for information on these

status bits.
Once the sector erase operation begins, only

the Erase Suspend command is valid. All other

commands are ignored. However, note that a

hardware reset immediately terminates the

erase operation. If that occurs, the sector erase

command sequence should be reinitiated once

the device returns to reading array data, to en-

sure data integrity.

Figure 5, on page 28

illustrates the algorithm

for the erase operation. Refer to table

"Erase

and Program Operations" on page 41

for pa-

rameters, and

Figure 19, on page 43

for timing

diagrams.

Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the

system to interrupt a sector erase operation

and then read data from, or program data to,

any sector not selected for erasure. This com-

mand is valid only during the sector erase oper-

ation, including the 50 µs time-out period

during the sector erase command sequence.

The Erase Suspend command is ignored if writ-

ten during the chip erase operation or Embed-

ded Program algorithm.
When the Erase Suspend command is written

during the sector erase operation, the device

requires a maximum of 20 µs to suspend the

erase operation. However, when the Erase Sus-

pend command is written during the sector

erase time-out, the device immediately termi-

nates the time-out period and suspends the

erase operation.

After the erase operation is suspended, the de-

vice enters the erase-suspend-read mode. The

system can read data from or program data to

any sector not selected for erasure. (The device

"erase suspends" all sectors selected for era-

sure.) Reading at any address within erase-sus-

pended sectors produces status information on

DQ7DQ0. The system can use DQ7, or DQ6

and DQ2 together, to determine if a sector is

actively erasing or is erase-suspended. Refer to

the

"Write Operation Status" on page 30

sec-

tion for information on these status bits.

After an erase-suspended program operation is

complete, the device returns to the erase-sus-

pend-read mode. The system can determine

the status of the program operation using the

DQ7 or DQ6 status bits, just as in the standard

Byte Program operation. Refer to

"Write Opera-

tion Status" on page 30

for more information.

In the erase-suspend-read mode, the system

can also issue the autoselect command se-

quence. Refer to

"Autoselect Mode" on page 16

and

"Autoselect Command Sequence" on

page 25

for details.

To resume the sector erase operation, the sys-

tem must write the Erase Resume command.

Further writes of the Resume command are ig-

nored. Another Erase Suspend command can

be written after the chip resumes erasing.

Figure 5. Erase Operation

START

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Data = FFh?

Yes

Erasure Completed

Embedded
Erase
algorithm
in progress

Notes:
1. See

Table 14, on page 29

for erase command

sequence.

2. See the section on DQ3 for information on the

sector erase timer.

November 15, 2004

Am29LV320D

Command Definitions

Table 14. Am29LV320D Command Definitions

Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.

PD = Data to be programmed at location PA. Data latches on
the rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode)
or erased. Address bits A20A12 uniquely select any sector.

Notes:

1. See

Table 1

for description of bus operations.

2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

4. Data bits DQ15DQ8 are don't care in command sequences,

except for RD and PD.

5. Unless otherwise noted, address bits A20A11 are don't cares.
6. No unlock or command cycles required when device is in read

mode.

7. The Reset command is required to return to the read mode (or

to the erase-suspend-read mode if previously in Erase Suspend)

when a device is in the autoselect mode, or if DQ5 goes high

(while the device is providing status information).

8. The fourth cycle of the autoselect command sequence is a read

cycle. Data bits DQ15DQ8 are don't care. See the Autoselect

Command Sequence section for more information.

9. The data is 99h for factory locked and 19h for not factory

locked.

10. The data is 00h for an unprotected sector and 01h for a

protected sector.

11. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

12. The Unlock Bypass Reset command is required to return to the

read mode when the device is in the unlock bypass mode.

13. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase

operation.

14. The Erase Resume command is valid only during the Erase

Suspend mode.

15. Command is valid when device is ready to read array data or

when device is in autoselect mode.

Command

Sequence

(Note 1)

c
l
e

Bus Cycles (Notes 25)

First

Second Third

Fourth Fifth Sixth

Addr Data Addr Data

Addr

Data Addr

Data

Addr Data Addr Data

Read (Note 6)

Reset (Note 7)

XXX

s
e
l
e
ct

(

t
e

8)

Manufacturer ID

Word

555

2AA

555

X00

Byte

AAA

555

AAA

Device ID

Word

555

2AA

555

X01

(see

Table 6

)

Byte

AAA

555

AAA

X02

SecSi Sector
Factory Protect
(Note 9)

Word

555

2AA

555

X03

99/19

Byte

AAA

555

AAA

X06

Sector Protect
Verify (Note 10)

Word

555

2AA

555

(SA)X0

00/01

Byte

AAA

555

AAA

(SA)X0

Enter

SecSiTM Sector

Region

Word

555

2AA

555

Byte

AAA

555

AAA

Exit

SecSi Sector

Region

Word

555

2AA

555

XXX

Byte

AAA

555

AAA

Program

Word

555

2AA

555

Byte

AAA

555

AAA

Unlock Bypass

Word

555

2AA

555

Byte

AAA

555

AAA

Unlock Bypass Program (Note
11)

XXX

Unlock Bypass Reset (Note 12)

XXX

Chip Erase

Word

555

2AA

555

2AA

555

Byte

AAA

555

AAA

555

AAA

Sector Erase

Word

555

2AA

555

2AA

Byte

AAA

555

AAA

555

Erase Suspend (Note 13)

XXX

Erase Resume (Note 14)

XXX

CFI Query (Note 15)

Word

Byte

Am29LV320D

November 15, 2004

WRITE OPERATION STATUS

The device provides several bits to determine

the status of a program or erase operation:

DQ2, DQ3, DQ5, DQ6, and DQ7.

Table 15, on

page 33

and the following subsections describe

the function of these bits. DQ7 and DQ6 each

offer a method for determining whether a pro-

gram or erase operation is complete or in

progress. The device also provides a hard-

ware-based output signal, RY/BY#, to deter-

mine whether an Embedded Program or Erase

operation is in progress or is completed.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the

host system whether an Embedded Program or

Erase algorithm is in progress or completed, or

whether a device is in Erase Suspend. Data#

Polling is valid after the rising edge of the final

WE# pulse in the command sequence.

During the Embedded Program algorithm, the

device outputs on DQ7 the complement of the

datum programmed to DQ7. This DQ7 status

also applies to programming during Erase Sus-

pend. When the Embedded Program algorithm

is complete, the device outputs the datum pro-

grammed to DQ7. The system must provide the

program address to read valid status informa-

tion on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active

for approximately 1 µs, then the device returns

to the read mode.
During the Embedded Erase algorithm, Data#

Polling produces a "0" on DQ7. When the Em-

bedded Erase algorithm is complete, or if the

device enters the Erase Suspend mode, Data#

Polling produces a "1" on DQ7. The system

must provide an address within any of the sec-

tors selected for erasure to read valid status in-

formation on DQ7.

After an erase command sequence is written, if

all sectors selected for erasing are protected,

Data# Polling on DQ7 is active for approxi-

mately 100 µs, then the device returns to the

read mode. If not all selected sectors are pro-

tected, the Embedded Erase algorithm erases

the unprotected sectors, and ignores the se-

lected sectors that are protected. However, if

the system reads DQ7 at an address within a

protected sector, the status may not be valid.
Just prior to the completion of an Embedded

Program or Erase operation, DQ7 may change

asynchronously with DQ0DQ6 while Output

Enable (OE#) is asserted low. That is, the de-

vice may change from providing status infor-

mation to valid data on DQ7. Depending on

when the system samples the DQ7 output, it

may read the status or valid data. Even if the

device completes the program or erase opera-

tion and DQ7 contains valid data, the data out-

puts on DQ0DQ6 may be still invalid. Valid

data on DQ0DQ7 appears on successive read

cycles.

Table 15, on page 33

shows the outputs for

Data# Polling on DQ7.

Figure 6, on page 30

shows the Data# Polling algorithm.

Figure 20,

on page 44

in the AC Characteristics section

shows the Data# Polling timing diagram.

Figure 6. Data# Polling Algorithm

DQ7 = Data?

Yes

DQ5 = 1?

Yes

FAIL

PASS

Read DQ7DQ0

Addr = VA

Read DQ7DQ0

Addr = VA

DQ7 = Data?

START

Notes:
1. VA = Valid address for programming. During a

sector erase operation, a valid address is any
sector address within the sector being erased.
During chip erase, a valid address is any
non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = "1"

because DQ7 may change simultaneously with
DQ5.

November 15, 2004

Am29LV320D

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output

pin which indicates whether an Embedded Al-

gorithm is in progress or complete. The RY/BY#

status is valid after the rising edge of the final

WE# pulse in the command sequence. Since

RY/BY# is an open-drain output, several

RY/BY# pins can be tied together in parallel

with a pull-up resistor to V

If the output is low (Busy), the device is ac-

tively erasing or programming. (This includes

programming in the Erase Suspend mode.) If

the output is high (Ready), the device is in the

read mode, the standby mode, or in the

erase-suspend-read m ode.

Table 15, on

page 33

shows the outputs for RY/BY#.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Em-

bedded Program or Erase algorithm is in

progress or complete, or whether the device

entered the Erase Suspend mode. Toggle Bit I

may be read at any address, and is valid after

the rising edge of the final WE# pulse in the

command sequence (prior to the program or

erase operation), and during the sector erase

time-out.

During an Embedded Program or Erase algo-

rithm operation, successive read cycles to any

address cause DQ6 to toggle. The system may

use either OE# or CE# to control the read cy-

cles. When the operation is complete, DQ6

stops toggling.
After an erase command sequence is written, if

all sectors selected for erasing are protected,

DQ6 toggles for approximately 100 µs, then re-

turns to reading array data. If not all selected

sectors are protected, the Embedded Erase al-

gorithm erases the unprotected sectors, and ig-

nores the selected sectors that are protected.

The system can use DQ6 and DQ2 together to

determine whether a sector is actively erasing

or is erase-suspended. When the device is ac-

tively erasing (that is, the Embedded Erase al-

gorithm is in progress), DQ6 toggles. When the

device enters the Erase Suspend mode, DQ6

stops toggling. However, the system must also

use DQ2 to determine which sectors are eras-

ing or erase-suspended. Alternatively, the sys-

tem can use DQ7 (see the subsection on

"DQ7:

Data# Polling" on page 30

If a program address falls within a protected

sector, DQ6 toggles for approximately 1 µs

after the program command sequence is writ-

ten, then returns to reading array data.

D Q 6 als o to ggl es du rin g the era se-su s-

pend-program mode, and stops toggling once

the Embedded Program algorithm is complete.

Table 15, on page 33

shows the outputs for

Toggle Bit I on DQ6.

Figure 7, on page 31

shows the toggle bit algorithm.

Figure 21, on

page 45

in the

"AC Characteristics"

section

shows the toggle bit timing diagrams.

Figure

22, on page 45

shows the differences between

DQ2 and DQ6 in graphical form. See also the

subsection on DQ2: Toggle Bit II.

Figure 7. Toggle Bit Algorithm

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle?

Program/Erase

Operation Not

Complete, Write
Reset Command

Program/Erase

Operation Complete

Read DQ7DQ0

Toggle Bit

= Toggle?

Read DQ7DQ0

Twice

Read DQ7DQ0

Note: The system should recheck the toggle bit
even if DQ5 = "1" because the toggle bit may stop
toggling as DQ5 changes to "1." See the subsections
on DQ6 and DQ2 for more information.

Am29LV320D

November 15, 2004

DQ2: Toggle Bit II

The "Toggle Bit II" on DQ2, when used with

DQ6, indicates whether a particular sector is

actively erasing (that is, the Embedded Erase

algorithm is in progress), or whether that sec-

tor is erase-suspended. Toggle Bit II is valid

after the rising edge of the final WE# pulse in

the command sequence.
DQ2 toggles when the system reads at ad-

dresses within those sectors that were selected

for erasure. (The system may use either OE#

or CE# to control the read cycles.) But DQ2

cannot distinguish whether the sector is ac-

tively erasing or is erase-suspended. DQ6, by

comparison, indicates whether the device is ac-

tively erasing, or is in Erase Suspend, but can-

not distinguish which sectors are selected for

erasure. Thus, both status bits are required for

sector and mode information. Refer to

Table 15,

on page 33

to compare outputs for DQ2 and

DQ6.

Figure 7, on page 31

shows the toggle bit algo-

rithm in flowchart form, and the section

"DQ2:

Toggle Bit II" on page 32

explains the algo-

rithm. See also the DQ6: Toggle Bit I subsec-

tion.

Figure 21, on page 45

shows the toggle bit

timing diagram.

Figure 22, on page 45

shows

the differences between DQ2 and DQ6 in

graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to

Figure 7, on page 31

for the following

discussion. Whenever the system initially be-

gins reading toggle bit status, it must read

DQ7DQ0 at least twice in a row to determine

whether a toggle bit is toggling. Typically, the

system would note and store the value of the

toggle bit after the first read. After the second

read, the system would compare the new value

of the toggle bit with the first. If the toggle bit

is not toggling, the device completed the pro-

gram or erase operation. The system can read

array data on DQ7DQ0 on the following read

cycle.

However, if after the initial two read cycles, the

system determines that the toggle bit is still

toggling, the system also should note whether

the value of DQ5 is high (see the section on

DQ5). If it is, the system should then deter-

mine again whether the toggle bit is toggling,

since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no

longer toggling, the device successfully com-

pleted the program or erase operation. If it is

still toggling, the device did not completed the

operation successfully, and the system must

write the reset command to return to reading

array data.

The remaining scenario is that the system ini-

tially determines that the toggle bit is toggling

and DQ5 has not gone high. The system may

continue to monitor the toggle bit and DQ5

through successive read cycles, determining

the status as described in the previous para-

graph. Alternatively, it may choose to perform

other system tasks. In this case, the system

must start at the beginning of the algorithm

when it returns to determine the status of the

operation (top of

Figure 7, on page 31

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase

time exceeded a specified internal pulse count

limit. Under these conditions DQ5 produces a

"1," indicating that the program or erase cycle

was not successfully completed.

The device may output a "1" on DQ5 if the sys-

tem tries to program a "1" to a location that

was previously programmed to "0." Only an

erase operation can change a "0" back to a

"1." Under this condition, the device halts the

operation, and when the timing limit is ex-

ceeded, DQ5 produces a "1."
Under both these conditions, the system must

write the reset command to return to the read

mode (or to the erase-suspend-read mode if

the device was previously in the erase-sus-

pend-program mode).

DQ3: Sector Erase Timer

After writing a sector erase command se-

quence, the system may read DQ3 to deter-

mine whether or not erasure started. (The

sector erase timer does not apply to the chip

erase command.) If additional sectors are se-

lected for erasure, the entire time-out also ap-

p lies af te r e ach ad ditiona l s ector e rase

command. When the time-out period is com-

plete, DQ3 switches from a "0" to a "1." If the

time between additional sector erase com-

mands from the system can be assumed to be

less than 50 µs, the system need not monitor

DQ3. See also the Sector Erase Command Se-

quence section.

After the sector erase command is written, the

system should read the status of DQ7 (Data#

Polling) or DQ6 (Toggle Bit I) to ensure that the

device accepted the command sequence, and

then read DQ3. If DQ3 is "1," the Embedded

Erase algorithm started; all further commands

(except Erase Suspend) are ignored until the

erase operation is complete. If DQ3 is "0," the

Am29LV320D

November 15, 2004

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages. . . . . . . . . . 65°C to +150°C
Ambient Temperature

with Power Applied. . . . . . . . 65°C to +125°C
Voltage with Respect to Ground

(Note 1) . . . . . . . . . . 0.5 V to +4.0 V

A9, OE#, RESET#,

and WP#/ACC (Note 2). . 0.5 V to +12.5 V
All other pins (Note 1) 0.5 V to V

+0.5 V

Output Short Circuit Current (Note 3). 200 mA

Notes:
1. Minimum DC voltage on input or I/O pins is 0.5

V. During voltage transitions, input or I/O pins
may overshoot V

to 2.0 V for periods of up to

20 ns. Maximum DC voltage on input or I/O pins
is V

+0.5 V. See

Figure 8, on page 34

. During

voltage transitions, input or I/O pins may
overshoot to V

+2.0 V for periods up to 20 ns.

See

Figure 9, on page 34

2. Minimum DC input voltage on pins A9, OE#,

RESET#, and WP#/ACC is 0.5 V. During voltage
transitions, A9, OE#, WP#/ACC, and RESET#
may overshoot V

to 2.0 V for periods of up to

20 ns. See

Figure 8, on page 34

. Maximum DC

input voltage on pin A9 is +12.5 V which may
overshoot to +14.0 V for periods up to 20 ns.
Maximum DC input voltage on WP#/ACC is +9.5
V which may overshoot to +12.0 V for periods up
to 20 ns.

3. No more than one output may be shorted to

ground at a time. Duration of the short circuit
should not be greater than one second.

Stresses above those listed under "A bsolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only; functional
operation of the device at these or any other
conditions above those indicated in the operational
sections of this data sheet is not implied. Exposure
of the device to absolute maximum rating conditions
for extended periods may affect device reliability.

OPERATING RANGES

Industrial (I) Devices
Ambient Temperature (T

). . . . 40°C to +85°C

Supply Voltages

for all devices . . . . . . . . . . 2.7 V to 3.6 V

Operating ranges define those limits between which the
functionality of the device is guaranteed.

20 ns

+0.8

0.5

20 ns

2.0

Figure 8. Maximum Negative

Overshoot Waveform

Figure 9. Maximum Positive

Overshoot Waveform

20 ns

+2.0

+0.5

20 ns

2.0 V

November 15, 2004

Am29LV320D

DC CHARACTERISTICS
CMOS Compatible

Notes:
1. The I

current listed is typically less than 2 mA/MHz, with OE# at V

2. Maximum I

specifications are tested with V

= V

max.

3. I

active while Embedded Erase or Embedded Program is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t

ACC

+ 30 ns. Typical sleep

mode current is 200 nA.

5. Not 100% tested.

Paramet

Symbol

Parameter Description

Test Conditions

Min

Typ

Max

Unit

Input Load Current

= V

to V

= V

max

±3.0

µA

LIT

A9 Input Load Current

= V

CC max

; A9 = 12.5 V

µA

RESET# Input Load Current

= V

CC max

; RESET# = 12.5 V

µA

Output Leakage Current

OUT

= V

to V

= V

CC max

±1.0

µA

CC1

Active Read Current

(Notes 1, 2)

CE# = V

IL,

OE#

Byte Mode

5 MHz

1 MHz

CE# = V

IL,

OE#

Word Mode

5 MHz

1 MHz

CC2

Active Write Current (Notes 2, 3) CE# = V

IL,

OE#

, WE# = V

CC3

Standby Current (Note 2)

CE#, RESET# = V

± 0.3 V

0.2

µA

CC4

Reset Current (Note 2)

RESET# = V

± 0.3 V

0.2

µA

CC5

Automatic Sleep Mode (Notes 2, 4)

= V

± 0.3 V;

= V

± 0.3 V

0.2

µA

Input Low Voltage

0.5

0.8

Input High Voltage

0.7 x V

+ 0.3

Voltage for WP#/ACC Sector
Protect/Unprotect and Program
Acceleration

= 3.0 V ± 10%

11.5

12.5

Voltage for Autoselect and Temporary
Sector Unprotect

= 3.0 V ± 10%

11.5

12.5

Output Low Voltage

= 4.0 mA, V

= V

CC min

0.45

OH1

Output High Voltage

= 2.0 mA, V

= V

CC min

0.85

OH2

= 100 µA, V

= V

CC min

0.4

LKO

Low V

Lock-Out Voltage (Note 5)

2.3

2.5

Am29LV320D

November 15, 2004

ERASE AND PROGRAMMING PERFORMANCE

Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V

, 1,000,000 cycles.

Additionally, programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V

= 2.7 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since

most bytes program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before

erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program

command. See

Table 14, on page 29

for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Note: Includes all pins except V

. Test conditions: V

= 3.0 V, one pin at a time.

TSOP AND BGA PACKAGE CAPACITANCE

Notes:
1. Sampled, not 100% tested.
2. Test conditions T

= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter

Typ (Note 1) Max (Note 2)

Unit

Comments

Sector Erase Time

0.7

sec

Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time

sec

Byte Program Time

300

µs

Excludes system level

overhead (Note 5)

Word Program Time

360

µs

Accelerated Byte/Word Program Time

210

µs

Chip Program Time
(Note 3)

Byte Mode

108

sec

Word Mode

Description

Min

Max

Input voltage with respect to V

on all pins except I/O pins

(including A9, OE#, and RESET#)

1.0 V

12.5 V

Input voltage with respect to V

on all I/O pins

1.0 V

+ 1.0 V

Current

100 mA

+100 mA

Parameter Symbol

Parameter Description

Test Setup

Typ

Max

Unit

Input Capacitance

= 0

TSOP

7.5

Fine-pitch BGA

4.2

5.0

OUT

Output Capacitance

OUT

= 0

TSOP

8.5

Fine-pitch BGA

5.4

6.5

IN2

Control Pin Capacitance

= 0

TSOP

7.5

Fine-pitch BGA

3.9

4.7

Parameter Description

Test Conditions

Min

Unit

Minimum Pattern Data Retention Time

150°C

Years

125°C

Years

November 15, 2004

Am29LV320D

REVISION SUMMARY
Revision A (November 1, 2000)

Initial release.

Revision A+1 (January 23, 2001)

Ordering Information
Corrected FBGA part number table to include

bottom boot part numbers.

Revision A+2 (February 1, 2001)

Connection Diagrams
Corrected FBGA ball matrix.

Revision A+3 (July 2, 2001)

Global
Changed data sheet status from Advance Infor-

mation to Preliminary.

Table 3

, Top Boot SecSi

Sector Addresses

Corrected sector block size for SA60SA62 to

3x64.
Sector/Sector Block Protection and

Unprotection
Noted that sectors are erased in parallel.

SecSi

Sector (Secured Silicon) Flash Memory

Region
Noted changes for upcoming versions of these

devices: reduced SecSi Sector size, different

ESN location for top boot devices, and deletion

of SecSi Sector erase functionality. Current ver-

sions of these devices remain unaffected.

Revision B (July 12, 2002)

Global
Deleted Preliminary status from document.
Ordering Information
Deleted burn-in option.

Table 1

, Am29LV320D Device Bus Operations

In the legend, corrected V

maximum voltage

to 12.5 V.

SecSi

Sector (Secured Silicon) Flash Memory

Region
Added description of SecSi Sector protection

verification.

Autoselect Command Sequence
Clarified description of function.

Table 14

, Am29LV320D Command Definitions

Corrected autoselect codes for SecSi Sector

Factory Protect.
Erase and Program Operations table
Corrected to indicate t

BUSY

specification is a

maximum value.

Revision B+1 (July 30, 2002)

Figure 3

, SecSi Sector Protect Verify

Deleted fifth block in flowchart and modified

text in fourth block.

Revision C (October 25, 2002)

Distinctive Characteristics
Changed endurance from "write" to "erase" cy-

cles.

Connection Diagrams
Deleted ultrasonic reference and added pack-

age types to special package handling text.

Ordering Information
Added commercial temperature range and re-

moved extended temperature range.
SecSi Sector Flash Memory Region
Customer Lockable subsection: Deleted refer-

ence to alternate method of sector protection.

Command Definitions
Noted the following:

Autoselect, SecSi Sector, and CFI functions are

not available during a program or erase opera-

tion.
ACC and unlock bypass modes are not available

when the SecSi Sector is enabled.

Writing incorrect data or commands may place

the device in an unknown state. A reset com-

mand is then required.
AC Characteristics
Read-only Operations; Word/Byte Configura-

tion: Changed t

and t

FLQZ

to 16 ns for all

speed options.
DC Characteristics
Deleted I

ACC

and added I

specifications from

table.

TSOP, SO, and BGA Package Capacitance
Added BGA capacitance to table.

Am29LV320D

November 15, 2004

Revision C+1 (February 16, 2003)

Distinctive Characteristics

Added reference to MirrorBit in Secured Silicon
section.
Added Sector Architecture section.

SecSi Sector Flash Memory Region
Referenced MirrorBit for an example in last sen-

tence of first paragraph.

Command Definitions
Changed the first address of the Unlock Bypass

Reset from BA to XXX.

Erase and Programming Performance
Corrected the Sector Erase Time Typical to 0.7.

Revision C+2 (April 4, 2003)

Distinctive Characteristics
Clarified reference to MirrorBit in Secured Sili-

con section.

SecSi Sector Flash Memory Region
Clarified reference of MirrorBit for an example

in last sentence of first paragraph.

Revision C+3 (September 19, 2003)

Valid Combinations
Added the 90R package to table.

Revision C+4 (April 5, 2004)

Command Definitions
Changed first address data for Erase Sus-

pend/Resume from BA to XXX.

Revision C+5 (June 4, 2004)

Ordering Information
Added Lead-free (Pb-free) options to the tem-

perature ranges breakout table and valid com-

binations table.

Product Selector Guide
Added 90R voltage range.

Revision C+6 (November 15, 2004)

Global
Added Colophon

Updated Trademarks

Added reference links

Ordering Information
Added Automotive In-Cabin temperature range

and associated part numbers in the valid com-

bination table.

Erase and Programming Performance
Updated Chip Erase Time

AC Characteristics
Added t

line to Figure 15.

Erase and Program Operations

C o r r e c t e d S e c to r E ra s e O p e ra t i o n t i m e
(

WHWH2)

Alternate CE# Control Erase and Program Operations

C o r r e c t e d S e c to r E ra s e O p e ra t i o n t i m e
(

WHWH2)

Command Definitions
Update text in Sector Erase Command Se-

quence paragraph.

November 15, 2004

Am29LV320D

Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, includ-
ing without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, de-
veloped and manufactured as contemplated (1) for

any

use

that includes

fatal risks or dangers that, unless extremely high

safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical
damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport
control, medical life support system, missile launch control in weapon system), or (2)

for any use where chance of failure is

intolerable

(i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable

you and/or

any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating
safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions. If any products described in this document represent goods or technologies
subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan

, the US Export Adminis-

tration Regulations or the applicable laws of any other country,

the prior authorization by

the respective government entity

will

be required for export of those products.

Trademarks

-2004

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective compa-
nies
.

Document Outline

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Document Outline

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