A43E26161
1M X 16 Bit X 4 Banks Low Power Synchronous DRAM
(December, 2004, Version 1.0)
AMIC Technology, Corp.
Document Title
1M X 16 Bit X 4 Banks Low Power Synchronous DRAM
Revision History
Rev. No. History Issue
Date Remark
0.0 Initial
issue
September 13, 2004 Preliminary
1.0
Final version release
December 15, 2004
Final
A43E26161
1M X 16 Bit X 4 Banks Low Power Synchronous DRAM
(December, 2004, Version 1.0)
1
AMIC Technology, Corp.
Features
Low power supply
- VDD: 1.8V VDDQ : 1.8V
LVCMOS compatible with multiplexed address
Four banks / Pulse
RAS
MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1,2,4,8 & full page)
-
Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Deep Power Down Mode
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
Self refresh with programmable refresh period through
EMRS cycle
Programmable Power Reduction Feature by partial
array activation during Self-refresh through EMRS
cycle
Industrial operating temperature range: -25C to +85C
for -U series.
Available in 54 Balls CSP (8mm X 8mm) and 54-pin
TSOP(II) packages.
Clock Frequency (max) : 105MHz @ CL=3 (-95)
General Description
The A43E26161 is 67,108,864 bits Low Power
synchronous high data rate Dynamic RAM organized as 4
X 1,048,576 words by 16 bits, fabricated with AMIC's high
performance CMOS technology. Synchronous design
allows precise cycle control with the use of system clock.
I/O transactions are possible on every clock cycle. Range
of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high
bandwidth, high performance memory system
applications.
Pin Configuration
54 Balls CSP (8 mm x 8 mm)
Top View
54 Ball (8X8) CSP
1 2 3
7
8
9
A VSS
DQ
15
VSSQ
VDDQ
DQ
0
VDD
B DQ
14
DQ
13
VDDQ
VSSQ
DQ
2
DQ
1
C DQ
12
DQ
11
VSSQ
VDDQ
DQ
4
DQ
3
D DQ
10
DQ
9
VDDQ
VSSQ
DQ
6
DQ
5
E DQ
8
NC
VSS
VDD
LDQM
DQ
7
F UDQM
CLK CKE
CAS
RAS
WE
G NC A11 A9 BA0
BA1
CS
H
A8
A7
A6
A0
A1
A10
J VSS A5
A4
A3
A2
VDD
A43E26161
(December, 2004, Version 1.0)
2
AMIC Technology, Corp.
Pin Configuration (continued)
54 TSOP (II)
A43E26161
54 53 52 51 50 49 48 47 46 45
43
44
42 41 40 39 38 37 36 35 34 33 32 31 30
1
2
3
4 5
6
7
8
9 10
12
11
13 14 15 16 17 18 19 20 21 22 23 24 25
VSS
DQ
15
VSS
Q
DQ
14
DQ
13
VDDQ
DQ
12
DQ
11
VSSQ
DQ
10
DQ
9
VDDQ
DQ
8
VSS
UD
Q
M
CL
K
CK
E
NC
A9
A8
A7
A6
A5
A4
VSS
VDD
DQ
0
VDDQ
DQ
1
DQ
2
VS
SQ
DQ
3
DQ
4
VDDQ
DQ
5
DQ
6
V
SSQ
DQ
7
VD
D
LD
Q
M
WE
CAS
RAS
CS
A1
0
/
A
P
BS
1
BS
0
A0
A1
A2
26 27
28
29
A3
VDD
A1
1
NC
Block Diagram
Bank Select
Row Buff
er
Re
fr
e
s
h
C
o
u
n
te
r
A
ddr
es
s Re
g
i
s
t
e
r
Ro
w D
e
c
o
d
e
r
Col
u
m
n
B
u
ffe
r
LCBR
LRAS
CLK
ADD
Timing Register
Data Input Register
1M X 16
Sen
s
e A
M
P
Column Decoder
Latency & Burst Length
Programming Register
LRAS
LCAS
LRAS
LCBR
LWE
LWCBR
DQM
CLK
CKE
CS
RAS
CAS
WE
DQM
I/
O
C
o
n
t
r
o
l
O
u
tp
u
t
B
u
ff
e
r
LWE
DQM
DQi
1M X 16
1M X 16
1M X 16
A43E26161
(December, 2004, Version 1.0)
3
AMIC Technology, Corp.
Pin Descriptions
Symbol Name
Description
CLK
System Clock
Active on the positive going edge to sample all inputs.
CS
Chip Select
Disables or Enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM
CKE Clock
Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock + tss prior to new command.
Disable input buffers for power down in standby.
A0~A11 Address
Row / Column addresses are multiplexed on the same pins.
Row address : RA0~RA11, Column address: CA0~CA7
BS0, BS1
Bank Select Address
Selects bank to be activated during row address latch time.
Selects band for read/write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column Address
Strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write Enable
Enables write operation and Row precharge.
L(U)DQM
Data Input/Output
Mask
Makes data output Hi-Z, t SHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
DQ
0-15
Data Input/Output
Data inputs/outputs are multiplexed on the same pins.
VDD/VSS
Power
Supply/Ground
Power Supply: +1.7V ~ 1.95V/Ground
VDDQ/VSSQ
Data Output
Power/Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
NC/RFU No
Connection
A43E26161
(December, 2004, Version 1.0)
4
AMIC Technology, Corp.
Absolute Maximum Ratings*
Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +2.6V
Voltage on VDD supply relative to VSS (VDD, VDDQ )
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to + 2.6V
Storage Temperature (T
STG
) . . . . . . . . . . -55
C to +150
C
Soldering Temperature X Time (T
SLODER
) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
C X 10sec
Power Dissipation (P
D
) . . . . . . . . . . . . . . . . . . . . . . . . 0.8W
Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . . 50mA
*Comments
Permanent device damage may occur if "Absolute
Maximum Ratings" are exceeded.
Functional operation should be restricted to recommended
operating condition.
Exposure to higher than recommended voltage for
extended periods of time could affect device reliability.
Capacitance (T
A
=25
C, f=1MHz)
Parameter Symbol
Condition
Min
Max
Unit
Input Capacitance
CI1
A0 to A11, BS0, BS1
2.0
4.0
pF
CI2
CLK, CKE,
CS
,
RAS
,
CAS
,
WE
, DQM
2.0 4.0 pF
Data Input/Output Capacitance
CI/O
DQ0 to DQ15
3.5
6.0
pF
DC Electrical Characteristics
Recommend operating conditions (Voltage referenced to VSS = 0V, T
A
= 0C to +70C or T
A
= -25C to +85C)
Parameter Symbol
Min
Typ
Max
Unit
Note
Supply Voltage
VDD
1.7
1.8
1.95
V
DQ Supply Voltage
VDDQ
1.7
1.8
1.95
V
Input High Voltage
V
IH
0.8*VDDQ - VDDQ+0.3 V
Input Low Voltage
V
IL
-0.3 - 0.3 V Note
1
Output High Voltage
V
OH
VDDQ - 0.2
-
-
V
I
OH
= -0.1mA
Output Low Voltage
V
OL
- - 0.2 V
I
OL
= 0.1mA
Input Leakage Current
I
IL
-1 - 1
A
Note 2
Output Leakage Current
I
OL
-1.5 - 1.5
A
Note 3
Output Loading Condition
See Fig. 1 (Page 6)
Note:
1. V
IL
(min) = -1.5V AC (pulse width
5ns).
2. Any input 0V
VIN
VDD + 0.3V, all other pins are not under test = 0V
3. Dout is disabled, 0V
Vout
VDD
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