1
Features
Low Voltage and Standard Voltage Operation
5.0 (V
CC
= 4.5V to 5.5V)
2.7 (V
CC
= 2.7V to 5.5V)
2.5 (V
CC
= 2.5V to 5.5V)
1.8 (V
CC
= 1.8V to 5.5V)
Internally Organized 2048 x 8 (16K)
2-Wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
100 KHz (1.8V, 2.5V, 2.7V) and 400 KHz (5V) Compatibility
Write Protect Pin for Hardware Data Protection
Cascadable Feature Allows for Extended Densities
16-Byte Page Write Mode
Partial Page Writes Are Allowed
Self-Timed Write Cycle (10 ms max)
High Reliability
Endurance: 1 Million Write Cycles
Data Retention: 100 Years
ESD Protection: >3,000V
Automotive Grade and Extended Temperature Devices Available
8-Pin JEDEC SOIC and 8-Pin PDIP Packages
Description
The AT24C164 provides 16,384 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 2048 words of 8 bits each. The device's
cascadable feature allows up to eight devices to share a common 2-wire bus. The
device is optimized for use in many industrial and commercial applications where low
power and low voltage operation are essential. The AT24C164 is available in space
saving 8-pin PDIP and 8-pin SOIC packages and is accessed via a 2-wire serial inter-
face. In addition, this device is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V),
2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
2-Wire Serial
EEPROM
16K (2048 x 8)
AT24C164
Rev. 0105D07/98
2-Wire, 16K
Serial EEPROM
Pin Configurations
Pin Name
Function
A0 to A2
Address Inputs
SDA
Serial Data
SCL
Serial Clock Input
WP
Write Protect
8-Pin PDIP
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
8-Pin SOIC
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
AT24C164
2
Block Diagram
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive
edge clock data into each EEPROM device and negative
edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for
serial data transfer. This pin is open-drain driven and may
be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE SELECT (A2, A1, A0): The A2, A1 and A0 pins
are device address inputs that may be hardwired or actively
driven to V
DD
or V
SS
. These inputs allow the selection for
one of eight possible devices sharing a common bus. The
AT24C164 can be made compatible with the AT24C16 by
tying A2, A1 and A0 to V
SS
. Device addressing is discussed
in detail in the device addressing section.
WRITE PROTECT (WP): The write protect input, when tied
low to GND, allows normal write operations.
Memory Organization
The AT24C164 is internally organized with 256 pages of
8 bytes each. Random word addressing requires an 11 bit
data word address.
Absolute Maximum Ratings*
Operating Temperature .................................. -55
C to +125
C
*NOTICE:
Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature ..................................... -65
C to +150
C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage........................................... 6.25V
DC Output Current........................................................ 5.0 mA
WP
AT24C164
3
Note:
1. This parameter is characterized and is not 100% tested.
Note:
1. V
IL
min and V
IH
max are reference only and are not tested.
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25
C, f = 1.0 MHz, V
CC
= +1.8V.
Symbol
Test Condition
Max
Units
Conditions
C
I/O
Input/Output Capacitance (SDA)
8
pF
V
I/O
= 0V
C
IN
Input Capacitance (A
0
, A
1
, A
2
, SCL)
6
pF
V
IN
= 0V
DC Characteristics
Applicable over recommended operating range from: T
AI
= -40
C to +85
C, V
CC
= +1.8V to +5.5V, T
AC
= 0
C to +70
C,
V
CC
= +1.8V to +5.5V (unless otherwise noted).
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
V
CC1
Supply Voltage
1.8
5.5
V
V
CC2
Supply Voltage
2.5
5.5
V
V
CC3
Supply Voltage
2.7
5.5
V
V
CC4
Supply Voltage
4.5
5.5
V
I
CC
Standby Current V
CC
= 5.0V
READ at 100 KHz
0.4
1.0
mA
I
CC
Standby Current V
CC
= 5.0V
WRITE at 100 KHz
2.0
3.0
mA
I
SB1
Standby Current V
CC
= 1.8V
V
IN
= V
CC
or V
SS
0.6
3.0
A
I
SB2
Standby Current V
CC
= 2.5V
V
IN
= V
CC
or V
SS
1.4
4.0
A
I
SB3
Standby Current V
CC
= 2.7V
V
IN
= V
CC
or V
SS
1.6
4.0
A
I
SB4
Standby Current V
CC
= 5.0V
V
IN
= V
CC
or V
SS
8.0
18.0
A
I
LI
Input Leakage Current
V
IN
= V
CC
or V
SS
0.10
3.0
A
I
LO
Output Leakage Current
V
OUT =
V
CC
or V
SS
0.05
3.0
A
V
IL
Input Low Level
(1)
-0.6
V
CC
x 0.3
V
V
IH
Input High Level
(1)
V
CC
x 0.7
V
CC
+ 0.5
V
V
OL2
Output Low Level V
CC
= 3.0V
I
OL
= 2.1 mA
0.4
V
V
OL1
Output Low Level V
CC
= 1.8V
I
OL
= 0.15 mA
0.2
V
AT24C164
4
Notes:
1. This parameter is characterized and is not 100% tested.
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is nor-
mally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL
high periods will indicate a start or stop condition as
defined below.
START CONDITION: A high-to-low transition of SDA with
SCL high is a start condition which must precede any other
command (refer to Start and Stop Definition timing dia-
gram).
STOP CONDITION: A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are seri-
ally transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock
cycle.
STANDBY MODE: The AT24C164 features a low power
standby mode which is enabled: a) upon power-up and b)
after the receipt of the STOP bit and the completion of any
internal operations.
MEMORY RESET: After an interruption in protocol, power
loss or system reset, the AT24C164 can be reset by follow-
ing these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle
while SCL is high and then (c) create a start condition as
SDA is high.
AC Characteristics
Applicable over recommended operating range from T
A
= -40
C to +85
C, V
CC
= +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted).
Symbol
Parameter
2.7-, 2.5-, 1.8-volt
5.0-volt
Units
Min
Max
Min
Max
f
SCL
Clock Frequency, SCL
100
400
KHz
t
LOW
Clock Pulse Width Low
4.7
1.2
s
t
HIGH
Clock Pulse Width High
4.0
0.6
s
t
I
Noise Suppression Time
(1)
100
50
ns
t
AA
Clock Low to Data Out Valid
0.1
4.5
0.1
0.9
s
t
BUF
Time the bus must be free before a new
transmission can start
(1)
4.7
1.2
s
t
HD.STA
Start Hold Time
4.0
0.6
s
t
SU.STA
Start Set-up Time
4.7
0.6
s
t
HD.DAT
Data In Hold Time
0
0
s
t
SU.DAT
Data In Set-up Time
200
100
ns
t
R
Inputs Rise Time
(1)
1.0
0.3
s
t
F
Inputs Fall Time
(1)
300
300
ns
t
SU.STO
Stop Set-up Time
4.7
0.6
s
t
DH
Data Out Hold Time
100
50
ns
t
WR
Write Cycle Time
10
10
ms
Endurance
(1)
5.0V, 25
C, Page Mode
1M
1M
Write
cycles
AT24C164
5
Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
Note:
1.
The write cycle time t
WR
is the time from a valid stop condition of a write sequence to the end of the internal clear/write
cycle.
(1)
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