AT27C080
1
0360F-B7/97
8-Megabit
(1M x 8)
UV Erasable
CMOS EPROM
AT27C080
Features
Fast Read Access Time - 90 ns
Low Power CMOS Operation
- 100
A max. Standby
- 40 mA max. Active at 5 MHz
JEDEC Standard Packages
- 32 Lead PLCC
- 32-Lead 600-mil PDIP and Cerdip
- 32-Lead 450-mil SOIC (SOP)
- 32-Lead TSOP
5V
10% Supply
High-Reliability CMOS Technology
- 2,000V ESD Protection
- 200 mA Latchup Immunity
Rapid
TM
Programming Algorithm - 50
s/byte (typical)
CMOS and TTL Compatible Inputs and Outputs
Integrated Product Identification Code
Industrial and Commercial Temperature Ranges
Description
The AT27C080 chip is a low-power, high-performance 8,388,608-bit ultraviolet eras-
able programmable read only memory (EPROM) organized as 1M by 8 bits. The
AT27C080 requires only one 5V power supply in normal read mode operation. Any
byte can be accessed in less than 90 ns, eliminating the need for speed reducing
WAIT states on high-performance microprocessor systems.
Atmel's scaled CMOS technology provides low active power consumption and fast
programming. Power consumption is typically 10 mA in active mode and less than 10
A in standby mode.
(continued)
Pin Configurations
Pin Name
Function
A0 - A19
Addresses
O0 - O7
Outputs
CE
Chip Enable
OE
Output Enable
PLCC Top View
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A7
A6
A5
A4
A3
A2
A1
A0
O0
A14
A13
A8
A9
A11
OE/VPP
A10
CE
07
4
3
2
1
32
31
30
14
15
16
17
18
19
20
01
02
GND
03
04
05
06
A12
A15
A16
A19
VCC
A18
A17
CDIP, PDIP, SOIC Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A19
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
VCC
A18
A17
A14
A13
A8
A9
A11
OE/VPP
A10
CE
07
06
05
04
03
TSOP Top View
Type 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
A17
A18
VCC
A19
A16
A15
A12
A7
A6
A5
OE/VPP
A10
CE
07
06
05
04
03
GND
02
01
O0
A0
A1
A2
A3
A4
AT27C080
2
The AT27C080 is available in a choice of packages, includ-
ing; one-time programmable (OTP) plastic PLCC, PDIP,
SOIC (SOP), and TSOP, as well as windowed ceramic
Cerdip. All devices feature two-line control (CE, OE) to give
designers the flexibility to prevent bus contention.
W i t h h ig h d e n s i t y 1 M b y t e s t o ra g e c a p a b i l i t y , t h e
AT27C080 allows firmware to be stored reliably and to be
accessed by the system without the delays of mass storage
media.
Atmel's 27C080 has additional features to ensure high
quality and efficient production use. The Rapid
TM
Program-
ming Algorithm reduces the time required to program the
part and guarantees reliable programming. Programming
time is typically only 50
s/byte. The Integrated Product
Identification Code electronically identifies the device and
manufacturer. This feature is used by industry standard
programming equipment to select the proper programming
algorithms and voltages.
Erasure Characteristics
The entire memory array of the AT27C080 is erased (all
outputs read as V
OH
) after exposure to ultraviolet light at a
wavelength of 2,537. Complete erasure is assured after a
minimum of 20 minutes of exposure using 12,000
W/cm
2
intensity lamps spaced one inch away from the chip. Mini-
mum erase time for lamps at other intensity ratings can be
calculated from the minimum integrated erasure dose of 15
W.sec/cm
2
. To prevent unintentional erasure, an opaque
label is recommended to cover the clear window on any UV
erasable EPROM that will be subjected to continuous
flourescent indoor lighting or sunlight.
System Considerations
Switching between active and standby conditions via the
Chip Enable pin may produce transient voltage excursions.
Unless accommodated by the system design, these tran-
sients may exceed data sheet limits, resulting in device
non-conformance. At a minimum, a 0.1
F high frequency,
low inherent inductance, ceramic capacitor should be uti-
lized for each device. This capacitor should be connected
between the V
CC
and Ground terminals of the device, as
close to the device as possible. Additionally, to stabilize the
supply voltage level on printed circuit boards with large
EPROM arrays, a 4.7
F bulk electrolytic capacitor should
be utilized, again connected between the V
CC
and Ground
terminals. This capacitor should be positioned as close as
possible to the point where the power supply is connected
to the array.
AT27C080
3
Absolute Maximum Ratings*
Temperature Under Bias ...................-55C to +125C
*NOTICE:
Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions beyond those
indicated in the operational sections of this
specification is not implied. Exposure to abso-
lute maximum rating conditions for extended
periods may affect device reliability.
Note:
1.
Minimum voltage is -0.6V DC which may
undershoot to -2.0V for pulses of less than 20
ns. Maximum output pin voltage is V
CC
+
0.75V DC which may overshoot to +7.0V for
pulses of less than 20 ns.
Storage Temperature.........................-65C to +150C
Voltage on Any Pin with
Respect to Ground ............................-2.0V to +7.0V
(1)
Voltage on A9 with
Respect to Ground .........................-2.0V to +14.0V
(1)
V
PP
Supply Voltage with
Respect to Ground ..........................-2.0V to +14.0V
(1)
Integrated UV Erase Dose................ 7258 Wsec/cm
2
Operating Modes
Notes:
1. X can be V
IL
or V
IH.
2. Refer to Programming Characteristics.
3. V
H
= 12.0
0.5V.
4. Two identifier bytes may be selected. All Ai inputs are held low (V
IL
), except A9 which is set to V
H
and A0 which is toggled
low (V
IL
) to select the Manufacturer's Identification byte and high (V
IH
) to select the Device Code byte.
Mode/Pin
CE
OE/V
PP
Ai
Outputs
Read
V
IL
V
IL
Ai
D
OUT
Output Disable
X
V
IH
X
(1)
High Z
Standby
V
IH
X
X
High Z
Rapid Program
(2)
V
IL
V
PP
Ai
D
IN
PGM Verify
V
IL
V
IL
Ai
D
OUT
PGM Inhibit
V
IH
V
PP
X
High Z
Product Identification
(4)
V
IL
V
IL
A9 = V
H
(3)
A0 = V
IH
or V
IL
A1 - A19 = V
IL
Identification Code
Block Diagram
AT27C080
4
DC and AC Operating Conditions for Read Operation
AT27C080
-90
-10
-12
-15
Operating Temperature (Case)
Com.
0C - 70C
0C - 70C
0C - 70C
0C - 70C
Ind.
-40
C - 85
C
-40
C - 85
C
-40
C - 85
C
-40
C - 85
C
V
CC
Power Supply
5V
10%
5V
10%
5V
10%
5V
10%
DC and Operating Characteristics for Read Operation
Note:
1. V
CC
must be applied simultaneously or before OE/ V
PP
, and removed simultaneously or after OE/V
PP
.
Symbol
Parameter
Condition
Min
Max
Units
I
LI
Input Load Current
V
IN
= 0V to V
CC
(Com., Ind.)
1.0
A
I
LO
Output Leakage Current
V
OUT
= 0V to V
CC
(Com., Ind.)
5.0
A
I
SB
V
CC
(1)
Standby Current
I
SB1
(CMOS), CE = V
CC
0.3V
100
A
I
SB2
(TTL), CE = 2.0 to V
CC
+ 0.5V
1.0
mA
I
CC
V
CC
Active Current
f = 5 MHz, I
OUT
= 0 mA, CE = V
IL
40
mA
V
IL
Input Low Voltage
-0.6
0.8
V
V
IH
Input High Voltage
2.0
V
CC
+ 0.5
V
V
OL
Output Low Voltage
I
OL
= 2.1 mA
0.4
V
V
OH
Output High Voltage
I
OH
= -400
A
2.4
V
AC Characteristics for Read Operation
Note:
2, 3, 4, 5. See AC Waveforms for Read Operation.
Symbol Parameter
Condition
AT27C080
Units
-90
-10
-12
-15
Min
Max
Min
Max
Min
Max
Min
Max
t
ACC
(4)
Address to Output Delay
CE = OE/V
PP
= V
IL
90
100
120
150
ns
t
CE
(3)
CE to Output Delay
OE = V
IL
90
100
120
150
ns
t
OE
(3)(4)
OE to Output Delay
CE = V
IL
20
20
30
35
ns
t
DF
(2)(5)
OE or CE High to Output Float,
whichever occurred first
30
30
35
40
ns
t
OH
Output Hold from Address, CE or
OE/V
PP
,whichever occurred first
0
0
0
0
ns
AT27C080
5
AC Waveforms for Read Operation
(1)
Notes:
1.
Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V, unless otherwise specified.
2.
t
DF
is specified form OE/VPP or CE, whichever occurs first. Output float is defined as the point when data is no longer
driven.
3.
OE/V
PP
may be delayed up to t
CE
- t
OE
after the falling edge of CE without impact on t
CE.
4.
OE/V
PP
may be delayed up to t
ACC
- t
OE
after the address is valid without impact on t
ACC
.
5.
This parameter is only sampled and is not 100% tested.
Input Test Waveform and Measurement Levels
t
R
, t
F
< 20 ns (10% to 90%)
Output Test Load
Note:
1.
CL = 100 pF including jig
capacitance.
Pin Capacitance
f = 1 MHz, T = 25
C
(1)
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Typ
Max
Units Conditions
C
IN
4
8
pF
V
IN
= 0V
C
OUT
8
12
pF
V
OUT
= 0V
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