1
Features
Low Voltage and Standard Voltage Operation
2.7 (V
CC
= 2.7V to 5.5V)
1.8 (V
CC
= 1.8V to 5.5V)
Internally Organized 128 x 8
2-Wire Serial Interface
Bidirectional Data Transfer Protocol
100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility
4-Byte Page Write Mode
Self-Timed Write Cycle (10 ms max)
High Reliability
Endurance: 1 Million Write Cycles
Data Retention: 100 Years
Automotive Grade, Extended Temperature and Lead-Free Devices Available
8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP Packages
Description
The AT24C01 provides 1024 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 128 words of 8 bits each. The device is
optimized for use in many industrial and commercial applications where low power
and low voltage operation are essential. The AT24C01 is available in space saving
8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP packages and is accessed via a
2-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V)
and 1.8V (1.8V to 5.5V) versions.
2-Wire Serial
EEPROM
1K (128 x 8)
AT24C01
Rev. 0134FSEEPR1/03
Pin Configurations
Pin Name
Function
NC
No Connect
SDA
Serial Data
SCL
Serial Clock Input
TEST
Test Input (GND or VCC)
8-lead PDIP
1
2
3
4
8
7
6
5
NC
NC
NC
GND
VCC
TEST
SCL
SDA
8-lead SOIC
1
2
3
4
8
7
6
5
NC
NC
NC
GND
VCC
TEST
SCL
SDA
8-lead TSSOP
1
2
3
4
8
7
6
5
NC
NC
NC
GND
VCC
TEST
SCL
SDA
2
AT24C01
0134FSEEPR1/03
Block Diagram
Absolute Maximum Ratings*
Operating Temperature .................................. -55
C to +125C
*NOTICE:
Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature ..................................... -65
C to +150C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
3
AT24C01
0134FSEEPR1/03
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
Memory Organization
AT24C01, 1K SERIAL EEPROM: Internally organized with 128 pages of 1 byte each.
The 1K requires a 7-bit data word address for random word addressing.
Note:
1. V
IL
min and V
IH
max are reference only and are not tested.
Pin Capacitance
Applicable over recommended operating range from T
A
= 25
C, f = 1.0 MHz, V
CC
= +1.8V.
Symbol
Test Condition
Max
Units
Condition
C
I/O
Input/Output Capacitance (SDA)
8
pF
V
I/O
= 0V
C
IN
Input Capacitance (A0, A1, A2, SCL)
6
pF
V
IN
= 0V
DC Characteristics
Applicable over recommended operating range from: T
AI
= -40
C to +85C, V
CC
= +1.8V to +5.5V, T
AE
= -40
C to +125C,
V
CC
= +1.8V to +5.5V (unless otherwise noted).
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
V
CC1
Supply Voltage
1.8
5.5
V
V
CC2
Supply Voltage
2.5
5.5
V
V
CC3
Supply Voltage
2.7
5.5
V
V
CC4
Supply Voltage
4.5
5.5
V
I
CC
Supply Current V
CC
= 5.0V
READ at 100 kHz
0.4
1.0
mA
I
CC
Supply Current V
CC
= 5.0V
WRITE at 100 kHz
2.0
3.0
mA
I
SB1
Standby Current V
CC
= 1.8V
V
IN
= V
CC
or V
SS
0.6
3.0
A
I
SB2
Standby Current V
CC
= 2.5V
V
IN
= V
CC
or V
SS
1.4
4.0
A
I
SB3
Standby Current V
CC
= 2.7V
V
IN
= V
CC
or V
SS
1.6
4.0
A
I
SB4
Standby Current V
CC
= 5.0V
V
IN
= V
CC
or V
SS
8.0
18.0
A
I
LI
Input Leakage Current
V
IN
= V
CC
or V
SS
0.10
3.0
A
I
LO
Output Leakage Current
V
OUT
= V
CC
or V
SS
0.05
3.0
A
V
IL
Input Low Level
(1)
-0.6
V
CC
0.3
V
V
IH
Input High Level
(1)
V
CC
0.7
V
CC
+ 0.5
V
V
OL2
Output Low Level V
CC
= 3.0V
I
OL
= 2.1 mA
0.4
V
V
OL1
Output Low Level V
CC
= 1.8V
I
OL
= 0.15 mA
0.2
V
4
AT24C01
0134FSEEPR1/03
Note:
1. This parameter is characterized and is not 100% tested.
AC Characteristics
Applicable over recommended operating range from T
AI
= -40
C to +85C, T
AE
= -40
C to +125C, V
CC
= +1.8V to +5.5V,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
2.7-, 2.5-, 1.8-volt
5.0-volt
Units
Min
Max
Min
Max
f
SCL
Clock Frequency, SCL
100
400
kHz
t
LOW
Clock Pulse Width Low
4.7
1.2
s
t
HIGH
Clock Pulse Width High
4.0
0.6
s
t
I
Noise Suppression Time
(1)
100
50
ns
t
AA
Clock Low to Data Out Valid
0.1
4.5
0.1
0.9
s
t
BUF
Time the bus must be free before a new
transmission can start
(1)
4.7
1.2
s
t
HD.STA
Start Hold Time
4.0
0.6
s
t
SU.STA
Start Set-up Time
4.7
0.6
s
t
HD.DAT
Data In Hold Time
0
0
s
t
SU.DAT
Data In Set-up Time
200
100
ns
t
R
Inputs Rise Time
(1)
1.0
0.3
s
t
F
Inputs Fall Time
(1)
300
300
ns
t
SU.STO
Stop Set-up Time
4.7
0.6
s
t
DH
Data Out Hold Time
100
50
ns
t
WR
Write Cycle Time
10
10
ms
Endurance
(1)
5.0V, 25C, Page Mode
1M
1M
Write
Cycles
5
AT24C01
0134FSEEPR1/03
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL high periods will indicate a start
or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (refer to Start and Stop Definition timing
diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition
which terminates all communications. After a read sequence, the stop command will
place the EEPROM in a standby power mode (refer to Start and Stop Definition timing
diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from
the EEPROM in 8-bit words. Any device on the system bus receiving data (when com-
municating with the EEPROM) must pull the SDA bus low to acknowledge that it has
successfully received each word. This must happen during the ninth clock cycle after
each word received and after all other system devices have freed the SDA bus. The
EEPROM will likewise acknowledge by pulling SDA low after receiving each address or
data word (refer to Acknowledge Response from Receiver timing diagram).
STANDBY MODE: The AT24C01 features a low power standby mode which is enabled:
(a) upon power-up and (b) after the receipt of the STOP bit and the completion of any
internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-
wire part can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.
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