1
Features
Low-voltage and Standard-voltage Operation
5.0 (V
CC
= 4.5V to 5.5V)
2.7 (V
CC
= 2.7V to 5.5V)
Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),
1024 x 8 (8K) or 2048 x 8 (16K)
2-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bi-directional Data Transfer Protocol
100 kHz (2.7V) and 400 kHz (5V) Compatibility
8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes
Partial Page Writes Are Allowed
Self-timed Write Cycle (10 ms max)
High-reliability
Endurance: 100,000 Write Cycles
Data Retention: 100 Years
ESD Protection: >3000V
Description
The AT24C01A/02SC/04SC/08SC/16SC provides 1024/2048/4096/8192/16384 bits
of serial, electrically-erasable and programmable read-only memory (EEPROM)
organized as 128/256/512/1024/2048 words of 8 bits each. The devices are optimized
for use in smart card applications where low-power and low-voltage operation may be
essential. The devices are available in several standard ISO 7816 smart card modules
(see Ordering Information). The entire family is available in both high-voltage (4.5V to
5.5V) and low-voltage (2.7V to 5.5V) versions. All devices are functionally equivalent
to Atmel serial EEPROM products offered in standard IC packages (PDIP, SOIC,
EIAJ, LAP), with the exception of the slave address and Write Protect functions, which
are not required for smart card applications.
Pin Configurations
Card Module Contact
Pad Name
Description
ISO Module Contact
VCC
Power Supply Voltage
C1
GND
Ground
C5
SCL
Serial Clock Input
C3
SDA
Serial Data Input/Output
C7
NC
No Connect
C2, C4, C6, C8
NC
VCC
2-wire Serial
EEPROM Smart
Card Modules
1K (128 x 8)
2K (256 x 8)
4K (512 x 8)
8K (1024 x 8)
16K (2048 x 8)
AT24C01ASC
AT24C02SC
AT24C04SC
AT24C08SC
AT24C16SC
Rev. 1610A05/00
AT24C01ASC/02SC/04SC/08SC/16SC
2
Block Diagram
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive
edge clock data into each EEPROM device and negative
edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bi-directional for
serial data transfer. This pin is open-drain driven and may
be wire-ORed with any number of other open-drain or
open-collector devices.
Memory Organization
AT24C01ASC, 1K SERIAL EEPROM: Internally organized
with 16 pages of 8 bytes each, the 1K requires a 7-bit data
word address for random word addressing.
AT24C02SC, 2K SERIAL EEPROM: Internally organized
with 32 pages of 8 bytes each, the 2K requires an 8-bit data
word address for random word addressing.
AT24C04SC, 4K SERIAL EEPROM: The 4K is internally
organized with 32 pages of 16 bytes each. Random word
addressing Chip Number requires a 9-bit data word
address.
AT24C08SC, 8K SERIAL EEPROM: The 8K is internally
organized with 64 pages of 16 bytes each. Random word
addressing requires a 10-bit data word address.
AT24C16SC, 16K SERIAL EEPROM: The 16K is internally
organized with 128 pages of 16 bytes each. Random word
addressing requires an 11-bit data word address.
Absolute Maximum Ratings
Operating Temperature.................................. -55
C to +125C
*NOTICE:
Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature ..................................... -65
C to +150C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
AT24C01ASC/02SC/04SC/08SC/16SC
3
Note:
1. This parameter is characterized and is not 100% tested.
Note:
1. V
IL
min and V
IH
max are reference only and are not tested.
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25
C, f = 1.0 MHz, V
CC
= +2.7V.
Symbol
Test Condition
Max
Units
Conditions
C
I/O
Input/Output Capacitance (SDA)
8
pF
V
I/O
= 0V
C
IN
Input Capacitance (SCL)
6
pF
V
IN
= 0V
DC Characteristics
Applicable over recommended operating range from: T
AC
= 0
C to +70C, V
CC
= +2.7V to +5.5V (unless otherwise noted).
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
V
CC1
Supply Voltage
2.7
5.5
V
V
CC2
Supply Voltage
4.5
5.5
V
I
CC
Supply Current V
CC
= 5.0V
READ at 100 kHz
0.4
1.0
mA
I
CC
Supply Current V
CC
= 5.0V
WRITE at 100 kHz
2.0
3.0
mA
I
SB1
Standby Current V
CC
= 2.7V
V
IN
= V
CC
or GND
1.6
4.0
A
I
SB2
Standby Current V
CC
= 5.0V
V
IN
= V
CC
or GND
8.0
18.0
A
I
LI
Input Leakage Current
V
IN
= V
CC
or GND
0.10
3.0
A
I
LO
Output Leakage Current
V
OUT
= V
CC
or GND
0.05
3.0
A
V
IL
Input Low Level
(1)
-0.6
V
CC
x 0.3
V
V
IH
Input High Level
(1)
V
CC
x 0.7
V
CC
+ 0.5
V
V
OL
Output Low Level V
CC
= 3.0V
I
OL
= 2.1 mA
0.4
V
AC Characteristics
Applicable over recommended operating range from T
A
= 0
C to +70C, V
CC
= +2.7V to +5.5V, CL = 1 TTL Gate and 100
pF (unless otherwise noted).
Symbol
Parameter
2.7-volt
5.0-volt
Units
Min
Max
Min
Max
f
SCL
Clock Frequency, SCL
100
400
kHz
t
LOW
Clock Pulse Width Low
4.7
1.2
s
t
HIGH
Clock Pulse Width High
4.0
0.6
s
t
I
Noise Suppression Time
(1)
100
50
ns
t
AA
Clock Low to Data Out Valid
0.1
4.5
0.1
0.9
s
t
BUF
Time the bus must be free before a new
transmission can start
(1)
4.7
1.2
s
t
HD.STA
Start Hold Time
4.0
0.6
s
t
SU.STA
Start Setup Time
4.7
0.6
s
t
HD.DAT
Data In Hold Time
0
0
s
t
SU.DAT
Data In Setup Time
200
100
ns
t
R
Inputs Rise Time
(1)
1.0
0.3
s
AT24C01ASC/02SC/04SC/08SC/16SC
4
Note:
1. This parameter is characterized and is not 100% tested.
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is nor-
mally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL
high periods will indicate a start or stop condition as
defined below.
START CONDITION: A high-to-low transition of SDA with
SCL high is a start condition that must precede any other
command (refer to Start and Stop Definition timing dia-
gram).
STOP CONDITION: A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
Stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are
serially transmitted to and from the EEPROM in 8-bit
words. Each word requires the receiver to acknowledge
that it has received a valid command or data byte. During
the transmission of commands from the host to the
EEPROM, the EEPROM will send a zero to the host to
acknowledge that it has received a valid command byte.
This occurs on the ninth clock cycle of the command byte.
During read operations, the host will send a zero to the
EEPROM to acknowledge that it has received a valid data
byte and that it requests the next sequential data byte to be
transmitted during the subsequent eight clock cycles. This
occurs on the ninth clock cycle of the data byte. If the host
does not transmit this acknowledge bit, the EEPROM will
disable the Read operation and return to standby mode.
STANDBY MODE: The AT24C01ASC/02SC/04SC/
08SC/16SC features a low-power standby mode that is
enabled: (a) upon power-up and (b) after the receipt of the
STOP bit and the completion of any internal operations.
MEMORY RESET: After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by follow-
ing these steps:
1.
Clock up to 9 cycles.
2.
Look for SDA high in each cycle while SCL is high.
3.
Create a start condition as SDA is high.
t
F
Inputs Fall Time
(1)
300
300
ns
t
SU.STO
Stop Setup Time
4.7
0.6
s
t
DH
Data Out Hold Time
100
50
ns
t
WR
Write Cycle Time
10
10
ms
Endurance
(1)
5.0V, 25
C, Page Mode
100K
100K
Write
Cycles
AC Characteristics (Continued)
Applicable over recommended operating range from T
A
= 0
C to +70C, V
CC
= +2.7V to +5.5V, CL = 1 TTL Gate and 100
pF (unless otherwise noted).
Symbol
Parameter
2.7-volt
5.0-volt
Units
Min
Max
Min
Max
AT24C01ASC/02SC/04SC/08SC/16SC
5
Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
Note:
1.
The write cycle time t
WR
is the time from a valid stop condition of a write sequence to the end of the internal clear/write
cycle.
t
WR
(1)
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