1
Features
Low-voltage and Standard-voltage Operation
2.7 (V
CC
= 2.7V to 5.5V)
1.8 (V
CC
= 1.8V to 3.6V)
Internally Organized 65,536 x 8
2-wire Serial Interface
Schmitt Triggers, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility
Write Protect Pin for Hardware and Software Data Protection
128-byte Page Write Mode (Partial Page Writes Allowed)
Self-timed Write Cycle (5 ms Typical)
High Reliability
Endurance: 100,000 Write Cycles
Data Retention: 40 Years
Automotive Grade and Extended Temperature Devices Available
8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP,
8-lead LAP and 8-ball dBGA
TM
Packages
Description
The AT24C512 provides 524,288 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device's
cascadable feature allows up to 4 devices to share a common 2-wire bus. The device
is optimized for use in many industrial and commercial applications where low-power
and low-voltage operation are essential. The devices are available in space-saving
8-pin PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead Leadless
Array (LAP) and 8-ball dBGA
packages. In addition, the entire family is available in
2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.
Rev. 1116ISEEPR3/03
2-wire Serial
EEPROM
512K (65,536 x 8)
AT24C512
Pin Configurations
Pin Name
Function
A0 - A1
Address Inputs
SDA
Serial Data
SCL
Serial Clock Input
WP
Write Protect
NC
No Connect
8-lead PDIP
1
2
3
4
8
7
6
5
A0
A1
NC
GND
VCC
WP
SCL
SDA
8-lead Leadless Array
Bottom View
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
NC
GND
8-lead TSSOP
1
2
3
4
8
7
6
5
A0
A1
NC
GND
VCC
WP
SCL
SDA
8-ball dBGA
Bottom View
VCC
WP
SCL
SDA
A0
A1
NC
GND
1
2
3
4
8
7
6
5
8-lead SOIC
1
2
3
4
8
7
6
5
A0
A1
NC
GND
VCC
WP
SCL
SDA
2
AT24C512
1116ISEEPR3/03
Block Diagram
Absolute Maximum Ratings*
Operating Temperature .................................. -55
C to +125
C
*NOTICE:
Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature ..................................... -65
C to +150
C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
3
AT24C512
1116ISEEPR3/03
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs
that are hardwired or left not connected for hardware compatibility with AT24C128/256.
When the pins are hardwired, as many as four 512K devices may be addressed on a
single bus system (device addressing is discussed in detail under the Device Address-
ing section). When the pins are not hardwired, the default A1 and A0 are zero.
WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write
operations. When WP is tied high to V
CC
, all write operations to the memory are inhib-
ited. If left unconnected, WP is internally pulled down to GND. Switching WP to V
CC
prior
to a write operation creates a software write protect function.
Memory Organization
AT24C512, 512K SERIAL EEPROM: The 512K is internally organized as 512 pages of
128-bytes each. Random word addressing requires a 16-bit data word address.
4
AT24C512
1116ISEEPR3/03
Note:
1. This parameter is characterized and is not 100% tested.
Note:
1. V
IL
min and V
IH
max are reference only and are not tested.
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25
C, f = 1.0 MHz, V
CC
= +1.8V.
Symbol
Test Condition
Max
Units
Conditions
C
I/O
Input/Output Capacitance (SDA)
8
pF
V
I/O
= 0V
C
IN
Input Capacitance (A
0
, A
1
, SCL)
6
pF
V
IN
= 0V
DC Characteristics
Applicable over recommended operating range from: T
AI
= -40
C to +85
C, V
CC
= +1.8V to +5.5V, T
AC
= 0
C to +70
C,
V
CC
= +1.8V to +5.5V (unless otherwise noted).
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
V
CC1
Supply Voltage
1.8
3.6
V
V
CC2
Supply Voltage
2.7
5.5
V
V
CC3
Supply Voltage
4.5
5.5
V
I
CC1
Supply Current
V
CC
= 5.0V
READ at 400 kHz
1.0
2.0
mA
I
CC2
Supply Current
V
CC
= 5.0V
WRITE at 400 kHz
2.0
3.0
mA
I
SB1
Standby Current
(1.8V option)
V
CC
= 1.8V
V
IN
= V
CC
or V
SS
1.0
A
V
CC
= 3.6V
3.0
I
SB2
Standby Current
(2.7V option)
V
CC
= 2.7V
V
IN
= V
CC
or V
SS
2.0
A
V
CC
= 5.5V
6.0
I
SB3
Standby Current
(5.0V option)
V
CC
= 4.5 - 5.5V
V
IN
= V
CC
or V
SS
6.0
A
I
LI
Input Leakage Current
V
IN
= V
CC
or
V
SS
0.10
3.0
A
I
LO
Output Leakage
Current
V
OUT
= V
CC
or
V
SS
0.05
3.0
A
V
IL
Input Low Level
(1)
-0.6
V
CC
x 0.3
V
V
IH
Input High Level
(1)
V
CC
x 0.7
V
CC
+ 0.5
V
V
OL2
Output Low Level
V
CC
= 3.0V
I
OL
= 2.1 mA
0.4
V
V
OL1
Output Low Level
V
CC
= 1.8V
I
OL
= 0.15 mA
0.2
V
5
AT24C512
1116ISEEPR3/03
Notes:
1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
R
L
(connects to V
CC
): 1.3 k
(2.7V, 5V), 10 k
(1.8V)
Input pulse voltages: 0.3V
CC
to 0.7V
CC
Input rise and fall times:
50 ns
Input and output timing reference voltages: 0.5V
CC
AC Characteristics
Applicable over recommended operating range from T
A
= -40
C to +85
C, V
CC
= +1.8V to +5.5V, C
L
= 100 pF (unless oth-
erwise noted). Test conditions are listed in Note 2.
Symbol
Parameter
1.8-volt
2.7-volt
5.0-volt
Units
Min
Max
Min
Max
Min
Max
f
SCL
Clock Frequency, SCL
100
400
1000
kHz
t
LOW
Clock Pulse Width Low
4.7
1.3
0.4
s
t
HIGH
Clock Pulse Width High
4.0
1.0
0.4
s
t
AA
Clock Low to Data Out Valid
0.1
4.5
0.05
0.9
0.05
0.55
s
t
BUF
Time the bus must be free before a new
transmission can start
(1)
4.7
1.3
0.5
s
t
HD.STA
Start Hold Time
4.0
0.6
0.25
s
t
SU.STA
Start Set-up Time
4.7
0.6
0.25
s
t
HD.DAT
Data In Hold Time
0
0
0
s
t
SU.DAT
Data In Set-up Time
200
100
100
ns
t
R
Inputs Rise Time
(1)
1.0
0.3
0.3
s
t
F
Inputs Fall Time
(1)
300
300
100
ns
t
SU.STO
Stop Set-up Time
4.7
0.6
0.25
s
t
DH
Data Out Hold Time
100
50
50
ns
t
WR
Write Cycle Time
20
10
10
ms
Endurance
(1)
5.0V, 25
C, Page Mode
100K
100K
100K
Write Cycles
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