1
Features
Low-voltage and Standard-voltage Operation
2.7 (V
CC
= 2.7 to 5.5V)
1.8 (V
CC
= 1.8 to 5.5V)
Low-power Devices (I
SB
= 6
A at 5.5V) Available
Internally Organized 8192 x 8
2-Wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bi-directional Data Transfer Protocol
400 kHz Clock Rate
Write Protect Pin for Hardware Data Protection
32-Byte Page Write Mode (Partial Page Writes Allowed)
Self-Timed Write Cycle (5 ms max)
High Reliability
Endurance: 1 Million Write Cycles
Data Retention: 100 Years
Lead-free/Halogen-free Devices Available
8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP Packages
Description
The AT24C64B provides 65,536 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 8192 words of 8 bits each. The device's
cascadable feature allows up to 8 devices to share a common 2-wire bus. The device
is optimized for use in many industrial and commercial applications where low power
and low voltage operation are essential. The AT24C64B is available in space saving
8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP packages and is accessed via a
2-wire serial interface. In addition, the entire family is available in 2.7V (2.7 to 5.5V)
and 1.8V (1.8 to 5.5V) versions.
2-Wire
Serial EEPROM
64K (8192 x 8)
AT24C64B
3350CSEEPR5/04
2-Wire, 32K
Serial E
2
PROM
Pin Configurations
Pin Name
Function
A0 - A2
Address Inputs
SDA
Serial Data
SCL
Serial Clock Input
WP
Write Protect
8-lead SOIC
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
8-lead PDIP
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
8-lead TSSOP
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
2
AT24C64B
3350CSEEPR5/04
Block Diagram
Absolute Maximum Ratings*
Operating Temperature...................................... -55 to +125
C
*NOTICE:
Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature ......................................... -65 to +150
C
Voltage on Any Pin
with Respect to Ground ....................................... -1.0 to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
3
AT24C64B
3350CSEEPR5/04
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs
that are hard wired or left not connected for hardware compatibility with other AT24CXX
devices. When the pins are hardwired, as many as eight 64K devices may be addressed
on a single bus system (device addressing is discussed in detail under the Device
Addressing section). If the pins are left floating, the A2, A1 and A0 pins will be internally
pulled down to GND if the capacitive coupling to the circuit board V
CC
plane is <3pF.
If coupling is >3pF, Atmel recommends connecting the address pins to GND.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows nor-
mal write operations. When WP is connected high to V
CC
, all write operations to the
upper quandrant (16K bits) of memory are inhibited. If the pin is left floating, the WP pin
will be internally pulled down to GND if the capacitive coupling to the circuit board V
CC
plane is <3pF. If coupling is >3pF, Atmel recommends connecting the pin to GND.
Memory Organization
AT24C64B, 64K SERIAL EEPROM: The 64K is internally organized as 256 pages of
32 bytes each. Random word addressing requires a 13 bit data word address.
4
AT24C64B
3350CSEEPR5/04
Note:
1. This parameter is characterized and is not 100% tested.
Note:
1. V
IL
min and V
IH
max are reference only and are not tested.
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25
C, f = 1.0 MHz, V
CC
= +1.8V.
Symbol
Test Condition
Max
Units
Conditions
C
I/O
Input/Output Capacitance (SDA)
8
pF
V
I/O
= 0V
C
IN
Input Capacitance (A
0
, A
1
, A
2
, SCL)
6
pF
V
IN
= 0V
DC Characteristics
Applicable over recommended operating range from: T
AI
= -40 to +85
C, V
CC
= +1.8 to +5.5V (unless otherwise noted).
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
V
CC1
Supply Voltage
1.8
5.5
V
V
CC2
Supply Voltage
2.7
5.5
V
V
CC3
Supply Voltage
4.5
5.5
V
I
CC1
Supply Current
V
CC
= 5.0V
READ at 400 kHz
0.4
1.0
mA
I
CC2
Supply Current
V
CC
= 5.0V
WRITE at 400 kHz
2.0
3.0
mA
I
SB1
Standby Current
(1.8V option)
V
CC
= 1.8V
V
IN
= V
CC
or V
SS
1.0
A
I
SB2
Standby Current
(2.7V option)
V
CC
= 2.7V
V
IN
= V
CC
or V
SS
2.0
A
I
SB3
Standby Current
(5V option)
V
CC
= 4.5 - 5.5V
V
IN
= V
CC
or V
SS
6.0
A
I
LI
Input Leakage
Current
V
IN
= V
CC
or
V
SS
0.10
3.0
A
I
LO
Output Leakage
Current
V
OUT
= V
CC
or
V
SS
0.05
3.0
A
V
IL
Input Low Level
(1)
-0.6
V
CC
x 0.3
V
V
IH
Input High Level
(1)
V
CC
x 0.7
V
CC
+ 0.5
V
V
OL2
Output Low Level
V
CC
= 3.0V
I
OL
= 2.1 mA
0.4
V
V
OL1
Output Low Level
V
CC
= 1.8V
I
OL
= 0.15 mA
0.2
V
5
AT24C64B
3350CSEEPR5/04
Notes:
1. This parameter is characterized and is not 100% tested (T
A
= 25
C)
2. This parameter is characterized and is not 100% tested.
AC Characteristics
Applicable over recommended operating range from T
AI
= -40
C to +85
C, V
CC
= +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted).
Symbol
Parameter
AT24C64B
Units
1.8V 3.6V
5.0V
Min
Max
Min
Max
f
SCL
Clock Frequency, SCL
400
400
kHz
t
LOW
Clock Pulse Width Low
1.3
1.2
s
t
HIGH
Clock Pulse Width High
0.6
0.6
s
t
I
Noise Suppression Time
(1)
100
50
ns
t
AA
Clock Low to Data Out Valid
0.2
0.9
0.1
0.9
s
t
BUF
Time the bus must be free before a new transmission can start
(2)
1.3
1.2
s
t
HD.STA
Start Hold Time
0.6
0.6
s
t
SU.STA
Start Set-up Time
0.6
0.6
s
t
HD.DAT
Data In Hold Time
0
0
s
t
SU.DAT
Data In Set-up Time
100
100
ns
t
R
Inputs Rise Time
(2)
0.3
0.3
s
t
F
Inputs Fall Time
(2)
300
300
ns
t
SU.STO
Stop Set-up Time
0.6
0.6
s
t
DH
Data Out Hold Time
200
50
ns
t
WR
Write Cycle Time
5
5
ms
Endurance
(1)
5.0V, 25
C, Page Mode
1M
1M
Write
Cycles
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