1
Features
Write Protect Pin for Hardware Data Protection
Utilizes Different Array Protection Compared to the AT24C02B
Low-voltage and Standard-voltage Operation
1.8 (V
CC
= 1.8V to 5.5V)
Internally Organized 256 x 8 (2K)
Two-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
1 MHz (5V) and 400 kHz (1.8V, 2.5V, 2.7V) Clock Rate
8-byte Page
Partial Page Writes Allowed
Self-timed Write Cycle (5 ms Max)
High Reliability
Endurance: One Million Write Cycles
Data Retention: 100 Years
8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP Packages
Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
Description
The AT24HC02B provides 2048 bits of serial electrically erasable and programmable
read-only memory (EEPROM) organized as 256 words of 8 bits each. The device is opti-
mized for use in many industrial and commercial applications where low-power and low-
voltage operation are essential. The AT24HC02B is available in space-saving 8-lead
PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP packages and is accessed via a two-wire
serial interface. In addition, the entire family is available in 1.8V (1.8V to 5.5V) version.
Table 1. Pin Configuration
Pin Name
Function
A0A2
Address Inputs
SDA
Serial Data
SCL
Serial Clock Input
WP
Write Protect
NC
No-connect
Two-wire Serial
EEPROM
2K (256 x 8)
AT24HC02B
Rev. 5134ASEEPR9/05
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
8-lead PDIP
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
8-lead SOIC
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
8-lead TSSOP
2
AT24HC02B
5134ASEEPR9/05
Figure 1. Block Diagram
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device
address inputs that must be hardwired for the AT24HC02B. As many as eight 2K
devices may be addressed on a single bus system. (Device addressing is discussed in
detail under Device Addressing, page 8).
Absolute Maximum Ratings*
Operating Temperature
........................................-40C to +85C
*NOTICE:
Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature
.........................................-65C to +150C
Voltage on Any Pin
with Respect to Ground
........................................ -1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
START
STOP
LOGIC
3
AT24HC02B
5134ASEEPR9/05
WRITE PROTECT (WP): The AT24HC02B has a WP pin that provides hardware data
protection. The WP pin allows normal read/write operations when connected to ground
(GND). When the WP pin is connected to V
CC
, the write protection feature is enabled
and operates as shown.
Table 2. Write Protect
Memory Organization
AT24HC02B, 2K SERIAL EEPROM: The 2K is internally organized with 32 pages of 8
bytes each. Random word addressing requires an 8-bit data word address.
Note:
1. This parameter is characterized and is not 100% tested.
WP Pin Status
Part of the Array Protected
24HC02B
At V
CC
Upper Half (1K) Array
At GND
Normal Read/Write Operations
Table 3. Pin Capacitance
(1)
Applicable over recommended operating range from T
AI
= 25
C, f = 1.0 MHz, V
CC
= +1.8V
Symbol
Test Condition
Max
Units
Conditions
C
I/O
Input/Output Capacitance (SDA)
8
pF
V
I/O
= 0V
C
IN
Input Capacitance (A
0
, A
1
, A
2
, SCL)
6
pF
V
IN
= 0V
4
AT24HC02B
5134ASEEPR9/05
Note:
1. V
IL
min and V
IH
max are reference only and are not tested.
Table 4. DC Characteristics
Applicable over recommended operating range from: T
AI
=
-40C to +85C, V
CC
= +1.8V to +5.5V (unless otherwise noted)
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
V
CC1
Supply Voltage
1.8
5.5
V
V
CC2
Supply Voltage
2.5
5.5
V
V
CC3
Supply Voltage
2.7
5.5
V
V
CC4
Supply Voltage
4.5
5.5
V
I
CC
Supply Current V
CC
= 5.0V
READ at 100 kHz
0.4
1.0
mA
I
CC
Supply Current V
CC
= 5.0V
WRITE at 100 kHz
2.0
3.0
mA
I
SB1
Standby Current V
CC
= 1.8V
V
IN
= V
CC
or V
SS
0.6
3.0
A
I
SB2
Standby Current V
CC
= 2.5V
V
IN
= V
CC
or V
SS
1.4
4.0
A
I
SB3
Standby Current V
CC
= 2.7V
V
IN
= V
CC
or V
SS
1.6
4.0
A
I
SB4
Standby Current V
CC
= 5.0V
V
IN
= V
CC
or V
SS
8.0
18.0
A
I
LI
Input Leakage Current
V
IN
= V
CC
or V
SS
0.10
3.0
A
I
LO
Output Leakage Current
V
OUT
= V
CC
or V
SS
0.05
3.0
A
V
IL
Input Low Level
(1)
-0.6
V
CC
x 0.3
V
V
IH
Input High Level
(1)
V
CC
x 0.7
V
CC
+ 0.5
V
V
OL2
Output Low Level V
CC
= 3.0V
I
OL
= 2.1 mA
0.4
V
V
OL1
Output Low Level V
CC
= 1.8V
I
OL
= 0.15 mA
0.2
V
5
AT24HC02B
5134ASEEPR9/05
Note:
1. This parameter is ensured by characterization only.
Table 5. AC Characteristics
Applicable over recommended operating range from T
AI
=
40
C to +85C, V
CC
= +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted)
Symbol
Parameter
1.8, 2.5, 2.7
5.0-volt
Units
Min
Max
Min
Max
f
SCL
Clock Frequency, SCL
400
1000
kHz
t
LOW
Clock Pulse Width Low
1.2
0.4
s
t
HIGH
Clock Pulse Width High
0.6
0.4
s
t
I
Noise Suppression Time
50
40
ns
t
AA
Clock Low to Data Out Valid
0.1
0.9
0.05
0.55
s
t
BUF
Time the bus must be free before a new
transmission can start
1.2
0.5
s
t
HD.STA
Start Hold Time
0.6
0.25
s
t
SU.STA
Start Setup Time
0.6
0.25
s
t
HD.DAT
Data In Hold Time
0
0
s
t
SU.DAT
Data In Setup Time
100
100
ns
t
R
Inputs Rise Time
(1)
0.3
0.3
s
t
F
Inputs Fall Time
(1)
300
100
ns
t
SU.STO
Stop Setup Time
0.6
.25
s
t
DH
Data Out Hold Time
50
50
ns
t
WR
Write Cycle Time
5
5
ms
Endurance
(1)
5.0V, 25
C, Byte Mode
1M
Write Cycles
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