1
Features
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
Low-voltage and Standard-voltage Operation
2.7 (V
CC
= 2.7V to 5.5V)
3.0 MHz Clock Rate (5V)
8-byte Page Mode
Block Write Protection
Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
Self-timed Write Cycle (10 ms max)
High Reliability
Endurance: One Million Write Cycles
Data Retention: 100 Years
Automotive Grade Devices Available
8-lead PDIP and 8-lead JEDEC SOIC Packages
Description
The AT25010/020/040 provides 1024/2048/4096 bits of serial electrically erasable
programmable read only memory (EEPROM) organized as 128/256/512 words of 8
bits each. The device is optimized for use in many industrial and commercial applica-
tions where low-power and low voltage operation are essential. The AT25010/020/040
is available in space saving 8-lead PDIP and 8-lead JEDEC SOIC packages.
The AT25010/020/040 is enabled through the Chip Select pin (CS) and accessed via a
3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-
rate ERASE cycle is required before WRITE.
BLOCK WRITE protection is enabled by programming the status register with one of
four blocks of write protection. Separate program enable and program disable instruc-
tions are provided for additional data protection. Hardware data protection is provided
via the WP pin to protect against inadvertent write attempts. The HOLD pin may be
used to suspend any serial communication without resetting the serial sequence.
SPI Serial
EEPROMs
1K (128 x 8)
2K (256 x 8)
4K (512 x 8)
AT25010
AT25020
AT25040
Pin Configurations
Pin Name
Function
CS
Chip Select
SCK
Serial Data Clock
SI
Serial Data Input
SO
Serial Data Output
GND
Ground
VCC
Power Supply
WP
Write Protect
HOLD
Suspends Serial Input
8-lead PDIP
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
8-lead SOIC
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
Rev. 0606LSEEPR03/03
2
AT25010/020/040
0606LSEEPR03/03
Block Diagram
Absolute Maximum Ratings*
Operating Temperature ................................. -55C to + 125C
*NOTICE:
Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature .................................... -65C to + 150C
Voltage on Any Pin
with Respect to Ground ....................................-1.0V to + 7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
3
AT25010/020/040
0606LSEEPR03/03
Note:
1. This parameter is characterized and is not 100% tested.
Note:
1. This parameter is preliminary and Atmel may change the specifications upon further characterization.
2. V
IL
min and V
IH
max are reference only and are not tested.
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25C, f = 1.0 MHz, V
CC
= +5.0V (unless otherwise noted).
Symbol
Test Conditions
Max
Units
Conditions
C
OUT
Output Capacitance (SO)
8
pF
V
OUT
= 0V
C
IN
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
V
IN
= 0V
DC Characteristics
Applicable over recommended operating range from: T
AI
= -40C to +85C, V
CC
= +2.7V to +5.5V, V
CC
= +2.7V to +5.5V
(unless otherwise noted).
Symbol
Parameter
Test Condition
Min
Max
Units
V
CC1
Supply Voltage
2.7
5.5
V
V
CC2
Supply Voltage
4.5
5.5
V
I
CC1
Supply Current
V
CC
= 5.0V at 1 MHz, SO = Open, Read
3.0
mA
I
CC2
Supply Current
V
CC
= 5.0V at 2 MHz, SO = Open,
Read, Write
6.0
mA
I
SB1
Standby Current
V
CC
= 2.7V
CS = V
CC
5
A
I
SB2
Standby Current
V
CC
= 5.0V
CS = V
CC
10
A
I
IL
Input Leakage
V
IN
= 0V to V
CC
-0.6
3.0
A
I
OL
Output Leakage
V
IN
= 0V to V
CC
, T
AC
= 0
C to 70C
-0.6
3.0
A
V
IL
(2)
Input Low Voltage
-0.6
V
CC
x 0.3
V
V
IH
(2)
Input High Voltage
V
CC
x 0.7
V
CC
+ 0.5
V
V
OL1
Output Low Voltage
4.5V
V
CC
5.5V
I
OL
= 2.0 mA
0.4
V
V
OH1
Output High Voltage
I
OH
= -1.0 mA
V
CC
- 0.8
V
V
OL2
Output Low Voltage
2.7V
V
CC
5.5V
I
OL
= 0.15 mA
0.2
V
V
OH2
Output High Voltage
I
OH
= -100 A
V
CC
- 0.2
V
4
AT25010/020/040
0606LSEEPR03/03
Note:
1. This parameter is characterized and is not 100% tested.
AC Characteristics
Applicable over recommended operating range from T
AI
= -40C to +85C, V
CC
= As Specified, CL = 1 TTL Gate and
100 pF (unless otherwise noted).
Symbol
Parameter
Voltage
Min
Max
Units
f
SCK
SCK Clock Frequency
4.5 - 5.5
2.7 - 5.5
0
0
3.0
2.1
MHz
t
RI
Input Rise Time
4.5 - 5.5
2.7 - 5.5
2
2
s
t
FI
Input Fall Time
4.5 - 5.5
2.7 - 5.5
2
2
s
t
WH
SCK High Time
4.5 - 5.5
2.7 - 5.5
133
200
ns
t
WL
SCK Low Time
4.5 - 5.5
2.7 - 5.5
133
200
ns
t
CS
CS High Time
4.5 - 5.5
2.7 - 5.5
250
250
ns
t
CSS
CS Setup Time
4.5 - 5.5
2.7 - 5.5
250
250
ns
t
CSH
CS Hold Time
4.5 - 5.5
2.7 - 5.5
250
250
ns
t
SU
Data In Setup Time
4.5 - 5.5
2.7 - 5.5
50
50
ns
t
H
Data In Hold Time
4.5 - 5.5
2.7 - 5.5
50
100
ns
t
HD
Hold Setup Time
4.5 - 5.5
2.7 - 5.5
100
100
ns
t
CD
Hold Hold Time
4.5 - 5.5
2.7 - 5.5
200
200
ns
t
V
Output Valid
4.5 - 5.5
2.7 - 5.5
0
0
133
200
ns
t
HO
Output Hold Time
4.5 - 5.5
2.7 - 5.5
0
0
ns
t
LZ
Hold to Output Low Z
4.5 - 5.5
2.7 - 5.5
0
0
100
100
ns
t
HZ
Hold to Output High Z
4.5 - 5.5
2.7 - 5.5
100
100
ns
t
DIS
Output Disable Time
4.5 - 5.5
2.7 - 5.5
250
500
ns
t
WC
Write Cycle Time
4.5 - 5.5
2.7 - 5.5
5
10
ms
Endurance
(1)
5.0V, 25
C, Page Mode
1M
Write Cycles
5
AT25010/020/040
0606LSEEPR03/03
Serial Interface
Description
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25010/020/040
always operates as a slave.
TRANSMITTER/RECEIVER: The AT25010/020/040 has separate pins designated for
data transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
The op-code also contains address bit A8 in both the READ and WRITE instructions.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25010/020/040, and the serial output pin (SO) will remain in a high impedance state
un til the fall ing edge of CS is de tected a gain. T his will reinitiali ze the seri al
communication.
CHIP SELECT: The AT25010/020/040 is selected when the CS pin is low. When the
device is not selected, data will not be accepted via the SI pin, and the serial output pin
(SO) will remain in a high impedance state.
H O L D : T h e H O LD p i n i s u se d i n co n j un cti o n w it h the C S pi n to s e le ct th e
AT25010/020/040. When the device is selected and a serial sequence is underway,
HOLD can be used to pause the serial communication with the master device without
resetting the serial sequence. To pause, the HOLD pin must be brought low while the
SCK pin is low. To resume serial communication, the HOLD pin is brought high while the
SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored
while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations
when held high. When the WP pin is brought low, all write operations are inhibited.
WP going low while CS is still low will interrupt a write to the AT25010/020/040. If the
internal write cycle has already been initiated, WP going low will have no effect on any
write operation.
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