1
8-lead SOIC
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
Features
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
Low-voltage and Standard-voltage Operation
2.7 (V
CC
= 2.7V to 5.5V)
1.8 (V
CC
= 1.8V to 5.5V)
3 MHz Clock Rate
64-byte Page Mode and Byte Write Operation
Block Write Protection
Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
Self-timed Write Cycle (5 ms Typical)
High-reliability
Endurance: 100,000 Write Cycles
Data Retention: >200 Years
Automotive Grade, Extended Temperature and Lead-Free Devices Available
8-lead PDIP, 8-lead EIAJ SOIC, 8-lead and 16-lead JEDEC SOIC, 14-lead and 20-lead
TSSOP, 8-lead Leadless Array and 8-ball dBGA
TM
Packages
Description
The AT25128/256 provides 131,072/262,144 bits of serial electrically-erasable pro-
grammable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits
each. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The devices are available in
space saving 8-lead PDIP (AT25128/256), 8-lead EIAJ SOIC (AT25128/256), 8-lead
Rev. 0872MSEEPR4/03
*Note: Pins 3, 4 and 17, 18 are internally connected for 14-lead TSSOP socket compatibility.
SPI Serial
EEPROMs
128K (16,384 x 8)
256K (32,768 x 8)
AT25128
AT25256
Pin Configurations
Pin Name
Function
CS
Chip Select
SCK
Serial Data Clock
SI
Serial Data Input
SO
Serial Data Output
GND
Ground
VCC
Power Supply
WP
Write Protect
HOLD
Suspends Serial Input
NC
No Connect
DC
Don't Connect
20-lead TSSOP*
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
CS
SO
SO
NC
NC
WP
GND
DC
NC
NC
VCC
HOLD
HOLD
NC
NC
SCK
SI
DC
NC
8-lead PDIP
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
16-lead SOIC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CS
SO
NC
NC
NC
NC
WP
GND
VCC
HOLD
NC
NC
NC
NC
SCK
SI
14-lead TSSOP
1
2
3
4
5
6
7
14
13
12
11
10
9
8
CS
SO
NC
NC
NC
WP
GND
VCC
HOLD
NC
NC
NC
SCK
SI
8-lead Leadless Array
Bottom View
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
CS
SO
WP
GND
8-ball dBGA
Bottom View
VCC
HOLD
SCK
SI
CS
SO
WP
GND
1
2
3
4
8
7
6
5
2
AT25128/256
0872MSEEPR4/03
and 16-lead JEDEC SOIC (AT25128), 14-lead TSSOP (AT25128), 20-lead TSSOP (AT25128/256), 8-lead Leadless Array
(AT25256), and 8-ball dBGA packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to
5.5V) versions.
The AT25128/256 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data
Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no sep-
arate ERASE cycle is required before WRITE.
BLOCK WRITE protection is enabled by programming the status register with top , top or entire array of write protec-
tion. Separate program enable and program disable instructions are provided for additional data protection. Hardware data
protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may
be used to suspend any serial communication without resetting the serial sequence.
Block Diagram
Absolute Maximum Ratings*
Operating Temperature .................................. -55
C to +125
C
*NOTICE:
Stresses beyond those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions beyond those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
Storage Temperature ..................................... -65
C to +150
C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
16384/32768 x 8
3
AT25128/256
0872MSEEPR4/03
Note:
1. This parameter is characterized and is not 100% tested.
Note:
1. V
IL
and V
IH
max are reference only and are not tested.
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25
C, f = 1.0 MHz, V
CC
= +5.0V (unless otherwise noted).
Symbol
Test Conditions
Max
Units
Conditions
C
OUT
Output Capacitance (SO)
8
pF
V
OUT
= 0V
C
IN
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
V
IN
= 0V
DC Characteristics
Applicable over recommended operating range from T
AI
= -40C to +85C, V
CC
= +1.8V to +5.5V,
T
AE
= -40
C to +125
C, V
CC
= +1.8V to +5.5V(unless otherwise noted).
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
V
CC1
Supply Voltage
1.8
5.5
V
V
CC2
Supply Voltage
2.7
5.5
V
V
CC3
Supply Voltage
4.5
5.5
V
I
CC1
Supply Current
V
CC
= 5.0V at 1 MHz, SO = Open, Read
2.0
3.0
mA
I
CC2
Supply Current
V
CC
= 5.0V at 2 MHz,
SO = Open, Read, Write
3.0
5.0
mA
I
SB1
Standby Current
V
CC
= 1.8V, CS = V
CC
0.1
2.0
A
I
SB2
Standby Current
V
CC
= 2.7V, CS = V
CC
0.2
2.0
A
I
SB3
Standby Current
V
CC
= 5.0V, CS = V
CC
2.0
5.0
A
I
IL
Input Leakage
V
IN
= 0V to V
CC
-3.0
3.0
A
I
OL
Output Leakage
V
IN
= 0V to V
CC
, T
AC
= 0
C to 70
C
-3.0
3.0
A
V
IL
(1)
Input Low-voltage
-1.0
V
CC
x 0.3
V
V
IH
(1)
Input High-voltage
V
CC
x 0.7
V
CC
+ 0.5
V
V
OL1
Output Low-voltage
4.5
V
CC
5.5V
I
OL
= 3.0 mA
0.4
V
V
OH1
Output High-voltage
I
OH
= -1.6 mA
V
CC
- 0.8
V
V
OL2
Output Low-voltage
1.8V
V
CC
3.6V
I
OL
= 0.15 mA
0.2
V
V
OH2
Output High-voltage
I
OH
= -100 A
V
CC
- 0.2
V
4
AT25128/256
0872MSEEPR4/03
AC Characteristics
Applicable over recommended operating range from T
AI
= -40
C to + 85
C, T
AE
= -40
C to +125
C, V
CC
= As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
Voltage
Min
Max
Units
f
SCK
SCK Clock Frequency
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
0
0
0
3.0
2.1
0.5
MHz
t
RI
Input Rise Time
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
2
2
2
s
t
FI
Input Fall Time
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
2
2
2
s
t
WH
SCK High Time
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
150
200
800
ns
t
WL
SCK Low Time
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
150
200
800
ns
t
CS
CS High Time
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
250
250
1000
ns
t
CSS
CS Setup Time
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
100
250
1000
ns
t
CSH
CS Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
150
250
1000
ns
t
SU
Data In Setup Time
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
30
50
100
ns
t
H
Data In Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
50
50
100
ns
t
HD
Hold Setup Time
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
100
100
400
ns
t
CD
Hold Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
200
300
400
ns
t
V
Output Valid
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
0
0
0
150
200
800
ns
t
HO
Output Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
0
0
0
ns
t
LZ
Hold to Output Low Z
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
0
0
0
100
200
300
ns
5
AT25128/256
0872MSEEPR4/03
Note:
1. This parameter is characterized and is not 100% tested. Contact Atmel for further information.
Serial Interface
Description
MASTER:
The device that generates the serial clock.
SLAVE:
Because the Serial Clock pin (SCK) is always an input, the AT25128/256
always operates as a slave.
TRANSMITTER/RECEIVER: The AT25128/256 has seperate pins designated for data
transmission (SO) and reception (SI).
MSB:
The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE:
After the device is selected with CS going low, the first byte will
be received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE:
If an invalid op-code is received, no data will be shifted into the
AT25128/256, and the serial output pin (SO) will remain in a high impedance state until
the falling edge of CS is detected again. This will reinitialize the serial communication.
CHIP SELECT: The AT25128/256 is selected when the CS pin is low. When the device
is not selected, data will not be accepted via the SI pin, and the serial output pin (SO)
will remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25128/256.
When the device is selected and a serial sequence is underway, HOLD can be used to
pause the serial communication with the master device without resetting the serial
sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To
resume serial communication, the HOLD pin is brought high while the SCK pin is low
(SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin
is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations
when held high. When the WP pin is brought low and WPEN bit is "1", all write opera-
tions to the status register are inhibited. WP going low while CS is still low will interrupt a
write to the status register. If the internal write cycle has already been initiated, WP
going low will have no effect on any write operation to the status register. The WP pin
function is blocked when the WPEN bit in the status register is "0". This will allow the
user to install the AT25128/256 in a system with the WP pin tied to ground and still be
able to write to the status register. All WP pin functions are enabled when the WPEN bit
is set to "1".
t
HZ
Hold to Output High Z
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
100
200
300
ns
t
DIS
Output Disable Time
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
200
250
1000
ns
t
WC
Write Cycle Time
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
5
10
10
ms
Endurance
(1)
5.0V, 25
C, Page Mode
100K
Write Cycles
AC Characteristics (Continued)
Applicable over recommended operating range from T
AI
= -40
C to + 85
C, T
AE
= -40
C to +125
C, V
CC
= As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
Voltage
Min
Max
Units
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