1
Features
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
Data Sheet Describes Mode 0 Operation
Medium-voltage and Standard-voltage Operation
5.0 (V
CC
= 4.5V to 5.5V)
2.7 (V
CC
= 2.7V to 5.5V)
Extended Temperature Range
-40C to +125C
5 MHz Clock Rate
64-byte Page Mode and Byte Write Operation
Block Write Protection
Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software
Data Protection
Self-timed Write Cycle (5 ms max)
High Reliability
Endurance: 100,000 Write Cycles
Data Retention: >100 Years
8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP Packages
Description
The AT25128A/256A provides 131,072/262,144 bits of serial electrically-erasable pro-
grammable read-only memory (EEPROM) organized as 16,384/32,768 words of 8 bits
each. The device is optimized for use in many industrial and automotive applications
where low-power and low-voltage operation are essential. The devices are available in
space-saving 8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP packages.
The AT25128A/256A is enabled through the Chip Select pin (CS) and accessed via a
three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-
rate erase cycle is required before write.
Table 1. Pin Configurations
Pin Name
Function
CS
Chip Select
SCK
Serial Data Clock
SI
Serial Data Input
SO
Serial Data Output
GND
Ground
VCC
Power Supply
WP
Write Protect
HOLD
Suspends Serial Input
NC
No Connect
DC
Don't Connect
5088CSEEPR11/04
SPI Serial
Extended
Temperature
EEPROMs
128K (16,384 x 8)
256K (32,768 x 8)
AT25128A
AT25256A
1
2
3
4
8
7
6
5
8-Lead PDIP
1
2
3
4
8
7
6
5
8-lead SOIC
1
2
3
4
8
7
6
5
8-lead TSSOP
CS
SO
WP
GND
VCC
HOLD
SCK
SI
CS
SO
WP
GND
VCC
HOLD
SCK
SI
CS
SO
WP
GND
VCC
HOLD
SCK
SI
2
AT25128A/256A
5088CSEEPR11/04
Block write protection is enabled by programming the status register with top one-forth,
top one-half, or entire array of write protection. Separate program enable and program
disable instructions are provided for additional data protection. Hardware data protec-
tion is provided via the WP pin to protect against inadvertent write attempts to the status
register. The HOLD pin may be used to suspend any serial communication without
resetting the serial sequence
.
Figure 1. Block Diagram
Absolute Maximum Ratings*
Operating Temperature
......................................-40C to +125C
*NOTICE:
Stresses beyond those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions beyond those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
Storage Temperature
.........................................-65C to +150C
Voltage on Any Pin
with Respect to Ground
........................................ -1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
16384/32768 x 8
3
AT25128A/256A
5088CSEEPR11/04
Note:
1. This parameter is characterized and is not 100% tested.
Note:
1. Maximum value at
+125C
2. V
IL
and V
IH
max are reference only and are not tested.
Table 2. Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25
C, f = 1.0 MHz, V
CC
= +5.0V (unless otherwise noted)
Symbol
Test Conditions
Max
Units
Conditions
C
OUT
Output Capacitance (SO)
8
pF
V
OUT
= 0V
C
IN
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
V
IN
= 0V
Table 3. DC Characteristics
Applicable over recommended operating range from T
AE
=
-40C to +125C, V
CC
= +2.7V to +5.5V
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
V
CC1
Supply Voltage
2.7
5.5
V
V
CC2
Supply Voltage
4.5
5.5
V
I
CC1
Supply Current
V
CC
= 5.0V at 1 MHz, SO = Open, Read
2.0
3.0
mA
I
CC2
Supply Current
V
CC
= 5.0V at 2 MHz,
SO = Open, Read, Write
3.0
5.0
mA
I
CC3
Supply Current
V
CC
= 5.0V at 5 MHz,
SO = Open, Read, Write
3.5
6.0
mA
I
SB1
Standby Current
V
CC
= 2.7V, CS = V
CC
0.5
12.0
(1)
A
I
SB2
Standby Current
V
CC
= 5.0V, CS = V
CC
2.0
15.0
(1)
A
I
IL
Input Leakage
V
IN
= 0V to V
CC
-3.0
3.0
A
I
OL
Output Leakage
V
IN
= 0V to V
CC
-3.0
3.0
A
V
IL
(2)
Input Low-voltage
-1.0
V
CC
x 0.3
V
V
IH
(2)
Input High-voltage
V
CC
x 0.7
V
CC
+ 0.5
V
V
OL1
Output Low-voltage
3.6
V
CC
5.5V
I
OL
= 3.0 mA
0.4
V
V
OL2
Output Low-voltage
2.7
V
CC
3.6V
I
OL
= 0.15mA
0.2
V
V
OH1
Output High-voltage
3.6
V
CC
5.5V
I
OH
=
-1.6 mA
V
CC
-0.8
V
V
OH2
Output High-voltage
2.7
V
CC
3.6V
I
OH
=
-100 mA
V
CC
-0.2
V
4
AT25128A/256A
5088CSEEPR11/04
Note:
1. This parameter is characterized and is not 100% tested. Contact Atmel for further information.
Table 4. AC Characteristics
Applicable over recommended operating range from T
AE
=
-40C to +125C, V
CC
= As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol
Parameter
Voltage
Min
Max
Units
f
SCK
SCK Clock Frequency
2.75.5
0
5.0
MHz
t
RI
Input Rise Time
2.75.5
2
s
t
FI
Input Fall Time
2.75.5
2
s
t
WH
SCK High Time
2.75.5
40
ns
t
WL
SCK Low Time
2.75.5
40
ns
t
CS
CS High Time
2.75.5
80
ns
t
CSS
CS Setup Time
2.75.5
80
ns
t
CSH
CS Hold Time
2.75.5
80
ns
t
SU
Data In Setup Time
2.75.5
5
ns
t
H
Data In Hold Time
2.75.5
20
ns
t
HD
Hold Setup Time
2.75.5
40
ns
t
CD
Hold Hold Time
2.75.5
40
ns
t
V
Output Valid
2.75.5
0
40
ns
t
HO
Output Hold Time
2.75.5
0
ns
t
LZ
Hold to Output Low Z
2.75.5
0
40
ns
t
HZ
Hold to Output High Z
2.75.5
80
ns
t
DIS
Output Disable Time
2.75.5
80
ns
t
WC
Write Cycle Time
2.75.5
5
ms
Endurance
(1)
5.0V, 25
C, Page Mode
100K
Write Cycles
5
AT25128A/256A
5088CSEEPR11/04
Serial Interface
Description
MASTER: The device that generates the serial clock.
SLAVE: Because the serial clock pin (SCK) is always an input, the AT25128A/256A
always operates as a slave.
TRANSMITTER/RECEIVER: The AT25128A/256A has separate pins designated for
data transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25128A/256A, and the serial output pin (SO) will remain in a high impedance state
until the falling edge of CS is detected again. This will reinitialize the serial
communication.
CHIP SELECT: The AT25128A/256A is selected when the CS pin is low. When the
device is not selected, data will not be accepted via the SI pin, and the SO pin will
remain in a high impedance state.
HOLD: The H OL D pin is used in con ju nction w ith t he CS pin to select th e
AT25128A/256A. When the device is selected and a serial sequence is underway,
HOLD can be used to pause the serial communication with the master device without
resetting the serial sequence. To pause, the HOLD pin must be brought low while the
SCK pin is low. To resume serial communication, the HOLD pin is brought high while the
SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored
while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations
when held high. When the WP pin is brought low and WPEN bit is "1", all write opera-
tions to the status register are inhibited. WP going low while CS is still low will interrupt a
write to the status register. If the internal write cycle has already been initiated, WP
going low will have no effect on any write operation to the status register. The WP pin
function is blocked when the WPEN bit in the status register is "0". This will allow the
user to install the AT25128A/256A in a system with the WP pin tied to ground and still be
able to write to the status register. All WP pin functions are enabled when the WPEN bit
is set to "1".
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