1
Features
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
20 MHz Clock Rate
Byte Mode and 256-byte Page Mode for Program Operations
Sector Architecture:
Two Sectors with 32K Bytes Each (512K)
Four Sectors with 32K Bytes Each (1M)
128 Pages per Sector
Product Identification Mode
Low-voltage Operation
2.7 (V
CC
= 2.7V to 3.6V)
Sector Write Protection
Write Protect (WP) Pin and Write Disable Instructions for
both Hardware and Software Data Protection
Self-timed Program Cycle (60 s/Byte Typical)
Self-timed Sector Erase Cycle (1 second/Sector Typical)
Single Cycle Reprogramming (Erase and Program) for Status Register
High Reliability
Endurance: 10,000 Write Cycles Typical
8-lead JEDEC SOIC
Description
The AT25F512/1024 provides 524,288/1,048,576 bits of serial reprogrammable Flash
memory organized as 65,536/131,072 words of 8 bits each. The device is optimized
for use in many industrial and commercial applications where low-power and low-volt-
age operation are essential. The AT25F512/1024 is available in a space-saving 8-lead
JEDEC SOIC package.
The AT25F512/1024 is enabled through the Chip Select pin (CS) and accessed via a
3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All write cycles are completely self-timed.
BLOCK WRITE protection for top 1/4, top 1/2 or the entire memory array (1M) or
entire memory array (512K) is enabled by programming the status register. Separate
write enable and write disable instructions are provided for additional data protection.
Hardware data protection is provided via the WP pin to protect against inadvertent
write attempts to the status register. The HOLD pin may be used to suspend any serial
communication without resetting the serial sequence.
Rev. 1440MSEEPR7/03
SPI Serial
Memory
512K (65,536 x 8)
1M (131,072 x 8)
AT25F512
AT25F1024
Pin Configurations
Pin Name
Function
CS
Chip Select
SCK
Serial Data Clock
SI
Serial Data Input
SO
Serial Data Output
GND
Ground
VCC
Power Supply
WP
Write Protect
HOLD
Suspends Serial Input
8-lead SOIC
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
2
AT25F512/1024
1440MSEEPR7/03
Block Diagram
Absolute Maximum Ratings*
Operating Temperature .................................... -40
C to +85
C
*NOTICE:
Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature ..................................... -65
C to +150
C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
65,536 x 8
or
131,072 x 8
3
AT25F512/1024
1440MSEEPR7/03
Note:
1. This parameter is characterized and is not 100% tested.
Note:
1. V
IL
and V
IH
max are reference only and are not tested.
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25
C, f = 1.0 MHz, V
CC
= +3.6V (unless otherwise noted).
Symbol
Test Conditions
Max
Units
Conditions
C
OUT
Output Capacitance (SO)
8
pF
V
OUT
= 0V
C
IN
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
V
IN
= 0V
DC Characteristics
Applicable over recommended operating range from: T
AI
= -40
C to +85
C, V
CC
= +2.7V to +3.6V,
T
AC
= 0
C to +70
C, V
CC
= +2.7V to +3.6V (unless otherwise noted).
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
V
CC
Supply Voltage
2.7
3.6
V
I
CC1
Supply Current
V
CC
= 3.6V at 20 MHz, SO = Open Read
10.0
15.0
mA
I
CC2
Supply Current
V
CC
= 3.6V at 20 MHz, SO = Open Write
15.0
30.0
mA
I
SB
Standby Current
V
CC
= 2.7V, CS = V
CC
2.0
10.0
A
I
IL
Input Leakage
V
IN
= 0V to V
CC
-3.0
3.0
A
I
OL
Output Leakage
V
IN
= 0V to V
CC
, T
AC
= 0
C to 70
C
-3.0
3.0
A
V
IL
(1)
Input Low Voltage
-0.6
V
CC
x 0.3
V
V
IH
(1)
Input High Voltage
V
CC
x 0.7
V
CC
+ 0.5
V
V
OL
Output Low Voltage
2.7V
V
CC
3.6V
I
OL
= 0.15 mA
0.2
V
V
OH
Output High Voltage
I
OH
= -100 A
V
CC
- 0.2
V
4
AT25F512/1024
1440MSEEPR7/03
Notes:
1. The programming time for n bytes will be equal to n x t
BPC
.
2. This parameter is characterized at 3.0V, 25
C and is not 100% tested.
3. One write cycle consists of erasing a sector, followed by programming the same sector.
AC Characteristics
Applicable over recommended operating range from T
AI
= -40
C to +85
C, V
CC
= +2.7V to +3.6V
C
L
= 1 TTL Gate and 30 pF (unless otherwise noted).
Symbol
Parameter
Min
Typ
Max
Units
f
SCK
SCK Clock Frequency
0
20
MHz
t
RI
Input Rise Time
20
ns
t
FI
Input Fall Time
20
ns
t
WH
SCK High Time
20
ns
t
WL
SCK Low Time
20
ns
t
CS
CS High Time
25
ns
t
CSS
CS Setup Time
25
ns
t
CSH
CS Hold Time
25
ns
t
SU
Data In Setup Time
5
ns
t
H
Data In Hold Time
5
ns
t
HD
Hold Setup Time
15
ns
t
CD
Hold Time
15
ns
t
V
Output Valid
20
ns
t
HO
Output Hold Time
0
ns
t
LZ
Hold to Output Low Z
200
ns
t
HZ
Hold to Output High Z
200
ns
t
DIS
Output Disable Time
100
ns
t
EC
Erase Cycle Time per Sector
1.1
s
t
BPC
Byte Program Cycle Time
(1)
60
100
s
Endurance
(2)
10K
Write Cycles
(3)
5
AT25F512/1024
1440MSEEPR7/03
Serial Interface
Description
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25F512/1024
always operates as a slave.
TRANSMITTER/RECEIVER: The AT25F512/1024 has separate pins designated for
data transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25F512/1024, and the serial output pin (SO) will remain in a high impedance state
un til the fall ing edge of CS is de tected a gain. T his will reinitiali ze the seri al
communication.
CHIP SELECT: The AT25F512/1024 is selected when the CS pin is low. When the
device is not selected, data will not be accepted via the SI pin, and the serial output pin
(SO) will remain in a high impedance state.
H O L D : T h e H O LD p i n i s u se d i n co n j un cti o n w it h the C S pi n to s e le ct th e
AT25F512/1024. When the device is selected and a serial sequence is underway,
HOLD can be used to pause the serial communication with the master device without
resetting the serial sequence. To pause, the HOLD pin must be brought low while the
SCK pin is low. To resume serial communication, the HOLD pin is brought high while the
SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored
while the SO pin is in the high impedance state.
WRITE PROTECT: The 25F512/1024 has a write lockout feature that can be activated
by asserting the write protect pin (WP). When the lockout feature is activated, locked-out
sectors will be READ only. The write protect pin will allow normal read/write operations
when held high. When the WP is brought low and WPEN bit is "1", all write operations to
the status register are inhibited. WP going low while CS is still low will interrupt a write to
the status register. If the internal status register write cycle has already been initiated,
WP going low will have no effect on any write operation to the status register. The WP
pin function is blocked when the WPEN bit in the status register is "0". This will allow the
user to install the AT25F512/1024 in a system with the WP pin tied to ground and still be
able to write to the status register. All WP pin functions are enabled when the WPEN bit
is set to "1".
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