Features
Single 2.7V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
33 MHz Maximum Clock Frequency
Flexible, Uniform Erase Architecture
4-Kbyte Blocks
32-Kbyte Blocks
64-Kbyte Blocks
Full Chip Erase
Optimized Physical Sectoring for Code Shadowing and Code + Data Storage
Applications
One 16-Kbyte Top Boot Sector
Two 8-Kbyte Sectors
One 32-Kbyte Sector
Seven 64-Kbyte Sectors
Individual Sector Protection for Program/Erase Protection
Hardware Controlled Locking of Protected Sectors
Byte Program Architecture with Sequential Byte Program Mode Capability
Sequential Byte Program Mode Improves Throughput for
Programming Multiple Bytes
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
7 mA Active Read Current (Typical)
15 A Deep Power-down Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC
8-lead MLF
1.
Description
The AT26F004 is a serial interface Flash memory device designed for use in a wide
variety of high-volume consumer based applications in which program code is shad-
owed from Flash memory into embedded or external RAM for execution. The flexible
erase architecture of the AT26F004, with its erase granularity as small as 4 Kbytes,
makes it ideal for data storage as well, eliminating the need for additional data storage
EEPROM devices.
The physical sectoring and the erase block sizes of the AT26F004 have been opti-
mized to meet the needs of today's code and data storage applications. By optimizing
the size of the physical sectors and erase blocks, the memory space can be used
much more efficiently. Because certain code modules and data storage segments
must reside by themselves in their own protected sectors, the wasted and unused
memory space that occurs with large sectored and large block erase Flash memory
devices can be greatly reduced. This increased memory space efficiency allows addi-
tional code routines and data storage segments to be added while still maintaining the
same overall device density.
4-megabit
2.7-volt Only
Serial Firmware
DataFlash
Memory
AT26F004
3588ADFLSH10/05
2
3588ADFLSH10/05
AT26F004
The AT26F004 also offers a sophisticated method for protecting individual sectors against
erroneous or malicious program and erase operations. By providing the ability to individually
protect and unprotect sectors, a system can unprotect a specific sector to modify its contents
while keeping the remaining sectors of the memory array securely protected. This is useful in
applications where program code is patched or updated on a subroutine or module basis, or in
applications where data storage segments need to be modified without running the risk of errant
modifications to the program code segments.
Specifically designed for use in 3-volt systems, the AT26F004 supports read, program, and
erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for
programming and erasing.
2.
Pin Descriptions and Pinouts
Table 2-1.
Pin Descriptions
Symbol
Name and Function
Asserted
State
Type
CS
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally placed in standby mode (not Deep Power-down mode), and
the SO pin will be in a high-impedance state. When the device is deselected, data will not be
accepted on the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition
is required to end an operation. When ending an internally self-timed operation such as a program
or erase cycle, the device will not enter the standby mode until the completion of the operation.
Low
Input
SCK
SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of
data to and from the device. Command, address, and input data present on the SI pin is always
latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the
falling edge of SCK.
Input
SI
SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data input
including command and address sequences. Data on the SI pin is always latched on the rising
edge of SCK.
Input
SO
SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is
always clocked out on the falling edge of SCK.
Output
WP
WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Refer to
section
"Protection Commands and Features" on page 13
for more details on protection features
and the WP pin.
The WP pin is not internally pulled-high and cannot be left floating. If hardware controlled locking
will not be used, then the WP pin must be externally connected to V
CC
.
Low
Input
HOLD
HOLD: The HOLD pin is used to temporarily pause serial communication without deselecting
or resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the
SI pin will be ignored, and the SO pin will be in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold
condition to start. A Hold condition pauses serial communication only and does not have an effect
on internally self-timed operations such as a program or erase cycle. Please refer to section
"Hold"
on page 27
for additional details on the Hold operation.
The HOLD pin is not internally pulled-high and cannot be left floating. If the Hold function will not
be used, then the HOLD pin must be externally connected to V
CC
.
Low
Input
V
CC
DEVICE POWER SUPPLY: The V
CC
pin is used to supply the source voltage to the device.
Operations at invalid V
CC
voltages may produce spurious results and should not be attempted.
Power
GND
GROUND: The ground reference for the power supply. GND should be connected to the
system ground.
Power
5
3588ADFLSH10/05
AT26F004
5.
Device Operation
The AT26F004 is controlled by a set of instructions that are sent from a host controller, com-
monly referred to as the SPI Master. The SPI Master communicates with the AT26F004 via the
SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial
Input (SI), and Serial Output (SO).
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode
differing in respect to the SCK polarity and phase and how the polarity and phase control the
flow of data on the SPI bus. The AT26F004 supports the two most common modes, SPI modes
0 and 3. The only difference between SPI modes 0 and 3 is the polarity of the SCK signal when
in the inactive state (when the SPI Master is in standby mode and not transferring any data).
With SPI modes 0 and 3, data is always latched in on the rising edge of SCK and always output
on the falling edge of SCK.
Figure 5-1.
SPI Mode 0 and 3
6.
Commands and Addressing
A valid instruction or operation must always be started by first asserting the CS pin. After the CS
pin has been asserted, the SPI Master must then clock out a valid 8-bit opcode on the SPI bus.
Following the opcode, instruction dependent information such as address and data bytes would
then be clocked out by the SPI Master. All opcode, address, and data bytes are transferred with
the most significant bit (MSB) first. An operation is ended by deasserting the CS pin.
Opcodes not supported by the AT26F004 will be ignored by the device and no operation will be
started. The device will continue to ignore any data presented on the SI pin until the start of the
next operation (CS pin being deasserted and then reasserted). In addition, if the CS pin is deas-
serted before all eight bits of an opcode are sent to the device, then the device will simply return
to the idle state and wait for the next operation.
Addressing of the device requires a total of three bytes of information to be sent, representing
address bits A23 - A0. Since the upper address limit of the AT26F004 memory array is
07FFFFh, address bits A23 - A19 are always ignored by the device.
SCK
CS
SI
SO
MSB
LSB
MSB
LSB
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