AT28BV16
16K (2K x 8)
Battery-Voltage
TM
CMOS
E
2
PROM
Features
2.7 to 3.6V Supply
Full Read and Write Operation
Low Power Dissipation
8 mA Active Current
50
A CMOS Standby Current
Read Access Time - 250 ns
Byte Write - 3 ms
Direct Microprocessor Control
DATA Polling
READ/BUSY Open Drain Output on TSOP
High Reliability CMOS Technology
Endurance: 100,000 Cycles
Data Retention: 10 Years
Low Voltage CMOS Compatible Inputs and Outputs
JEDEC Approved Byte Wide Pinout
Commercial and Industrial Temperature Ranges
Description
The AT28BV16 is a low-power, high-performance Electrically Erasable and Program-
mable Read Only Memory with easy to use features. The AT28BV16 is a 16K mem-
ory organized as 2,048 words by 8 bits. The device is manufactured with Atmel's
reliable nonvolatile CMOS technology.
The AT28BV16 is accessed like a static RAM for the read or write cycles without the
need of external components. During a byte write, the address and data are latched
(continued)
PLCC
Top View
PDIP, SOIC
Top View
Pin Name
Function
A0 - A10
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
NC
No Connect
DC
Don't Connect
Pin Configurations
TSOP
Top View
0308A
AT28BV16
2-119
Description (Continued)
Block Diagram
Temperature Under Bias................. -55C to +125C
Storage Temperature...................... -65C to +150C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V
CC
+ 0.6V
Voltage on OE and A9
with Respect to Ground ................... -0.6V to +13.5V
*NOTICE: Stresses beyond those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Absolute Maximum Ratings*
internally, freeing the microprocessor address and data
bus for other operations. Following the initiation of a write
cycle, the device will go to a busy state and automatically
clear and write the latched data using an internal control
timer. The end of a write cycle can be determined by
DATA polling of I/O
7.
Once the end of a write cycle has
been detected, a new access for a read or a write can
begin.
The CMOS technology offers fast access times of 250 ns
at low power dissipation. When the chip is deselected the
standby current is less than 50
A.
Atmel's 28BV16 has additional features to ensure high
quality and manufacturability. The device utilizes error cor-
rection internally for extended endurance and for im-
proved data retention characteristics. An extra 32-bytes of
E
2
PROM are available for device identification or tracking.
2-120
AT28BV16
Device Operation
READ: The AT28BV16 is accessed like a Static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in a high im-
pedance state whenever CE or OE is high. This dual line
control gives designers increased flexibility in preventing
bus contention.
BYTE WRITE: Writing data into the AT28BV16 is similar
to writing into a Static RAM. A low pulse on the WE or CE
input with OE high and CE or WE low (respectively) initi-
ates a byte write. The address location is latched on the
last falling edge of WE (or CE); the new data is latched on
the first rising edge. Internally, the device performs a self-
clear before write. Once a byte write has been started, it
will automatically time itself to completion. Once a pro-
gramming operation has been initiated and for the dura-
tion of t
WC
, a read operation will effectively be a polling
operation.
DATA POLLING: The AT28BV16 provides DATA
POLLING to signal the completion of a write cycle. During
a write cycle, an attempted read of the data being written
results in the complement of that data for I/O
7
(the other
outputs are indeterminate). When the write cycle is fin-
ished, true data appears on all outputs.
READY/BUSY (TSOP only): READY/BUSY is an open
drain output; it is pulled low during the internal write cycle
and released at the completion of the write cycle.
WRITE PROTECTION: Inadvertent writes to the device
are protected against in the following ways. (a) Vcc
sense-- if Vcc is below 2.0V (typical) the write function is
inhibited. (b) Vcc power on delay-- once Vcc has reached
2.0V the device will automatically time out 5 ms (typical)
before allowing a byte write. (c) Write Inhibit-- holding any
one of OE low, CE high or WE high inhibits byte write cy-
cles.
DEVICE IDENTIFICATION: A n e x t r a 3 2 - b y t e s o f
E
2
PROM memory are available to the user for device
identification. By raising A9 to 12
0.5V and using ad-
dress locations 7E0H to 7FFH the additional bytes may be
written to or read from in the same manner as the regular
memory array.
AT28BV16
2-121
Symbol
Parameter
Condition
Min
Max
Units
I
LI
Input Load Current
V
IN
= 0V to V
CC
+ 1.0V
5
A
I
LO
Output Leakage Current
V
I/O
= 0V to V
CC
5
A
I
SB
V
CC
Standby Current CMOS
CE = V
CC
- 0.3V to V
CC
+ 1.0V
50
A
I
CC
V
CC
Active Current AC
f = 5 MHz; I
OUT
= 0 mA; CE = V
IL
8
mA
V
IL
Input Low Voltage
0.6
V
V
IH
Input High Voltage
2.0
V
V
OL
Output Low Voltage
I
OL
= 1 mA
0.3
V
I
OL
= 2 mA for RDY/BUSY
0.3
V
V
OH
Output High Voltage
I
OH
= -100
A
2.0
V
DC Characteristics
Mode
CE
OE
WE
I/O
Read
V
IL
V
IL
V
IH
D
OUT
Write
(2)
V
IL
V
IH
V
IL
D
IN
Standby/Write Inhibit
V
IH
X
(1)
X
High Z
Write Inhibit
X
X
V
IH
Write Inhibit
X
V
IL
X
Output Disable
X
V
IH
X
High Z
Notes: 1. X can be V
IL
or V
IH
.
2. Refer to AC Programming Waveforms.
Operating Modes
AT28BV16-25
AT28BV16-30
Operating
Temperature (Case)
Com.
0C - 70C
0C - 70C
Ind.
-40C - 85C
-40C - 85C
V
CC
Power Supply
2.7V to 3.6V
2.7V to 3.6V
DC and AC Operating Range
2-122
AT28BV16
Notes: 1. CE may be delayed up to t
ACC
- t
CE
after the address
transition without impact on t
ACC
.
2. OE may be delayed up to t
CE
- t
OE
after the falling
edge of CE without impact on t
CE
or by t
ACC
- t
OE
after an address change without impact on t
ACC
.
3. t
DF
is specified from OE or CE whichever occurs first
(C
L
= 5 pF).
4. This parameter is characterized and is not 100% tested.
AC Read Waveforms
(1, 2, 3, 4)
t
R
, t
F
< 20 ns
Input Test Waveforms and
Measurement Level
Output Test Load
Typ
Max
Units
Conditions
C
IN
4
6
pF
V
IN
= 0V
C
OUT
8
12
pF
V
OUT
= 0V
Pin Capacitance (f = 1 MHz, T = 25C)
(1)
Note: 1. This parameter is characterized and is not 100% tested.
AT28BV16-25
AT28BV16-30
Symbol
Parameter
Min
Max
Min
Max
Units
t
ACC
Address to Output Delay
250
300
ns
t
CE
(1)
CE to Output Delay
250
300
ns
t
OE
(2)
OE to Output Delay
100
100
ns
t
DF
(3, 4)
CE or OE High to Output Float
0
55
0
55
ns
t
OH
Output Hold from OE, CE or
Address, whichever occurred first
0
0
ns
AC Read Characteristics
AT28BV16
2-123
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