1
Features
Single 2.7V to 3.6V Supply
Hardware and Software Data Protection
Low Power Dissipation
15 mA Active Current
20
A CMOS Standby Current
Fast Read Access Time - 200 ns
Automatic Page Write Operation
Internal Address and Data Latches for 64 Bytes
Internal Control Timer
Fast Write Cycle Times
Page Write Cycle Time: 10 ms Maximum
1 to 64 Byte Page Write Operation
DATA Polling for End of Write Detection
High-reliability CMOS Technology
Endurance: 100,000 Cycles
Data Retention: 10 Years
JEDEC Approved Byte-wide Pinout
Commercial and Industrial Temperature Ranges
Description
The AT28BV64B is a high-performance electrically erasable programmable read only
memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits. Manu-
factured with Atmel's advanced nonvolatile CMOS technology, the device offers
access times to 200 ns with power dissipation of just 54 mW. When the device is
deselected, the CMOS standby current is less than 20
A.
64K (8K x 8)
Battery-Voltage
TM
Parallel EEPROM
with Page Write
and Software
Data Protection
AT28BV64B
Rev. 0299F05/28/99
3-Volt, 64K
E
2
PROM with
Data Protection
Pin Configurations
Pin Name
Function
A0 - A12
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
NC
No Connect
DC
Don't Connect
PDIP, SOIC
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
TSOP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE
A11
A9
A8
NC
WE
VCC
NC
A12
A7
A6
A5
A4
A3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
PLCC
Top View
Note:
PLCC package pins 1 and 17
are DON'T CONNECT.
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
4
3
2
1
32
31
30
14
15
16
17
18
19
20
I/O1
I/O2
GND
DC
I/O3
I/O4
I/O5
A7
A12
NC
DC
VCC
WE
NC
(continued)
AT28BV64B
2
The AT28BV64B is accessed like a static RAM for the read
or write cycle without the need for external components.
The device contains a 64 byte page register to allow writing
of up to 64 bytes simultaneously. During a write cycle, the
addresses and 1 to 64 bytes of data are internally latched,
freeing the address and data bus for other operations. Fol-
lowing the initiation of a write cycle, the device will automat-
ically write the latched data using an internal control timer.
The end of a write cycle can be detected by DATA polling of
I/O7. Once the end of a write cycle has been detected a
new access for a read or write can begin.
Atmel's AT28BV64B has additional features to ensure high
quality and manufacturability. A software data protection
mechanism guards against inadvertent writes. The device
also includes an extra 64 bytes of EEPROM for device
identification or tracking.
Block Diagram
Absolute Maximum Ratings*
Temperature Under Bias................................ -55
C to +125
C
*NOTICE:
Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Storage Temperature ..................................... -65
C to +150
C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
CC
+ 0.6V
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to +13.5V
AT28BV64B
3
Device Operation
READ: The AT28BV64B is accessed like a static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either CE or OE is high. This dual-
line control gives designers flexibility in preventing bus con-
tention in their systems.
BYTE WRITE: A low pulse on the WE or CE input with CE
or WE low (respectively) and OE high initiates a write cycle.
The address is latched on the falling edge of CE or WE,
whichever occurs last. The data is latched by the first rising
edge of CE or WE. Once a byte write has been started, it
will automatically time itself to completion. Once a pro-
gramming operation has been initiated and for the duration
of t
WC
, a read operation will effectively be a polling opera-
tion.
PA G E W R I T E : T h e p a g e w r i t e o p e r a t i o n o f t h e
AT28BV64B allows 1 to 64 bytes of data to be written into
the device during a single internal programming period. A
page write operation is initiated in the same manner as a
byte write; the first byte written can then be followed by 1 to
63 additional bytes. Each successive byte must be written
within 100
s (t
BLC
) of the previous byte. If the t
BLC
limit is
exceeded, the AT28BV64B will cease accepting data and
commence the internal programming operation. All bytes
during a page write operation must reside on the same
page as defined by the state of the A6 to A12 inputs. For
each WE high to low transition during the page write opera-
tion, A6 to A12 must be the same.
The A0 to A5 inputs specify which bytes within the page are
to be written. The bytes may be loaded in any order and
may be altered within the same load period. Only bytes
which are specified for writing will be written; unnecessary
cycling of other bytes within the page does not occur.
DATA POLLING: The AT28BV64B features DATA Polling
to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complement of the written data to be presented
on I/O7. Once the write cycle has been completed, true
data is valid on all outputs, and the next write cycle may
begin. DATA Polling may begin at anytime during the write
cycle.
TOGGLE BIT: In addition to DATA Polling, the AT28BV64B
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to
read data from the device will result in I/O6 toggling
between one and zero. Once the write has completed, I/O6
will stop toggling and valid data will be read. Reading the
toggle bit may begin at any time during the write cycle.
DATA PROTECTION: If precautions are not taken, inad-
vertent writes may occur during transitions of the host sys-
tem power supply. Atmel has incorporated both hardware
and software features that will protect the memory against
inadvertent writes.
HARDWARE PROTECTION: Hardware features protect
against inadvertent writes to the AT28BV64B in the follow-
ing ways: (a) V
CC
power-on delay--once V
CC
has reached
1.8V (typical) the device will automatically time out 10 ms
(typical) before allowing a write; (b) write inhibit
holding
any one of OE low, CE high or WE high inhibits write
cycles; and (c) noise filter
pulses of less than 15 ns (typi-
cal) on the WE or CE inputs will not initiate a write cycle.
SOFTWARE DATA PROTECTION: A software-controlled
data protection feature has been implemented on the
AT28BV64B. Software data protection (SDP) helps prevent
inadvertent writes from corrupting the data in the device.
SDP can prevent inadvertent writes during power-up and
power-down as well as any other potential periods of sys-
tem instability.
The AT28BV64B can only be written using the software
data protection feature
. A series of three write commands
to specific addresses with specific data must be presented
to the device before writing in the byte or page mode. The
same three write commands must begin each write opera-
tion. All software write commands must obey the page
mode write timing specifications. The data in the 3-byte
command sequence is not written to the device; the
addresses in the command sequence can be utilized just
like any other location in the device.
Any attempt to write to the device without the 3-byte
sequence will start the internal write timers. No data will be
written to the device; however, for the duration of t
WC
, read
operations will effectively be polling operations.
DEVICE IDENTIFICATION: An extra 64 bytes of EEPROM
memory are available to the user for device identification.
By raising A9 to 12V
0.5V and using address locations
7FC0H to 7FFFH, the additional bytes may be written to or
read from in the same manner as the regular memory
array.
AT28BV64B
5
AC Read Waveforms
(1)(2)(3)(4)
Notes:
1. CE may be delayed up to t
ACC
- t
CE
after the address transition without impact on t
ACC
.
2. OE may be delayed up to t
CE
- t
OE
after the falling edge of CE without impact on t
CE
or by t
ACC
- t
OE
after an address change
without impact on t
ACC
.
3. t
DF
is specified from OE or CE whichever occurs first (C
L
= 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
Note:
1. This parameter is characterized and is not 100% tested.
AC Read Characteristics
Symbol
Parameter
AT28BV64B-20
AT28BV64B-25
Units
Min
Max
Min
Max
t
ACC
Address to Output Delay
200
250
ns
t
CE
(1)
CE to Output Delay
200
250
ns
t
OE
(2)
OE to Output Delay
0
80
0
100
ns
t
DF
(3)(4)
CE or OE to Output Float
0
55
0
60
ns
t
OH
Output Hold from OE, CE or Address, whichever
occurred first
0
0
ns
t
R
, t
F
< 20 ns
Pin Capacitance
f = 1 MHz, T = 25C
(1)
Symbol
Typ
Max
Units
Conditions
C
IN
4
6
pF
V
IN
= 0V
C
OUT
8
12
pF
V
OUT
= 0V
PDF 
ZIP