1
Features
Fast Read Access Time 70 ns
Automatic Page Write Operation
Internal Address and Data Latches for 64 Bytes
Internal Control Timer
Fast Write Cycle Times
Page Write Cycle Time: 3 ms or 10 ms Maximum
1 to 64-byte Page Write Operation
Low Power Dissipation
80 mA Active Current
3 mA Standby Current
Hardware and Software Data Protection
DATA Polling for End of Write Detection
High Reliability CMOS Technology
Endurance: 10
4
or 10
5
Cycles
Data Retention: 10 Years
Single 5V
10% Supply
CMOS and TTL Compatible Inputs and Outputs
JEDEC Approved Byte-wide Pinout
Full Military, Commercial, and Industrial Temperature Ranges
Description
The AT28HC256 is a high-performance electrically erasable and programmable read
only memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac-
tured with Atmel's advanced nonvolatile CMOS technology, the AT28HC256 offers
256 (32K x 8)
High-speed
Parallel
EEPROM
AT28HC256
Rev. 0007I12/99
Pin Configurations
Pin Name
Function
A0 - A14
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
NC
No Connect
DC
Don't Connect
TSOP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
LCC, PLCC
Top View
Note: PLCC package pins 1 and
17 are DON'T CONNECT.
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
4
3
2
1
32
31
30
14
15
16
17
18
19
20
I/O1
I/O2
GND
DC
I/O3
I/O4
I/O5
A7
A12
A14
DC
VCC
WE
A13
PGA
Top View
(continued)
CERDIP, PDIP, FLATPACK
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
AT28HC256
2
access times to 70 ns with power dissipation of just
440 mW. When the AT28HC256 is deselected, the standby
current is less than 5 mA.
The AT28HC256 is accessed like a Static RAM for the read
or write cycle without the need for external components.
The device contains a 64-byte page register to allow writing
of up to 64 bytes simultaneously. During a write cycle, the
address and 1 to 64 bytes of data are internally latched,
freeing the addresses and data bus for other operations.
Following the initiation of a write cycle, the device will auto-
matically write the latched data using an internal control
timer. The end of a write cycle can be detected by DATA
Polling of I/O
7
. Once the end of a write cycle has been
detected a new access for a read or write can begin.
Atmel's 28HC256 has additional features to ensure high
quality and manufacturability. The device utilizes internal
error correction for extended endurance and improved data
retention characteristics. An optional software data protec-
tion mechanism is available to guard against inadvertent
writes. The device also includes an extra 64 bytes of
EEPROM for device identification or tracking.
Block Diagram
Absolute Maximum Ratings*
Temperature under Bias ................................ -55C to +125C
*NOTICE:
Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Storage Temperature ..................................... -65C to +150C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
CC
+ 0.6V
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to +13.5V
AT28HC256
3
Device Operation
READ: The AT28HC256 is accessed like a Static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either CE or OE is high. This dual-
line control gives designers flexibility in preventing bus con-
tention in their system.
BYTE WRITE: A low pulse on the WE or CE input with CE
or WE low (respectively) and OE high initiates a write cycle.
The address is latched on the falling edge of CE or WE,
whichever occurs last. The data is latched by the first rising
edge of CE or WE. Once a byte write has been started it
will automatically time itself to completion. Once a pro-
gramming operation has been initiated and for the duration
of t
W C
, a read operation will effectively be a polling
operation.
P A G E W R I T E : T h e p a g e w r i t e o p e r a t i o n o f t h e
AT28HC256 allows 1 to 64 bytes of data to be written into
the device during a single internal programming period. A
page write operation is initiated in the same manner as a
byte write; the first byte written can then be followed by 1 to
63 additional bytes. Each successive byte must be written
within 150
s (t
BLC
) of the previous byte. If the t
BLC
limit is
exceeded the AT28C256 will cease accepting data and
commence the internal programming operation. All bytes
during a page write operation must reside on the same
page as defined by the state of the A6 - A14 inputs. That is,
for each WE high to low transition during the page write
operation, A6 - A14 must be the same.
The A0 to A5 inputs are used to specify which bytes within
the page are to be written. The bytes may be loaded in any
order and may be altered within the same load period. Only
bytes which are specified for writing will be written; unnec-
essary cycling of other bytes within the page does not
occur.
DATA POLLING: The AT28HC256 features DATA Polling
to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complement of the written data to be presented
on I/O
7
. Once the write cycle has been completed, true
data is valid on all outputs, and the next write cycle may
begin. DATA Polling may begin at anytime during the write
cycle.
TOGGLE BIT: In addition to DATA Polling the AT28HC256
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to
read data from the device will result in I/O
6
toggling
between one and zero. Once the write has completed, I/O
6
will stop toggling and valid data will be read. Testing the
toggle bit may begin at any time during the write cycle.
DATA PROTECTION: If precautions are not taken, inad-
vertent writes to any 5-volt-only nonvolatile memory may
occur during transition of the host system power supply.
Atmel has incorporated both hardware and software fea-
tures that will protect the memory against inadvertent
writes.
HARDWARE PROTECTION: Hardware features protect
against inadvertent writes to the AT28HC256 in the follow-
ing ways: (a) V
CC
sense if V
CC
is below 3.8V (typical) the
write function is inhibited; (b) V
CC
power-on delay once
V
CC
has reached 3.8V the device will automatically time out
5 ms typical) before allowing a write; (c) write inhibit hold-
ing any one of OE low, CE high or WE high inhibits write
cycles; and (d) noise filter pulses of less than 15 ns (typi-
cal) on the WE or CE inputs will not initiate a write cycle.
SOFTWARE DATA PROTECTION: A software controlled
data protection feature has been implemented on the
AT28HC256. When enabled, the software data protection
(SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28HC256 is
shipped from Atmel with SDP disabled.
SDP is enabled by the host system issuing a series of three
write commands; three specific bytes of data are written to
three specific addresses (refer to "Software Data Protec-
tio n" algo rithm). After writin g the 3-byte comma nd
sequence and after t
WC
the entire AT28HC256 will be pro-
tected against inadvertent write operations. It should be
noted, that once protected the host may still perform a byte
or page write to the AT28HC256. This is done by preceding
the data to be written by the same 3-byte command
sequence.
Once set, SDP will remain active unless the disable com-
mand sequence is issued. Power transitions do not disable
SDP and SDP will protect the AT28HC256 during power-up
and power-down conditions. All command sequences must
conform to the page write timing specifications. It should
also be noted that the data in the enable and disable com-
mand sequences is not written to the device and the mem-
ory addresses used in the sequence may be written with
data in either a byte or page write operation.
After setting SDP, any attempt to write to the device without
the three byte command sequence will start the internal
write timers. No data will be written to the device; however,
for the duration of t
WC
, read operations will effectively be
polling operations.
DEVICE IDENTIFICATION: An extra 64 bytes of EEPROM
memory are available to the user for device identification.
By raising A9 to 12V
0.5V and using address locations
7FC0H to 7FFFH the additional bytes may be written to or
read from in the same manner as the regular memory
array.
OPTIONAL CHIP ERASE MODE: The entire device can
be erased using a 6-byte software code. Please see "Soft-
ware Chip Erase" application note for details.
AT28HC256
5
AC Read Waveforms
(1)(2)(3)(4)
Notes:
1. CE may be delayed up to t
ACC
- t
CE
after the address transition without impact on t
ACC
.
2. OE may be delayed up to t
CE
- t
OE
after the falling edge of CE without impact on t
CE
or by t
ACC
- t
OE
after an address change
without impact on t
ACC
.
3. t
DF
is specified from OE or CE whichever occurs first (C
L
= 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
Note:
1. This parameter is characterized and is not 100% tested.
AC Read Characteristics
Symbol
Parameter
AT28HC256-70
AT28C256-90
AT28HC256-12
Units
Min
Max
Min
Max
Min
Max
t
ACC
Address to Output Delay
70
90
120
ns
t
CE
(1)
CE to Output Delay
70
90
120
ns
t
OE
(2)
OE to Output Delay
0
35
0
40
0
50
ns
t
DF
(3)(4)
CE or OE to Output Float
0
35
0
40
0
50
ns
t
OH
Output Hold from OE, CE or Address,
whichever occurred first
0
0
0
ns
t
R
, t
F
< 5 ns
Pin Capacitance
f = 1 MHz, T = 25C
(1)
Symbol
Typ
Max
Units
Conditions
C
IN
4
6
pF
V
IN
= 0V
C
OUT
8
12
pF
V
OUT
= 0V
PDF 
ZIP