1
16-Megabit
2.7-volt Only
Serial
DataFlash
AT45DB161
Preliminary
Features
Single 2.7V - 3.6V Supply
Serial Interface Architecture
Page Program Operation
Single Cycle Reprogram (Erase and Program)
4096 Pages (528 Bytes/Page) Main Memory
Optional Page and Block Erase Operations
Two 528-Byte SRAM Data Buffers Allows Receiving of Data
while Reprogramming of Nonvolatile Memory
Internal Program and Control Timer
Fast Page Program Time 7 ms Typical
120
s Typical Page to Buffer Transfer Time
Low Power Dissipation
4 mA Active Read Current Typical
3
A CMOS Standby Current Typical
13 MHz Max Clock Frequency
Hardware Data Protection Feature
Serial Peripheral Interface (SPI) Compatible Modes 0 and 3
CMOS and TTL Compatible Inputs and Outputs
Commercial and Industrial Temperature Ranges
Description
The AT45DB161 is a 2.7-volt only, serial interface Flash memory suitable for in-sys-
tem reprogramming. Its 17,301,504 bits of memory are organized as 4096 pages of
528 bytes each. In addition to the main memory, the AT45DB161 also contains two
SRAM data buffers of 528 bytes each. The buffers allow receiving of data while a
page in the main memory is being reprogrammed. Unlike conventional Flash memo-
Rev. 0807C07/98
Pin Configurations
Pin Name
Function
CS
Chip Select
SCK
Serial Clock
SI
Serial Input
SO
Serial Output
WP
Hardware Page
Write Protect Pin
RESET
Chip Reset
RDY/BUSY
Ready/Busy
(continued)
TSOP Top View
Type 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RDY/BUSY
RESET
WP
NC
NC
VCC
GND
NC
NC
NC
CS
SCK
SI
SO
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
PLCC
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
SCK
SI
SO
NC
NC
NC
NC
NC
NC
WP
RESET
RDY/BUSY
NC
NC
NC
NC
NC
NC
4
3
2
1
32
31
30
14
15
16
17
18
19
20
NC
NC
DC
DC
NC
NC
NC
CS
NC
NC
GND
VCC
NC
NC
SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
NC
NC
CS
SCK
SI
SO
NC
NC
NC
NC
NC
NC
NC
VCC
NC
NC
WP
RESET
RDY/BUSY
NC
NC
NC
NC
NC
NC
NC
NC
CBGA Top View
Through Package
A
B
C
D
E
1
2
3
4
5
NC
NC
NC
NC
NC
VCC
WP
RESET
NC
NC
GND
RDY/BSY
SI
NC
NC
SCK
CS
SO
NC
NC
NC
NC
NC
NC
Note: PLCC package pins 16
and 17 are DON'T CONNECT
AT45DB161
Preliminary 16-
Megabit 2.7-volt
Only Serial
DataFlash
AT45DB161
2
ries that are accessed randomly with multiple address lines
and a parallel interface, the DataFlash uses a serial inter-
face to sequentially access its data. The simple serial inter-
face facilitates hardware layout, increases syste m
reliability, minimizes switching noise, and reduces package
size and active pin count. The device is optimized for use in
many commercial and industrial applications where high
density, low pin count, low voltage, and low power are
essential. Typical applications for the DataFlash are digital
voice storage, image storage, and data storage. The
device operates at clock frequencies up to 13 MHz with a
typical active read current consumption of 4 mA.
To allow for simple in-system reprogrammability, the
AT45DB161 does not require high input voltages for pro-
gramming. The device operates from a single power sup-
p ly , 2 . 7 V t o 3 . 6 V , f o r b o t h t h e p r o g r a m a n d r e a d
operations. The AT45DB161 is enabled through the chip
select pin (CS) and accessed via a three-wire interface
consisting of the Serial Input (SI), Serial Output (SO), and
the Serial Clock (SCK).
All programming cycles are self-timed, and no separate
erase cycle is required before programming.
Block Diagram
Memory Array
To provide optimal flexibility, the memory array of the
AT45DB161 is divided into three levels of granularity com-
prising of sectors, blocks, and pages. The Memory Archi-
tecture Diagram illustrates the breakdown of each level and
details the number of pages per sector and block. All pro-
gram operations to the DataFlash occur on a page by page
basis; however, the optional erase operations can be per-
formed at the block or page level.
FLASH MEMORY ARRAY
PAGE (528 BYTES)
BUFFER 2 (528 BYTES)
BUFFER 1 (528 BYTES)
I/O INTERFACE
SCK
CS
RESET
V
CC
GND
RDY/BUSY
WP
SO
SI
AT45DB161
3
Memory Architecture Diagram
Device Operation
The device operation is controlled by instructions from the
host processor. The list of instructions and their associated
opcodes are contained in Table 1 and Table 2. A valid
instruction starts with the falling edge of CS followed by the
appropriate 8-bit opcode and the desired buffer or main
memory address location. While the CS pin is low, toggling
the SCK pin controls the loading of the opcode and the
desired buffer or main memory address location through
the SI (serial input) pin. All instructions, addresses, and
data are transferred with the most significant bit (MSB) first.
Read
By specifying the appropriate opcode, data can be read
from the main memory or from either one of the two data
buffers.
MAIN MEMORY PAGE READ: A main memory read allows
the user to read data directly from any one of the 4096
pages in the main memory, bypassing both of the data buff-
ers and leaving the contents of the buffers unchanged. To
start a page read, the 8-bit opcode, 52H, is followed by 24
address bits and 32 don't care bits. In the AT45DB161, the
first two address bits are reserved for larger density
devices (see Notes on page 10), the next 12 address bits
(PA11-PA0) specify the page address, and the next 10
address bits (BA9-BA0) specify the starting byte address
within the page. The 32 don't care bits which follow the 24
address bits are sent to initialize the read operation. Fol-
lowing the 32 don't care bits, additional pulses on SCK
result in serial data being output on the SO (serial output)
pin. The CS pin must remain low during the loading of the
opcode, the address bits, and the reading of data. When
the end of a page in main memory is reached during a main
memory page read, the device will continue reading at the
beginning of the same page. A low to high transition on the
CS pin will terminate the read operation and tri-state the
SO pin.
BUFFER READ: Data can be read from either one of the
two buffers, using different opcodes to specify which buffer
to read from. An opcode of 54H is used to read data from
buffer 1, and an opcode of 56H is used to read data from
buffer 2. To perform a buffer read, the eight bits of the
opcode must be followed by 14 don't care bits, 10 address
bits, and eight don't care bits. Since the buffer size is 528-
bytes, 10 address bits (BFA9-BFA0) are required to specify
the first byte of data to be read from the buffer. The CS pin
must remain low during the loading of the opcode, the
address bits, the don't care bits, and the reading of data.
When the end of a buffer is reached, the device will con-
tinue reading back at the beginning of the buffer. A low to
Sector = 135,168 bytes
(128K + 4K)
32 Blocks
(256 Pages)
SECTOR 0
SECTOR 1
SECTOR 2
SECTOR 3
SECTOR 4
SECTOR 5
SECTOR 6
SECTOR 7
SECTOR 8
SECTOR 9
SECTOR 10
SECTOR 11
SECTOR 12
SECTOR 13
SECTOR 14
SECTOR 15
Block = 4224 bytes
(4K + 128)
8 Pages
BLOCK 0
BLOCK 1
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 510
BLOCK 511
SECTOR 0
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
BLOCK 66
BLOCK 509
SECTOR 1
Page = 528 bytes
(512 + 16)
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 4094
PAGE 4095
BLOCK 0
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 4093
BLOCK 1
SECTOR ARCHITECTURE
BLOCK ARCHITECTURE
PAGE ARCHITECTURE
AT45DB161
4
high transition on the CS pin will terminate the read opera-
tion and tri-state the SO pin.
MAIN MEMORY PAGE TO BUFFER TRANSFER: A page
of data can be transferred from the main memory to either
buffer 1 or buffer 2. An 8-bit opcode, 53H for buffer 1 and
55H for buffer 2, is followed by the two reserved bits, 12
address bits (PA11-PA0) which specify the page in main
memory that is to be transferred, and 10 don't care bits.
The CS pin must be low while toggling the SCK pin to load
the opcode, the address bits, and the don't care bits from
the SI pin. The transfer of the page of data from the main
memory to the buffer will begin when the CS pin transitions
from a low to a high state. During the transfer of a page of
data (t
XFR
), the status register can be read to determine
whether the transfer has been completed or not.
MAIN MEMORY PAGE TO BUFFER COMPARE: A page of
data in main memory can be compared to the data in buffer
1 or buffer 2. An 8-bit opcode, 60H for buffer 1 and 61H for
buffer 2, is followed by 24 address bits consisting of the two
reserved bits, 12 address bits (PA11-PA0) which specify
the page in the main memory that is to be compared to the
buffer, and 10 don't care bits. The loading of the opcode
and the address bits is the same as described previously.
The CS pin must be low while toggling the SCK pin to load
the opcode, the address bits, and the don't care bits from
the SI pin. On the low to high transition of the CS pin, the
528 bytes in the selected main memory page will be com-
pared with the 528 bytes in buffer 1 or buffer 2. During this
time (t
XFR
), the status register will indicate that the part is
busy. On completion of the compare operation, bit 6 of the
status register is updated with the result of the compare.
Program
BUFFER WRITE: Data can be shifted in from the SI pin
into either buffer 1 or buffer 2. To load data into either
buffer, an 8-bit opcode, 84H for buffer 1 or 87H for buffer 2,
is followed by 14 don't care bits and 10 address bits (BFA9-
BFA0). The 10 address bits specify the first byte in the
buffer to be written. The data is entered following the
address bits. If the end of the data buffer is reached, the
device will wrap around back to the beginning of the buffer.
Data will continue to be loaded into the buffer until a low to
high transition is detected on the CS pin.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH
BUILT-IN ERASE: Data written into either buffer 1 or buffer
2 can be programmed into the main memory. An 8-bit
opcode, 83H for buffer 1 or 86H for buffer 2, is followed by
the two reserved bits, 12 address bits (PA11-PA0) that
specify the page in the main memory to be written, and 10
additional don't care bits. When a low to high transition
occurs on the CS pin, the part will first erase the selected
page in main memory to all 1s and then program the data
stored in the buffer into the specified page in the main
memory. Both the erase and the programming of the page
are internally self timed and should take place in a maxi-
mum time of t
EP
. During this time, the status register will
indicate that the part is busy.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH-
OUT BUILT-IN ERASE: A previously erased page within
main memory can be programmed with the contents of
either buffer 1 or buffer 2. An 8-bit opcode, 88H for buffer 1
or 89H for buffer 2, is followed by the two reserved bits, 12
address bits (PA11-PA0) that specify the page in the main
memory to be written, and 10 additional don't care bits.
When a low to high transition occurs on the CS pin, the part
will program the data stored in the buffer into the specified
page in the main memory. It is necessary that the page in
main memory that is being programmed has been previ-
ously erased. The programming of the page is internally
self timed and should take place in a maximum time of t
P
.
During this time, the status register will indicate that the
part is busy.
PAGE ERASE: The optional Page Erase command can be
used to individually erase any page in the main memory
array allowing the Buffer to Main Memory Page Program
without Built-In Erase command to be utilized at a later
time. To perform a Page Erase, an opcode of 81H must be
loaded into the device, followed by two reserved bits, 12
address bits (PA11-PA0), and 10 don't care bits. The 12
address bits are used to specify which page of the memory
array is to be erased. When a low to high transition occurs
on the CS pin, the part will erase the selected page to 1s.
The erase operation is internally self-timed and should take
place in a maximum time of t
PE
. During this time, the status
register will indicate that the part is busy.
BLOCK ERASE: A block of eight pages can be erased at
one time allowing the Buffer to Main Memory Page Pro-
gram without Built-In Erase command to be utilized to
reduce programming times when writing large amounts of
data to the device. To perform a Block Erase, an opcode of
50H must be loaded into the device, followed by two
reserved bits, nine address bits (PA11-PA3), and 13 don't
care bits. The nine address bits are used to specify which
block of eight pages is to be erased. When a low to high
transition occurs on the CS pin, the part will erase the
selected block of eight pages to 1s. The erase operation is
internally self-timed and should take place in a maximum
time of t
BE
. During this time, the status register will indicate
that the part is busy.
AT45DB161
5
MAIN MEMORY PAGE PROGRAM: This operation is a
combination of the Buffer Write and Buffer to Main Memory
Page Program with Built-In Erase operations. Data is first
shifted into buffer 1 or buffer 2 from the SI pin and then pro-
grammed into a specified page in the main memory. An 8-
bit opcode, 82H for buffer 1 or 85H for buffer 2, is followed
by the two reserved bits and 22 address bits. The 12 most
significant address bits (PA11-PA0) select the page in the
main memory where data is to be written, and the next 10
address bits (BFA9-BFA0) select the first byte in the buffer
to be written. After all address bits are shifted in, the part
will take data from the SI pin and store it in one of the data
buffers. If the end of the buffer is reached, the device will
wrap around back to the beginning of the buffer. When
there is a low to high transition on the CS pin, the part will
first erase the selected page in main memory to all 1s and
then program the data stored in the buffer into the specified
page in the main memory. Both the erase and the program-
ming of the page are internally self timed and should take
place in a maximum of time t
EP
. During this time, the status
register will indicate that the part is busy.
AUTO PAGE REWRITE: This mode is only needed if multi-
ple bytes within a page or multiple pages of data are modi-
fied in a random fashion. This mode is a combination of two
operations: Main Memory Page to Buffer Transfer and
Buffer to Main Memory Page Program with Built-In Erase.
A page of data is first transferred from the main memory to
buffer 1 or buffer 2, and then the same data (from buffer 1
or buffer 2) is programmed back into its original page of
main memory. An 8-bit opcode, 58H for buffer 1 or 59H for
buffer 2, is followed by the two reserved bits, 12 address
bits (PA11-PA0) that specify the page in main memory to
be rewritten, and 10 additional don't care bits. When a low
to high transition occurs on the CS pin, the part will first
transfer data from the page in main memory to a buffer and
then program the data from the buffer back into same page
of main memory. The operation is internally self-timed and
should take place in a maximum time of t
EP
. During this
time, the status register will indicate that the part is busy.
If a sector is programmed or reprogrammed sequentially
page by page, then the programming algorithm shown in
Figure 1 is recommended. Otherwise, if multiple bytes in a
page or several pages are programmed randomly in a sec-
tor, then the programming algorithm shown in Figure 2 is
recommended.
STATUS REGISTER: The status register can be used to
determine the device's ready/busy status, the result of a
Main Memory Page to Buffer Compare operation, or the
device density. To read the status register, an opcode of
57H must be loaded into the device. After the last bit of the
opcode is shifted in, the eight bits of the status register,
starting with the MSB (bit 7), will be shifted out on the SO
pin during the next eight clock cycles. The five most-signifi-
cant bits of the status register will contain device informa-
tion, while the remaining three least-significant bits are
reserved for future use and will have undefined values.
After bit 0 of the status register has been shifted out, the
sequence will repeat itself (as long as CS remains low and
SCK is being toggled) starting again with bit 7. The data in
the status register is constantly updated, so each repeating
sequence will output new data.
Ready/busy status is indicated using bit 7 of the status reg-
ister. If bit 7 is a 1, then the device is not busy and is ready
to accept the next command. If bit 7 is a 0, then the device
is in a busy state. The user can continuously poll bit 7 of the
status register by stopping SCK once bit 7 has been output.
The status of bit 7 will continue to be output on the SO pin,
and once the device is no longer busy, the state of SO will
change from 0 to 1. There are eight operations which can
Block Erase Addressing
PA11
PA10
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Block
0
0
0
0
0
0
0
0
0
X
X
X
0
0
0
0
0
0
0
0
0
1
X
X
X
1
0
0
0
0
0
0
0
1
0
X
X
X
2
0
0
0
0
0
0
0
1
1
X
X
X
3
1
1
1
1
1
1
1
0
0
X
X
X
508
1
1
1
1
1
1
1
0
1
X
X
X
509
1
1
1
1
1
1
1
1
0
X
X
X
510
1
1
1
1
1
1
1
1
1
X
X
X
511
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