Features

2.7V to 3.6V Read/Write Operation

Fast Read Access Time - 120 ns

Internal Erase/Program Control

Sector Architecture

One 8K Words (16K bytes) Boot Block with Programming Lockout
Two 4K Words (8K bytes) Parameter Blocks
One 240K Words (480K bytes) Main Memory Array Block

Fast Sector Erase Time - 10 seconds

Byte-by-Byte or Word-By-Word Programming - 30

s Typical

Hardware Data Protection

DATA Polling For End Of Program Detection

Low-Power Dissipation

25 mA Active Current
50

A CMOS Standby Current

Typical 10,000 Write Cycles

Description

The AT49BV004(T) and AT49BV4096A(T) are 3-volt, 4-megabit Flash Memories
organized as 524,288 words of 8 bits each or 256K words of 16 bits each. Manufac-
tured with Atmel's advanced nonvolatile CMOS technology, the devices offer access
times to 120 ns with power dissipation of just 67 mW at 2.7V read. When deselected,
the CMOS standby current is less than 50

The device contains a user-enabled "boot block" protection feature. Two versions of
the feature are available: the AT49BV004/4096A locates the boot block at lowest
order addresses ("bottom boot"); the AT49BV004T/4096AT locates it at highest order
addresses ("top boot").

To allow for simple in-system reprogrammability, the AT49BV004(T)/4096A(T) does
not require high input voltages for programming. Reading data out of the device is
similar to reading from an EPROM; it has standard CE, OE, and WE inputs to avoid
bus contention. Reprogramming the AT49BV004(T)/4096A(T) is performed by first
erasing a block of data and then programming on a byte-by-byte or word-by-word
basis.

4-Megabit
(512K x 8/
256K x 16)
CMOS Flash
Memory

AT49BV004
AT49BV004T
AT49BV4096A
AT49BV4096AT
Preliminary

Rev. 1139A09/98

Pin Configurations

Pin Name

Function

A0 - A18

Addresses

Chip Enable

Output Enable

Write Enable

RESET

Reset

RDY/BUSY

Ready/Busy Output

VPP

Optional Power Supply for Faster
Program/Erase Operations

I/O0 - I/O14

Data Inputs/Outputs

I/O15(A-1)

I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)

BYTE

Selects Byte or Word Mode

No Connect

(continued)

AT49BV004(T)/4096A(T)

The device is erased by executing the erase command
sequence; the device internally controls the erase opera-
tion. The memory is divided into four blocks for erase oper-
ations. There are two 4K word parameter block sections,
the boot block, and the main memory array block. The typi-
cal number of program and erase cycles is in excess of
10,000 cycles.

The 8K word boot block section includes a reprogramming
lock out feature to provide data integrity. This feature is
enabled by a command sequence. Once the boot block
programming lockout feature is enabled, the data in the
boot block cannot be changed when input levels of 3.6
volts or less are used. The boot sector is designed to con-
tain user secure code.

For the AT49BV4096A(T), the BYTE pin controls whether
the device data I/O pins operate in the byte or word config-
uration. If the BYTE pin is set at a logic "1" or left open, the
device is in word configuration, I/O0 - I/O15 are active and
controlled by CE and OE.

If the BYTE pin is set at logic "0", the device is in byte con-
figuration, and only data I/O pins I/O0 - I/O7 are active and
controlled by CE and OE. The data I/O pins I/O8 - I/O14
are tri-stated and the I/O15 pin is used as an input for the
LSB (A-1) address function.

An optional V

pin is available to improve program/erase

times. Please contact Atmel for more information.

AT49BV4096A(T) TSOP Top View

Type 1

A15

A14

A13

A12

A11

A10

RESET

*NC/VPP

A17

A16

BYTE

GND

I/O15 / A-1

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

VCC

I/O11

I/O3

I/O10

I/O2

I/O9

I/O1

I/O8

I/O0

GND

AT49BV004(T) TSOP Top View

Type 1

A16

A15

A14

A13

A12

A11

RESET

*NC/VPP

RDY/BUSY

A18

A17

GND

A10

I/O7

I/O6

I/O5

I/O4

VCC

I/O3

I/O2

I/O1

I/O0

GND

ATBV4096A(T) SOIC (SOP)

*NC/VPP

A17

GND

I/O0

I/O8

I/O1

I/O9

I/O2

I/O10

I/O3

I/O11

RESET

A10

A11

A12

A13

A14

A15

A16

BYTE

GND

I/O15/A-1

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

VCC

*Standard device is a NC. Please contact Atmel for VPP option.

AT49BV004(T)/4096A(T)

AT49BV004(T) Block Diagram

AT49BV4096A(T) Block Diagram

Device Operation

READ: The AT49BV004(T)/4096A(T) is accessed like an
EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the
address pins is asserted on the outputs. The outputs are
put in the high impedance state whenever CE or OE is
high. This dual-line control gives designers flexibility in pre-
venting bus contention.

COMMAND SEQUENCES: When the device is first pow-
ered on it will be reset to the read or standby mode
depending upon the state of the control line inputs. In order
to perform other device functions, a series of command
sequences are entered into the device. The command

sequences are shown in the Command Definitions table
(I/O8 - I/O15 are don't care inputs for the command codes).
The command sequences are written by applying a low
pulse on the WE or CE input with CE or WE low (respec-
tively) and OE high. The address is latched on the falling
edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address loca-
tions used in the command sequences are not affected by
entering the command sequences.

RESET: A RESET input pin is provided to ease some sys-
tem applications. When RESET is at a logic high level, the

GND

CONTROL

LOGIC

DATA INPUTS/OUTPUTS

I/O0 - I/O7

DATA INPUTS/OUTPUTS

I/O0 - I/O7

RESET

ADDRESS

INPUTS

Y DECODER

INPUT/OUTPUT

BUFFERS

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES

PROGRAM DATA

LATCHES

Y-GATING

AT49BV004

AT49BV004T

Y-GATING

7FFFF

MAIN MEMORY

(480K BYTES)

BOOT BLOCK

16K BYTES

PARAMETER

BLOCK 2

8K BYTES

PARAMETER

BLOCK 1

8K BYTES

PARAMETER

BLOCK 1

8K BYTES

PARAMETER

BLOCK 2

8K BYTES

BOOT BLOCK

16K BYTES

MAIN MEMORY

480K BYTES

08000

07FFF

7C000

7BFFF

06000

05FFF

7A000
79FFF

X DECODER

04000

03FFF

78000

77FFF

00000

GND

CONTROL

LOGIC

DATA INPUTS/OUTPUTS

I/O0 - I/O7 I/O0 - I/O15

DATA INPUTS/OUTPUTS

I/O0 - I/O7 I/O0 - I/O15

RESET

ADDRESS

INPUTS

Y DECODER

INPUT/OUTPUT

BUFFERS

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES

PROGRAM DATA

LATCHES

Y-GATING

AT49BV4096A

AT49BV4096AT

Y-GATING

3FFFF

MAIN MEMORY

(240K WORDS)

BOOT BLOCK

8K WORDS

PARAMETER

BLOCK 2

4K WORDS

PARAMETER

BLOCK 1

4K WORDS

PARAMETER

BLOCK 1

4K WORDS

PARAMETER

BLOCK 2

4K WORDS

BOOT BLOCK

8K WORDS

MAIN MEMORY

(240K WORDS)

04000

03FFF

3E000

3DFFF

03000

02FFF

3D000

3CFFF

X DECODER

02000

01FFF

3C000

3BFFF

00000

AT49BV004(T)/4096A(T)

device is in its standard operating mode. A low level on the
RESET input halts the present device operation and puts
the outputs of the device in a high impedance state. When
a high level is reasserted on the RESET pin, the device
returns to the Read or Standby mode, depending upon the
state of the control inputs. By applying a 12V

0.5V input

signal to the RESET pin the boot block array can be repro-
grammed even if the boot block program lockout feature
has been enabled (see Boot Block Programming Lockout
Override section).

ERASURE: Before a byte or word can be reprogrammed, it
must be erased. The erased state of memory bits is a logi-
cal "1". The entire device can be erased by using the Chip
Erase command or individual sectors can be erased by
using the Sector Erase commands.

CHIP ERASE: The entire device can be erased at one time
by using the 6-byte chip erase software code. After the chip
erase has been initiated, the device will internally time the
erase operation so that no external clocks are required.
The maximum time to erase the chip is t

If the boot block lockout has been enabled, the Chip Erase
will not erase the data in the boot block; it will erase the
main memory block and the parameter blocks only. After
the chip erase, the device will return to the read or standby
mode.

SECTOR ERASE: As an alternative to a full chip erase, the
device is organized into four sectors that can be individually
erased. There are two 4K word parameter block sections,
one boot block, and the main memory array block. The
Sector Erase command is a six bus cycle operation. The
sector address is latched on the falling WE edge of the
sixth cycle while the 30H data input command is latched at
the rising edge of WE. The sector erase starts after the ris-
ing edge of WE of the sixth cycle. The erase operation is
internally controlled; it will automatically time to completion.
Whenever the main memory block is erased and repro-
grammed, the two parameter blocks should be erased and
reprogrammed before the main memory block is erased
again. Whenever a parameter block is erased and repro-
grammed, the other parameter block should be erased and
reprogrammed before the first parameter block is erased
again. Whenever the boot block is erased and repro-
grammed, the main memory block and the parameter
blocks should be erased and reprogrammed before the
boot block is erased again.

BYTE/WORD PROGRAMMING: Once a memory block is
erased, it is programmed (to a logical "0") on a byte-by-byte
or word-by-word basis. Programming is accomplished via
the internal device command register and is a 4 bus cycle
operation. The device will automatically generate the
required internal program pulses.

Any commands written to the chip during the embedded
programming cycle will be ignored. If a hardware reset hap-

pens during programming, the data at the location being
programmed will be corrupted. Please note that a data "0"
cannot be programmed back to a "1"; only erase operations
can convert "0"s to "1"s. Programming is completed after
the specified t

cycle time. The DATA polling feature may

also be used to indicate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 8K words. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block's usage as a write protected region is
optional to the user. The address range of the boot block is
00000H to 03FFFH for the AT49BV004; 7C000H to
7FFFFH for the AT49BV004T; 00000H to 01FFFH for the
A T 4 9 B V 4 0 9 6 A ; a n d 3 E 0 0 0 H t o 3 F F F F H f o r t h e
AT49BV4096AT.

Once the feature is enabled, the data in the boot block can
no longer be erased or programmed when input levels of
5.5V or less are used. Data in the main memory block can
still be changed through the regular programming method.
To activate the lockout feature, a series of six program
commands to specific addresses with specific data must be
performed. Please refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from the fol-
lowing address location will show if programming the boot
b l o c k i s l o c k e d o u t -- 0 0 0 0 2 H f o r A T4 9 B V 0 0 4 a n d
AT49BV4096A; 7C002 for the AT49BV004T; and 3E002H
for the AT49BV4096AT. If the data on I/O0 is low, the boot
block can be programmed; if the data on I/O0 is high, the
program lockout feature has been enabled and the block
cannot be programmed. The software product identification
exit code should be used to return to standard operation.

BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:
The user can override the boot block programming lockout
by taking the RESET pin to 12 volts during the entire chip
erase, sector erase or word programming operation. When
the RESET pin is brought back to TTL levels the boot block
programming lockout feature is again active.

PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.

AT49BV004(T)/4096A(T)

For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.

DATA POLLING: The AT49BV004(T)/4096A(T) features
DATA polling to indicate the end of a program cycle. During
a program cycle an attempted read of the last byte loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. During a
chip or sector erase operation, an attempt to read the
device will give a "0" on I/O7. Once the program or erase
cycle has completed, true data will be read from the device.
DATA polling may begin at any time during the program
cycle.

T O G G L E B I T : I n a d d i t i o n t o DATA p o l l i n g t h e
AT49BV004(T)/4096A(T) provides another method for
determining the end of a program or erase cycle. During a
program or erase operation, successive attempts to read
data from the device will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6
will stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.

READY/BUSY: For the AT49BV004(T), pin 12 is an open
drain READY/BUSY output pin which provides another
method of detecting the end of a program or erase opera-
tion. RDY/BUSY is actively pulled low during the internal
program and erase cycles and it is released at the comple-
tion of the cycle. The open drain connection allows for OR-
tying of several devices to the same RDY/BUSY line.

HARDWARE DATA PROTECTION: Hardware features
p r o t e c t a g a i n s t i n a d v e r t e n t p r o g r a m s t o t h e
AT49BV004(T)/4096A(T) in the following ways: (a) V

sense: if V

is below 1.8V (typical), the program function

is inhibited. (b) V

power on delay: once V

has reached

the V

sense level, the device will automatically time out

10 ms (typical) before programming. (c) Program inhibit:
holding any one of OE low, CE high or WE high inhibits
program cycles. (d) Noise filter: pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.

INPUT LEVELS: While operating with a 2.7V to 3.6V
power supply, the address inputs and control inputs (OE,
CE, and WE) may be driven from 0 to 5.5V without
adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to V

+ 0.6V.

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