1
Features
Single Supply Voltage, Range 2.7V to 3.6V
Single Supply for Read and Write
Fast Read Access Time - 70 ns
Internal Program Control and Timer
8K bytes Boot Block With Lockout
Fast Erase Cycle Time - 10 seconds
Byte By Byte Programming - 30
s/Byte typical
Hardware Data Protection
DATA Polling For End Of Program Detection
Low Power Dissipation
25 mA Active Current
50
A CMOS Standby Current
Typical 10,000 Write Cycles
Description
The AT49BV020 and the AT49LV020 are 3-volt-only, 2 megabit Flash memories
organized as 262,144 words of 8 bits each. Manufactured with Atmel's advanced non-
volatile CMOS technology, the devices offer access times to 70 ns with power dissipa-
tion of just 90 mW over the commercial temperature range. When the device is dese-
lected, the CMOS standby current is less than 50
A.
To allow for simple in-system reprogrammability, the AT49BV/LV020 does not require
high input voltages for programming. Three-volt-only commands determine the read
and programming operation of the device. Reading data out of the device is similar to
reading from an EPROM. Reprogramming the AT49BV/LV020 is performed by eras-
ing the entire 2 megabits of memory and then programming on a byte by byte basis.
The typical byte programming time is a fast 30
s. The end of a program cycle can be
optionally detected by the DATA polling feature. Once the end of a byte program cycle
has been detected, a new access for a read or program can begin. The typical num-
ber of program and erase cycles is in excess of 10,000 cycles.
2-Megabit
(256K x 8)
Single 2.7-volt
Battery-Voltage
TM
Flash Memory
AT49BV020
AT49LV020
Rev. 0678C03/98
(continued)
Pin Configuration
Pin Name
Function
A0 - A17
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
NC
No Connect
PLCC Top View
VSOP Top View (8 x 14mm) or
TSOP Top View (8 x 20mm)
Type 1
AT49BV020
2
The optional 8K bytes boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.
Block Diagram
Device Operation
READ: The AT49BV/LV020 is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus conten-
tion.
ERASURE: Before a byte can be reprogrammed, the 256K
bytes memory array (or 248K bytes if the boot block fea-
tured is used) must be erased. The erased state of the
memory bits is a logical "1". The entire device can be
erased at one time by using a 6-byte software code. The
software chip erase code consists of 6-byte load com-
mands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is t
EC
. If the boot block lockout feature has
been enabled, the data in the boot sector will not be
erased.
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical "0") on a
byte-by-byte basis. Please note that a data "0" cannot be
programmed back to a "1"; only erase operations can con-
vert "0"s to "1"s. Programming is accomplished via the
internal device command register and is a 4 bus cycle oper-
ation (please refer to the Command Definitions table). The
device will automatically generate the required internal pro-
gram pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified t
BP
cycle
time. The DATA polling feature may also be used to indicate
the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 8K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block's usage as a write protected region is
optional to the user. The address range of the boot block is
00000H to 01FFFH.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular pro-
gramming method. To activate the lockout feature, a series
of six program commands to specific addresses with spe-
cific data must be performed. Please refer to the Command
Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lock-
out feature has been activated and the block cannot be
programmed. The software product identification code
should be used to return to standard operation.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
AT49BV020
3
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT49BV/LV020 features DATA poll-
ing to indicate the end of a program cycle. During a pro-
gram cycle an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin. DATA polling
may begin at any time during the program cycle.
T O G G L E B I T : I n a d d i t i o n t o DATA p o l l i n g t h e
AT49BV/LV020 provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from the
device will result in I/O6 toggling between one and zero.
Once the program cycle has completed, I/O6 will stop tog-
gling and valid data will be read. Examining the toggle bit
may begin at any time during a program cycle.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT49BV/LV020
in the following ways: (a) V
CC
sense: if V
CC
is below 1.8V
(typical), the program function is inhibited. (b) Program
inhibit: holding any one of OE low, CE high or WE high
inhibits program cycles. (c) Noise filter: pulses of less than
15 ns (typical) on the WE or CE inputs will not initiate a pro-
gram cycle.
INPUT LEVELS: While operating with a 2.7V to 3.6V
power supply, the address inputs and control inputs (OE,
CE and WE) may be driven from 0 to 5.5V without
adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to V
CC
+ 0.6V.
Notes:
1. The 8K byte boot sector has the address range of 00000H to 01FFFH.
2. Either one of the Product ID exit commands can be used.
Command Definition (In Hex)
Command
Sequence
Bus
Cycles
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read
1
Addr
D
OUT
Chip Erase
6
5555
AA
2AAA
55
5555
80
5555
AA
2AAA
55
5555
10
Byte Program
4
5555
AA
2AAA
55
5555
A0
Addr
D
IN
Boot Block
Lockout
(1)
6
5555
AA
2AAA
55
5555
80
5555
AA
2AAA
55
5555
40
Product ID Entry
3
5555
AA
2AAA
55
5555
90
Product ID Exit
(2)
3
5555
AA
2AAA
55
5555
F0
Product ID Exit
(2)
1
XXXX
F0
Absolute Maximum Ratings*
Temperature Under Bias ................................ -55
C to +125
C
*NOTICE:
Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature ..................................... -65
C to +150
C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
CC
+ 0.6V
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
AT49BV020
4
Notes:
1. X can be V
IL
or V
IH
.
2. Refer to AC Programming Waveforms.
3. V
H
= 12.0V
0.5V.
4. Manufacturer Code: 1FH, Device Code: OBH
5. See details under Software Product Identification Entry/Exit.
Note:
1. In the erase mode, I
CC
is 50 mA.
DC and AC Operating Range
AT49BV/LV020-70
AT49BV/LV020-90
AT49BV/LV020-12
Operating
Temperature (Case)
Com.
0
C - 70
C
0
C - 70
C
0
C - 70
C
Ind.
-40
C - 85
C
-40
C - 85
C
-40
C - 85
C
V
CC
Power Supply
AT49LV020
3.0V to 3.6V
3.0V to 3.6V
3.0V to 3.6V
AT49BV020
2.7V to 3.6V
2.7V to 3.6V
2.7V to 3.6V
Operating Modes
Mode
CE
OE
WE
Ai
I/O
Read
V
IL
V
IL
V
IH
Ai
D
OUT
Program
(2)
V
IL
V
IH
V
IL
Ai
D
IN
Standby/Write Inhibit
V
IH
X
(1)
X
X
High Z
Program Inhibit
X
X
V
IH
Program Inhibit
X
V
IL
X
Output Disable
X
V
IH
X
High Z
Product Identification
Hardware
V
IL
V
IL
V
IH
A1 - A17 = V
IL
, A9 = V
H
(3)
A0 = V
IL
Manufacturer Code
(4)
A1 - A17 = V
IL
, A9 = V
H
,
(3)
A0 = V
IH
Device Code
(4)
Software
(5)
A0 = V
IL
, A1 - A17=V
IL
Manufacturer Code
(4)
A0 = V
IH
, A1 - A17=V
IL
Device Code
(4)
DC Characteristics
Symbol
Parameter
Condition
Min
Max
Units
I
LI
Input Load Current
V
IN
= 0V to V
CC
10
A
I
LO
Output Leakage Current
V
I/O
= 0V to V
CC
10
A
I
SB1
V
CC
Standby Current CMOS
CE = V
CC
- 0.3V to V
CC
50
A
I
SB2
V
CC
Standby Current TTL
CE = 2.0V to V
CC
1
mA
I
CC
(1)
V
CC
Active Current
f = 5 MHz; I
OUT
= 0 mA
25
mA
V
IL
Input Low Voltage
0.6
V
V
IH
Input High Voltage
2.0
V
V
OL
Output Low Voltage
I
OL
= 2.1 mA
0.45
V
V
OH
Output High Voltage
I
OH
= -100
A; V
CC
= 3.0V
2.4
V
AT49BV020
5
AC Read Waveforms
(1)(2)(3)(4)
Notes:
1.
CE may be delayed up to t
ACC
- t
CE
after the address transition without impact on t
ACC
.
2.
OE may be delayed up to t
CE
- t
OE
after the falling edge of CE without impact on t
CE
or by t
ACC
- t
OE
after an address change
without impact on t
ACC
.
3.
t
DF
is specified from OE or CE whichever occurs first (C
L
= 5pF).
4.
This parameter is characterized and is not 100% tested.
Note:
1. This parameter is characterized and is not 100% tested.
AC Read Characteristics
Symbol
Parameter
AT49BV/LV020
Units
-70
-90
-12
Min
Max
Min
Max
Min
Max
t
ACC
Address to Output Delay
70
90
120
ns
t
CE
(1)
CE to Output Delay
70
90
120
ns
t
OE
(2)
OE to Output Delay
0
35
0
40
0
50
ns
t
DF
(3)(4)
CE or OE to Output Float
0
25
0
25
0
30
ns
t
OH
Output Hold from OE, CE or Address,
whichever occurred first
0
0
0
ns
ADDRESS
CE
OUTPUT
OE
OUTPUT VALID
t
ACC
ADDRESS VALID
HIGH Z
t
DF
t
CE
t
OH
t
OE
Pin Capacitance
(f = 1 MHz, T = 25
C)
(1)
Typ
Max
Units
Conditions
C
IN
4
6
pF
V
IN
= 0V
C
OUT
8
12
pF
V
OUT
= 0V
Output Test Load
100 pF
1.3K
1.8K
3.0V
OUTPUT
PIN
Input Test Waveforms and Measurement Level
AC
DRIVING
LEVELS
AC
MEASUREMENT
LEVEL
0.4V
1.5V
2.4V
t
R
, t
F
< 5 ns
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