4-193

203Features

Compatible with MCS-51TM Products

20K Bytes of Reprogrammable Flash Memory

 Endurance: 1,000 Write/Erase Cycles

Fully Static Operation: 0 Hz to 12 MHz

Three-Level Program Memory Lock

256 x 8-bit Internal RAM

32 Programmable I/O Lines

Three 16-bit Timer/Counters

Eight Interrupt Sources

Low Power Idle and Power Down Modes

2.7V to 6.0V Operating Range

Description

The AT89LV55 is a low-voltage, low-power CMOS 8-bit microcomputer with 20K
bytes of Flash programmable and erasable read only memory. The device is manu-
factured using Atmel's high density nonvolatile memory technology and is compatible
with the industry standard 80C51 instruction set and pinout. The on-chip Flash allows
the program memory to be reprogrammed. By combining a versatile 8-bit CPU with
Flash on a monolithic chip, the Atmel AT89LV55 is a powerful microcomputer which
provides a highly flexible and cost effective solution to many embedded control appli-
cations.

0811B-B12/97

8-Bit
Microcontroller
with 20K Bytes
Flash

AT89LV55

Pin Configurations

TQFP

PDIP

PLCC

(continued)

AT89LV55

4-195

The AT89LV55 provides the following standard features:
20K bytes of Flash, 256-bytes of RAM, 32 I/O lines, three
16-bit timer/counters, a six-vector two-level interrupt archi-
tecture, a full duplex serial port, on-chip oscillator, and
clock circuitry. In addition, the AT89LV55 is designed with
static logic for operation down to zero frequency and sup-
ports two software selectable power saving modes. The
Idle Mo de stops the CPU while allowing the RAM ,
timer/counters, serial port, and interrupt system to continue
functioning. The Power Down Mode saves the RAM con-
tents but freezes the oscillator, disabling all other chip func-
tions until the next hardware reset. The low-voltage option
saves power and operates with a 2.7-volt power supply.

Pin Description

Supply voltage.

GND
Ground.

Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as high-
impedance inputs.

Port 0 can also be configured to be the multiplexed low-
order address/data bus during accesses to external pro-
gram and data memory. In this mode, P0 has internal pul-
lups.

Port 0 also receives the code bytes during Flash program-
ming and outputs the code bytes during program verifica-
tion. External pullups are required during program verifica-
tion.

Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pullups.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source
current (I

) because of the internal pullups.

In addition, P1.0 and P1.1 can be configured to be the
timer/counter 2 external count input (P1.0/T2) and the
timer/counter 2 trigger input (P1.1/T2EX), respectively, as
shown in the following table.

Port 1 also receives the low-order address bytes during
Flash programming and verification.

Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pullups.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source
current (I

) because of the internal pullups.

Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @
DPTR). In this application, Port 2 uses strong internal pul-
lups when emitting 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @ RI), Port 2
emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some
control signals during Flash programming and verification.

Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (I

) because of the pullups.

Port 3 also serves the functions of various special features
of the AT89LV55, as shown in the following table.

Port 3 also receives the highest-order address bit and
some control signals for Flash programming and verifica-
tion.

RST
Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device.

Port Pin

Alternate Functions

P1.0

T2 (external count input to Timer/Counter 2),
clock-out

P1.1

T2EX (Timer/Counter 2 capture/reload trigger and
direction control)

Port Pin

Alternate Functions

P3.0

RXD (serial input port)

P3.1

TXD (serial output port)

P3.2

INT0 (external interrupt 0)

P3.3

INT1 (external interrupt 1)

P3.4

T0 (timer 0 external input)

P3.5

T1 (timer 1 external input)

P3.6

WR (external data memory write strobe)

P3.7

RD (external data memory read strobe)

AT89LV55

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ALE/PROG
Address Latch Enable is an output pulse for latching the
low byte of the address during accesses to external mem-
ory. This pin is also the program pulse input (PROG) during
Flash programming.

In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency and may be used for external tim-
ing or clocking purposes. Note, however, that one ALE
pulse is skipped during each access to external data mem-
ory.

If desired, ALE operation can be disabled by setting bit 0 of
SFR location 8EH. With the bit set, ALE is active only dur-
ing a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no
effect if the microcontroller is in external execution mode.

PSEN
Program Store Enable is the read strobe to external pro-
gram memory.

When the AT89LV55 is executing code from external pro-
gram memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during
each access to external data memory.

EA/V

External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external pro-
gram memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be
internally latched on reset.

EA should be strapped to V

for internal program execu-

tions.

This pin also receives the 12-volt programming enable volt-
age (V

) during 12-volt Flash programming.

XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.

XTAL2
Output from the inverting oscillator amplifier.

Special Function Registers

A map of the on-chip memory area called the Special Func-
tion Register (SFR) space is shown in Table 1.

Note that not all of the addresses are occupied, and unoc-
cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indetermi-
nate effect.

User software should not write 1s to these unlisted loca-
tions, since they may be used in future products to invoke
new features. In that case, the reset or inactive values of
the new bits will always be 0.

Timer 2 Registers: Control and status bits are contained in
registers T2CON (shown in Table 2) and T2MOD (shown in
Table 4) for Timer 2. The register pair (RCAP2H, RCAP2L)
are the Capture/Reload registers for Timer 2 in 16-bit cap-
ture mode or 16-bit auto-reload mode.

Interrupt Registers: The individual interrupt enable bits
are in the IE register. Two priorities can be set for each of
the six interrupt sources in the IP register.

Data Memory

The AT89LV55 implements 256 bytes of on-chip RAM. The
upper 128 bytes occupy a parallel address space to the
Special Function Registers. That means the upper 128
bytes have the same addresses as the SFR space but are
physically separate from SFR space.

When an instruction accesses an internal location above
address 7FH, the address mode used in the instruction
specifies whether the CPU accesses the upper 128 bytes
of RAM or the SFR space. Instructions that use direct
addressing access SFR space.

For example, the following direct addressing instruction
accesses the SFR at location 0A0H (which is P2).

MOV 0A0H, #data

Instructions that use indirect addressing access the upper
128 bytes of RAM. For example, the following indirect
addressing instruction, where R0 contains 0A0H, accesses
the data byte at address 0A0H, rather than P2 (whose
address is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect
addressing, so the upper 128 bytes of data RAM are avail-
able as stack space.

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