1
AT91
ARM
Thumb
Microcontrollers
AT91M43300
Features
Utilizes the ARM7TDMI
TM
ARM
Thumb
Processor Core
High-performance 32-bit RISC Architecture
High-density 16-bit Instruction Set
Leader in MIPS/Watt
Embedded ICE (In-Circuit Emulation)
3K Bytes Internal RAM
Fully-programmable External Bus Interface (EBI)
Maximum External Address Space of 64M Bytes
Up to 8 Chip Selects
Software-programmable 8/16-bit External Data Bus
8-channel Peripheral Data Controller
8-level Priority, Individually-maskable, Vectored Interrupt Controller
5 External Interrupts, including a High-priority, Low-latency Interrupt Request
58 Programmable I/O Lines
6-channel 16-bit Timer/Counter
6 External Clock Inputs
2 Multi-purpose I/O Pins per Channel
3 USARTs
2 Dedicated Peripheral Data Controller (PDC) Channels per USART
Support for up to 9-bit Data Transfers
Master/Slave SPI Interface
2 Dedicated Peripheral Data Controller (PDC) Channels
8- to 16-bit Programmable Data Length
4 External Slave Chip Selects
Programmable Watchdog Timer
Power Management Controller (PMC)
CPU and Peripherals can be Deactivated Individually
IEEE 1149.1 JTAG Boundary Scan on all Active Pins
Fully Static Operation: 0 Hz to 25 MHz (12 MHz @ 1.8V)
1.8V to 3.6V Core Operating Voltage Range
2.7V to 5.5V I/O Operating Voltage Range
-40
to +85C Operating Temperature Range
Available in a 144-ball PBGA Package
Description
The AT91M43300 is a member of the Atmel AT91 16/32-bit Microcontroller family,
which is based on the ARM7TDMI processor core.
This processor has a high-performance 32-bit RISC architecture with a high-density
16-bit instruction set and features very low power consumption. In addition, a large
number of internally banked registers result in very fast exception handling, making
the device ideal for real-time control applications. The AT91 ARM-based MCU family
also features Atmel's high-density, in-system programmable, nonvolatile memory
technology.
The AT91M43300 has a direct connection to off-chip memory, including Flash,
through the fully-programmable External Bus Interface.
The AT91M43300 is manufactured using Atmel's high-density CMOS technology. By
combining the ARM7TDMI microcontroller core with an on-chip SRAM, and a wide
range of peripheral functions on a monolithic chip, the AT91M43300 provides a highly-
flexible and cost-effective solution to many compute-intensive multi-processor appli-
cations.
The compact BGA package reduces required board space to an absolute minimum.
Rev. 1322A10/99
AT91M43300
2
Pin Description
Table 1. AT91M43300 Pin Description
Module
Name
Function
Type
Active
Level
Comments
EBI
A0 - A23
Address Bus
Output
All valid after reset
D0 - D15
Data Bus
I/O
CS4 - CS7
Chip Select
Output
High
A23 - A20 after reset
NCS0 - NCS3
Chip Select
Output
Low
NWR0
Lower Byte 0 Write Signal
Output
Low
Used in Byte Write option
NWR1
Lower Byte 1 Write Signal
Output
Low
Used in Byte Write option
NRD
Read Signal
Output
Low
Used in Byte Write option
NWE
Write Enable
Output
Low
Used in Byte Select option
NOE
Output Enable
Output
Low
Used in Byte Select option
NUB
Upper Byte Select (16-bit SRAM)
Output
Low
Used in Byte Select option
NLB
Lower Byte Select (16-bit SRAM)
Output
Low
Used in Byte Select option
NWAIT
Wait Input
Input
Low
BMS
Boot Mode Select
Input
Sampled during reset
AIC
IRQ0 - IRQ3
External Interrupt Request
Input
PIO-controlled after reset
FIQ
Fast External Interrupt Request
Input
PIO-controlled after reset
Timer
TCLK0 - TCLK5
Timer External Clock
Input
PIO-controlled after reset
TIOA0 - TIOA5
Multi-purpose Timer I/O Pin A
I/O
PIO-controlled after reset
TIOB0 - TIOB5
Multi-purpose Timer I/O Pin B
I/O
PIO-controlled after reset
USART
SCK0 - SCK2
External Serial Clock
I/O
PIO-controlled after reset
TXD0 - TXD2
Transmit Data Output
Output
PIO-controlled after reset
RXD0 - RXD2
Receive Data Input
Input
PIO-controlled after reset
SPI
SPCK
SPI Clock
I/O
PIO-controlled after reset
MISO
Master In Slave Out
I/O
PIO-controlled after reset
MOSI
Master Out Slave In
I/O
PIO-controlled after reset
NSS
Slave Select
Input
Low
PIO-controlled after reset
NPCS0 - NPCS3
Peripheral Chip Select
Output
Low
PIO-controlled after reset
PIO
PA0 - PA29
Programmable I/O Port A
I/O
Input after reset
PB0 - PB27
Programmable I/O Port B
I/O
Input after reset
WD
NWDOVF
Watchdog Timer Overflow
Output
Low
Open drain
Clock
MCKI
Master Clock Input
Input
Schmitt trigger
MCKO
Master Clock Output
Output
Reset
NRST
Hardware Reset Input
Input
Low
Schmitt trigger, internal pull-up
JTAG/ICE
JTAGSEL
Selects between JTAG and ICE mode
Input
High enables IEEE 1149.1 JTAG
boundary scan
TMS
Test Mode Select
Input
Schmitt trigger, internal pull-up
TDI
Test Data In
Input
Schmitt trigger, internal pull-up
TDO
Test Data Out
Output
TCK
Test Clock
Input
Schmitt trigger, internal pull-up
NTRST
Test Reset Input
Input
Low
Schmitt trigger, internal pull-up
Power
VDDIO
I/O Power
Power
3V or 5V nominal supply
VDDCORE
Core Power
Power
2.0V or 3V nominal supply
GND
Ground
Ground
Emulation
NTRI
Tristate Mode Enable
Input
Low
Sampled during reset
AT91M43300
3
Pin Configuration
Figure 1. AT91M43300 in 144-ball BGA Package (top view)
NUB
NWR1
NOE
NRD
TCK
TDI
VDDIO
PB17
MCKO
GND
VDDIO
PB7
PB5
NCS0
NWE
NWR0
VDDIO
TDO
NTRST
MCKI
PB15
PB8
PB6
GND
NCS2
NCS1 VDDCORE NCS3
GND
NRST
PB10
PB14
PB9
VDDCORE
A3
A2
GND
PB13
PB16
PB12
VDDIO
GND
A10
PA7
TIOA5
NWDOVF VDDIO
A9
A14
A8
PB23
TIOA1
PA8
TIOB5
PA19
RXD1
A15
VDDIO
A21
CS6
PB27
TIOB2
PB25
TCLK2
PA25
MOSI
A18
D0
GND
PB20
TIOA0
PA12
IRQ3
PA11
IRQ2
A20
CS7
A19
D3
PA2
TIOB3
PA3
TCLK4
PA20
SCK2
D4
VDDIO VDDCORE
PA5
TIOB4
PA16
RXD0
PA17
SCK1
D5
D7
GND
VDDIO
PA10
IRQ1
VDDIO
D6
D8
D9
GND
PA9
IRQ0
PA13
FIQ
1
2
3
4
5
6
7
8
9
10
11
12
A
B
C
D
E
F
G
H
J
K
L
M
PB4
PB3
PB2
PB1
PB11
PB0
GND
GND
PA22
RXD2
GND
GND
GND
PA23
SPCK
PA29
NPCS3
PA27
NPCS1
PA28
NPCS2
PA24
MISO
PA26
NPCS0 /NSS
GND
PA21
TXD2
VDDCORE
PA18 / TXD1
NTRI
PA14
SCK0
PA15
TXD0
NWAIT
A5
PB18
BMS
A4
A1
A6
A12
A7
A0
A13
A17
A11
D2
A22
CS5
A23
CS4
D1
D11
D12
D10
D14
PB24
TIOB1
D15
VDDIO
PA0
TCLK3
PB22
TCLK1
GND
PA1
TIOA3
TMS
JTAGSEL
PB19
TCLK0
A16
D13
PB21
TIOB0
PB26
TIOA2
PA4
TIOA4
PA6
TCLK5
AT91M43300
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Architectural Overview
The AT91M43300 architecture consists of two main buses,
the Advanced System Bus (ASB) and the Advanced
Peripheral Bus (APB). The ASB is designed for maximum
performance. It interfaces the processor with the on-chip
32-bit memories and the external memories and devices by
means of the External Bus Interface (EBI). The APB is
designed for accesses to on-chip peripherals and is opti-
mized for low power consumption. The AMBA Bridge pro-
vides an interface between the ASB and the APB.
An on-chip Peripheral Data Controller (PDC) transfers data
between the on-chip USARTs/SPI and the on- and off-chip
memories without processor intervention. Most importantly,
the PDC removes the processor interrupt handling over-
head and significantly reduces the number of clock cycles
required for a data transfer. It can transfer up to 64K contig-
uous bytes without reprogramming the starting address. As
a re sult, the perfo rm ance of t he microcontrolle r is
increased and the power consumption reduced.
The AT91M43300 peripherals are designed to be easily
programmable with a minimum number of instructions.
Each peripheral has a 16K-byte address space allocated in
the upper 3M bytes of the 4G byte address space. Except
for the interrupt controller, the peripheral base address is
the lowest address of its memory space. The peripheral
register set is composed of control, mode, data, status and
interrupt registers.
To maximize the efficiency of bit manipulation, frequently-
written registers are mapped into three memory locations.
The first address is used to set the individual register bits,
the second resets the bits and the third address reads the
value stored in the register. A bit can be set or reset by writ-
ing a one to the corresponding position at the appropriate
address. Writing a zero has no effect. Individual bits can
thus be modified without having to use costly read-modify-
write and complex bit manipulation instructions.
All of the external signals of the on-chip peripherals are
under the control of the Parallel I/O controller. The PIO
controller can be programmed to insert an input filter on
each pin or generate an interrupt on a signal change. After
reset, the user must carefully program the PIO Controller in
order to define which peripheral signals are connected with
off-chip logic.
The ARM7TDMI processor operates in little-endian mode
in the AT91M43300 microcontroller. The processor's inter-
nal architecture and the ARM and Thumb instruction sets
are described in the ARM7TDMI datasheet. The memory
map and the on-chip peripherals are described in the
datasheet entitled "AT91M63200 Datasheet" (Literature
No. 1028). Electrical characteristics for the AT91M43300
are documented in the datasheet "AT91M63200 Electrical
and Mechanical Characteristics" (Literature No. 1090).
The ARM standard In-Circuit Emulation debug interface is
supported via the ICE port of the AT91M43300 via the
JTAG/ICE port when JTAGSEL is low. IEEE JTAG bound-
ary scan is supported via the JTAG/ICE port when JTAG-
SEL is high.
PDC: Peripheral Data Controller
The AT91M43300 has an 8-channel PDC dedicated to the
three on-chip USARTs and to the SPI. One PDC channel is
connected to the receiving channel and one to the transmit-
ting channel of each peripheral.
The user interface of a PDC channel is integrated in the
memory space of each USART channel and in the memory
space of the SPI. It contains a 32-bit address pointer regis-
ter and a 16-bit count register. When the programmed data
is transferred, an end-of-transfer interrupt is generated by
the corresponding peripheral. See the USART section and
the SPI section for more details on PDC operation and pro-
gramming.
Power Supplies
The AT91M43300 has two kinds of power supply pins:
VDDCORE pins, which power the chip core
VDDIO pins, which power the I/O lines
This allows core power consumption to be reduced by sup-
plying it with a lower voltage than the I/O lines. The
VDDCORE pins must never be powered at a voltage
greater than the supply voltage applied to the VDDIO pins.
Typical supported voltage combinations are shown in the
following table:
Pins
Typical Supply Voltages
VDDCORE
3.0V or 3.3V
3.0V or 3.3V
2.0V
VDDIO
5.0V
3.0V or 3.3V
3.0V or 3.3V
AT91M43300
5
Block Diagram
Figure 2. AT91M43300
ARM7TDMI
Core
Embedded
ICE
Reset
EBI: External
Bus Interface
Internal RAM
1K Bytes
ASB
Controller
AIC: Advanced
Interrupt Controller
AMBA Bridge
TC: Timer/
Counter
Block 0
TC0
TC1
TC2
USART0
USART1
2 PDC
Channels
2 PDC
Channels
PMC: Power
Management
Controller
APB
ASB
P
I
O
P
I
O
NRST
D0-D15
A1-A19
A0/NLB
NRD/NOE
NWR0/NWE
NWR1/NUB
NWAIT
NCS0
NCS1
NCS2
NCS3
PB19/TCLK0
PB22/TCLK1
PB25/TCLK2
PB20/TIOA0
PB21/TIOB0
PB23/TIOA1
PB24/TIOB1
PB26/TIOA2
PB27/TIOB2
MCKI
PB17/MCKO
PA10/IRQ1
PA11/IRQ2
PA12/IRQ3
PA13/FIQ
PA14/SCK0
PA15/TXD0
PA16/RXD0
PA17/SCK1
PA18/TXD1/NTRI
PA19/RXD1
PB11
PB12
PB13
PB14
PB15
PB16
TMS
TDO
TDI
TCK
NTRST
USART2
2 PDC
Channels
PA20/SCK2
PA21/TXD2
PA22/RXD2
SPI: Serial
Peripheral
Interface
WD: Watchdog
Timer
NWDOVF
TC: Timer/
Counter
Block 1
TC0
TC1
TC2
PA0/TCLK3
PA3/TCLK4
PA6/TCLK5
PA1/TIOA3
PA2/TIOB3
PA4/TIOA4
PA5/TIOB4
PA7/TIOA5
PA8/TIOB5
PB10
PB4
PB5
PB6
PB7
PB8
PB9
PB3
PB0
PB1
PB2
Clock
PA9/IRQ0
PA24/MISO
PA25/MOSI
PA26/NPCS0/NSS
PA27/NPCS1
PA23/SPCK
PA28/NPCS2
PA29/NPCS3
A20/CS7
A21/CS6
A22/CS5
A23/CS4
PB18/BMS
Chip ID
PIOA: Parallel I/O
Controller A
PIOB: Parallel I/O
Controller B
EBI User
Interface
2 PDC
Channels
JT
AGSEL
JT
AG
JTAGSEL
Internal RAM
2K Bytes
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