1
Features
Multichip Module Containing Field Programmable System Level Integrated Circuit
(FPSLIC
TM
) and Secure Configuration EEPROM Memory
512 Kbits to 1 Mbit of Configuration Memory with Security Protection and In-System
Programming (ISP)
Field Programmable System Level Integrated Circuit (FPSLIC)
AT40K SRAM-based FPGA with Embedded High-performance RISC AVR
Core and
Extensive Data and Instruction SRAM
5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM
TM
2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM
High-performance DSP Optimized FPGA Core Cell
Dynamically Reconfigurable In-System FPGA Configuration Access Available
On-chip from AVR Microcontroller Core to Support Cache Logic
Designs
Very Low Static and Dynamic Power Consumption Ideal for Portable and
Handheld Applications
Patented AVR Enhanced RISC Architecture
120+ Powerful Instructions Most Single Clock Cycle Execution
High-performance Hardware Multiplier for DSP-based Systems
Approaching 1 MIPS per MHz Performance
C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers
Low-power Idle, Power-save, and Power-down Modes
100 A Standby and Typical 2-3 mA per MHz Active
Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM
Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM
Up to 16 Kbytes x 8 Internal 15 ns Data SRAM
JTAG (IEEE Std. 1149.1 Compliant) Interface
Extensive On-chip Debugging Support
Limited Boundary-scan Capabilities According to the JTAG Standards (AVR Ports)
AVR Fixed Peripherals
Industry-standard 2-wire Serial Interface
Two Programmable Serial UARTs
Two 8-bit Timer/Counters with Separate Prescaler and PWM
One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture
Modes and Dual 8-, 9- or 10-bit PWM
Support for FPGA Custom Peripherals
AVR Peripheral Control Up to 16 Decoded AVR Address Lines Directly
Accessible to FPGA
FPGA Macro Library of Custom Peripherals
Up to 16 FPGA Supplied Internal Interrupts to AVR
Up to Four External Interrupts to AVR
8 Global FPGA Clocks
Two FPGA Clocks Driven from AVR Logic
FPGA Global Clock Access Available from FPGA Core
Multiple Oscillator Circuits
Programmable Watchdog Timer with On-chip Oscillator
Oscillator to AVR Internal Clock Circuit
Software-selectable Clock Frequency
Oscillator to Timer/Counter for Real-time Clock
V
CC
: 3.0V - 3.6V
5V Tolerant I/O
3.3V 33 MHz PCI Compliant FPGA I/O
20 mA Sink/Source High-performance I/O Structures
All FPGA I/O Individually Programmable
High-performance, Low-power 0.35 CMOS Five-layer Metal Process
State-of-the-art Integrated PC-based Software Suite including Co-verification
Rev. 2314DFPSLI2/04
Secure
5K - 40K Gates
of AT40K FPGA
with 8-bit
Microcontroller,
up to 36 Kbytes
of SRAM and
On-chip
Program
Storage
EEPROM
AT94S
Secure Series
Programmable
SLI
2
AT94S Secure Family
2314DFPSLI2/04
Description
The AT94S Series (Secure FPSLIC family) shown in Table 1 is a combination of the
popular Atmel AT40K Series SRAM FPGAs, the AT17 Series Configuration Memories
and the high-performance Atmel AVR 8-bit RISC microcontroller with standard peripher-
als. Extensive data and instruction SRAM as well as device control and management
logic are included in this multi-chip module (MCM).
The embedded AT40K FPGA core is a fully 3.3V PCI-compliant, SRAM-based FPGA
with distributed 10 ns programmable synchronous/asynchronous, dual-port/single-port
SRAM, 8 global clocks, Cache Logic ability (partially or fully reconfigurable without loss
of data) and 5,000 to 40,000 usable gates.
Table 1. The AT94S Series Family
Device
AT94S05AL
AT94S10AL
AT94S40AL
Configuration Memory Size
1 Mbit
1 Mbit
1 Mbit
FPGA Gates
5K
10K
40K
FPGA Core Cells
256
576
2304
FPGA SRAM Bits
2048
4096
18432
FPGA Registers (Total)
436
846
2862
Maximum FPGA User I/O
95
143
287
AVR Programmable I/O Lines
8
16
16
Program SRAM Bytes
4K - 16K
20K - 32K
20K - 32K
Data SRAM Bytes
4K - 16K
4K - 16K
4K - 16K
Hardware Multiplier (8-bit)
Yes
Yes
Yes
2-wire Serial Interface
Yes
Yes
Yes
UARTs
2
2
2
Watchdog Timer
Yes
Yes
Yes
Timer/Counters
3
3
3
Real-time Clock
Yes
Yes
Yes
JTAG ICE
Yes
Yes
Yes
Typical AVR
Throughput
@ 25 MHz
19 MIPS
19 MIPS
19 MIPS
@ 40 MHz
30 MIPS
30 MIPS
30 MIPS
Operating Voltage
3.0 - 3.6V
3.0 - 3.6V
3.0 - 3.6V
3
AT94S Secure Family
2314DFPSLI2/04
Figure 1. AT94S Architecture
The embedded AVR core achieves throughputs approaching 1 MIPS per MHz by exe-
cuting powerful instructions in a single-clock-cycle, and allows system designers to
optimize power consumption versus processing speed. The AVR core is based on an
enhanced RISC architecture that combines a rich instruction set with 32 general-pur-
pose working registers. All 32 registers are directly connected to the Arithmetic Logic
Unit (ALU), allowing two independent registers to be accessed in one single instruction
executed in one clock cycle. The resulting architecture is more code-efficient while
achieving throughputs up to ten times faster than conventional CISC microcontrollers at
the same clock frequency. The AVR executes out of on-chip SRAM. Both the FPGA
configuration SRAM and AVR instruction code SRAM are automatically loaded at sys-
tem power-up using Atmel's in-system programmable AT17 Series EEPROM
configuration memories, which are part of the AT94S Multi-chip Module (MCM).
State-of-the-art FPSLIC design tools, System Designer
TM
, were developed in conjunc-
tion with the FPSLIC architecture to help reduce overall time-to-market by integrating
microcontroller development and debugging, FPGA development, place and route, and
complete system co-verification in one easy-to-use software tool.
5 - 40K Gates FPGA
Up to
16K x 8
Data
SRAM
Up to 16K x 16
Program
SRAM Memory
PROGRAMMABLE I/O
with
Multiply
Two 8-bit
Timer/Counters
16 Prog. I/O
Lines
I/O
I/O
I/O
2-wire Serial
Unit
Up to 16 Interr
upt Lines
Up to 16
Decoded
Address Lines
4 Interrupt Lines
Configuration Logic
Configuration
EEPROM
I/O
For ISP
and Chip
Erase
Two Serial
UARTs
4
AT94S Secure Family
2314DFPSLI2/04
Internal Architecture
For details of the AT94S Secure FPSLIC architecture, please refer to the AT94K
FPSLIC datasheet and the AT17 Series Configuration Memory datasheet, available on
the Atmel web site at http://www.atmel.com. This document only describes the differ-
ences between the AT94S Secure FPSLIC and the AT94K FPSLIC.
FPSLIC and
Configurator
Interface
Fully In-System Programmable and Re-programmable
When Security Bit Set:
Data Verification Disabled
Data Transfer to FPSLIC not Externally Visible
Secured EEPROM Will Only Boot the FPSLIC Device or Respond to a Chip
Erase
When Security Bit Cleared:
Entire Chip Erase Performed
In-System Programming Enabled
Data Verification Enabled
External Data pins allow for In-System Programming of the device and setting of the
EEPROM-based security bit. When the security bit is set (active) this programming con-
nection will only respond to a device erase command. Data cannot be read out of the
external programming/data pins when the security bit is set. The part can be re-pro-
grammed, but only after first being erased.
Programming and
Configuration Timing
Characteristics
Atmel's Configurator Programming Software (CPS), available from the Atmel web site
(http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3191), creates the pro-
gramming algorithm for the embedded configurator; however, if you are planning to
write your own software or use other means to program the embedded configurator, the
section below includes the algorithm and other details.
The FPSLIC Configurator
The FPSLIC Configurator is a serial EEPROM memory which is used to load program-
mable devices. This document describes the features needed to program the
Configurator from within its programming mode (i.e., when SER_EN is driven Low).
Reference schematics are supplied for ISP applications.
Serial Bus Overview
The serial bus is a two-wire bus; one wire (cSCK) functions as a clock and is provided
by the programmer, the second wire (cSDA) is a bi-directional signal and is used to pro-
vide data and control information.
Information is transmitted on the serial bus in messages. Each MESSAGE is preceded
by a Start Condition and ends with a Stop Condition. The message consists of an inte-
ger number of bytes, each byte consisting of 8 bits of data, followed by a ninth
Acknowledge Bit. This Acknowledge Bit is provided by the recipient of the transmitted
byte. This is possible because devices may only drive the cSDA line Low. The system
must provide a small pull-up current (1 k
equivalent) for the cSDA line.
The MESSAGE FORMAT for read and write instructions consists of the bytes shown in
"Bit Format" on page 5.
While writing, the programmer is responsible for issuing the instruction and data. While
reading, the programmer issues the instruction and acknowledges the data from the
Configurator as necessary.
5
AT94S Secure Family
2314DFPSLI2/04
Again, the Acknowledge Bit is asserted on the cSDA line by the receiving device on a
byte-by-byte basis.
The factory blanks devices to all zeros before shipping. The array cannot otherwise be
"initialized" except by explicitly writing a known value to each location using the serial
protocol described herein.
Bit Format
Data on the cSDA pin may change only during the cSCK Low time; whereas Start and
Stop Conditions are identified as transitions during the cSCK High time.
Write Instruction Message Format
Current Address Read (Extended to Sequential Read) Instruction Message Format
Start and Stop
Conditions
The Start Condition is indicated by a high-to-low transition of the cSDA line when the
cSCK line is High. Similarly, the Stop Condition is generated by a low-to-high transition
of the cSDA line when the cSCK line is High, as shown in Figure 2.
The Start Condition will return the device to the state where it is waiting for a Device
Address (its normal quiescent mode).
The Stop Condition initiates an internally timed write signal whose maximum duration is
t
WR
(refer to AC Characteristics table for actual value). During this time, the Configurator
must remain in programming mode (i.e., SER_EN is driven Low). cSDA and cSCK lines
are ignored until the cycle is completed. Since the write cycle typically completes in less
than t
WR
seconds, we recommend the use of "polling" as described in later sections.
Input levels to all other pins should be held constant until the write cycle has been
completed.
Acknowledge Bit
The Acknowledge (ACK) Bit shown in Figure 2 is provided by the Configurator receiving
the byte. The receiving Configurator can accept the byte by asserting a Low value on
the cSDA line, or it can refuse the byte by asserting (allowing the signal to be externally
pulled up to) a High value on the cSDA line. All bytes from accepted messages must be
terminated by either an Acknowledge Bit or a Stop Condition. Following an ACK Bit,
when the cSDA line is released during an exchange of control between the Configurator
and the programmer, the cSDA line may be pulled High temporarily due to the open-col-
lector output nature of the line. Control of the line must resume before the next rising
edge of the clock.
ACK BIT
(CONFIGURATOR)
DATA
BYTE n
STOP
CONDITION
START
CONDITION
DEVICE
ADDRESS
MS EEPROM
ADDRESS BYTE
(NEXT) EEPROM
ADDRESS BYTE
LS EEPROM
ADDRESS BYTE
DATA
BYTE 1
ACK BIT
(CONFIGURATOR)
DATA
BYTE n
STOP
CONDITION
START
CONDITION
DEVICE
ADDRESS
DATA
BYTE 1
ACK BIT
(PROGRAMMER)
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