1
Features
High-density, High-performance, Electrically-erasable Complex
Programmable Logic Device
128 Macrocells
5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
84, 100, 160 Pins
7.5 ns Maximum Pin-to-pin Delay
Registered Operation up to 125 MHz
Enhanced Routing Resources
Flexible Logic Macrocell
D/T/Latch Configured Flip-flops
Global and Individual Register Control Signals
Global and Individual Output Enable
Programmable Output Slew Rate
Programmable Output Open Collector Option
Maximum Logic Utilization by Burying a Register within a COM Output
Advanced Power Management Features
Automatic 10 A Standby for "L" Version
Pin-controlled 1 mA Standby Mode
Programmable Pin-keeper Inputs and I/Os
Reduced-power Feature per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 84-lead PLCC, 100-lead PQFP, 100-lead TQFP and 160-lead PQFP Packages
Advanced EE Technology
100% Tested
Completely Reprogrammable
10,000 Program/Erase Cycles
20-year Data Retention
2000V ESD Protection
200 mA Latch-up Immunity
JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
Fast In-System Programmability (ISP) via JTAG
PCI-compliant
3.3 or 5.0V I/O Pins
Security Fuse Feature
Enhanced Features
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
Transparent-latch Mode
Combinatorial Output with Registered Feedback within Any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
Fast Registered Input from Product Term
Programmable "Pin-keeper" Option
V
CC
Power-up Reset Option
Pull-up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
Edge-controlled Power-down "L"
Individual Macrocell Power Option
Disable ITD on Global Clocks, Inputs and I/O for "Z" Parts
High-
performance
EE PLD
ATF1508AS
ATF1508ASL
Rev. 0784OPLD09/02
2
ATF1508AS(L)
0784OPLD09/02
84-lead PLCC
Top View
100-lead TQFP
Top View
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
I/O/PD1
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O/TMS
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
GND
I/O/TDO
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/TCK
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
11
10
9
8
7
6
5
4
3
2
1
84
83
82
81
80
79
78
77
76
75
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
GND
VCCINT
I/O
I/O/PD2
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
VCCIO
I/O
I/O
I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O/PD1
I/O
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O/TMS
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O/TDO
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/TCK
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
GND
VCCINT
I/O
I/O/PD2
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
100-lead PQFP
Top View
160-lead PQFP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
I/O
I/O/PD1
I/O
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O/TMS
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O/TDO
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/TCK
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
GND
VCCINT
I/O
I/O/PD2
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
VCCIO
I/O
I/O
I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
N/C
N/C
N/C
N/C
N/C
N/C
N/C
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O/TMS
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
GND
I/O/TDO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O/TCK
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N/C
N/C
N/C
N/C
N/C
N/C
N/C
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I/O
GND
I/O
N/C
N/C
N/C
N/C
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
GND
VCCINT
I/O
I/O/PD1
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N/C
N/C
N/C
N/C
I/O
VCCIO
I/O
I/O
I/O/PD2
I/O
N/C
N/C
N/C
N/C
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
N/C
N/C
N/C
N/C
I/O
I/O
I/O
3
ATF1508AS(L)
0784OPLD09/02
Block Diagram
8 to 12
16
4
ATF1508AS(L)
0784OPLD09/02
Description
The ATF1508AS is a high-performance, high-density complex programmable logic device
(CPLD) that utilizes Atmel's proven electrically-erasable technology. With 128 logic macrocells
and up to 100 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic
PLDs. The ATF1508AS's enhanced routing switch matrices increase usable gate count and
increase odds of successful pin-locked design modifications.
The ATF1508AS has up to 96 bi-directional I/O pins and four dedicated input pins, depending
on the type of device package selected. Each dedicated pin can also serve as a global control
signal, register clock, register reset or output enable. Each of these control signals can be
selected for use individually within each macrocell.
Each of the 128 macrocells generates a buried feedback that goes to the global bus. Each
input and I/O pin also feeds into the global bus. The switch matrix in each logic block then
selects 40 individual signals from the global bus. Each macrocell also generates a foldback
logic term that goes to a regional bus. Cascade logic between macrocells in the ATF1508AS
allows fast, efficient generation of complex logic functions. The ATF1508AS contains eight
such logic chains, each capable of creating sum term logic with a fan-in of up to 40 product
terms.
The ATF1508AS macrocell, shown in Figure 1, is flexible enough to support highly-complex
logic functions operating at high speed. The macrocell consists of five sections: product terms
and product term select multiplexer; OR/XOR/CASCADE logic, a flip-flop, output select and
enable, and logic array inputs.
Unused macrocells are automatically disabled by the compiler to decrease power consump-
tion. A security fuse, when programmed, protects the contents of the ATF1508AS. Two bytes
(16 bits) of User Signature are accessible to the user for purposes such as storing project
name, part number, revision or date. The User Signature is accessible regardless of the state
of the security fuse.
The ATF1508AS device is an in-system programmable (ISP) device. It uses the industry-stan-
dard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG's Boundary-
scan Description Language (BSDL). ISP allows the device to be programmed without remov-
ing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also
allows design modifications to be made in the field via software.
Product Terms and
Select Mux
Each ATF1508AS macrocell has five product terms. Each product term receives as its inputs
all signals from both the global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the five product terms as needed to
the macrocell logic gates and control signals. The PTMUX programming is determined by the
design compiler, which selects the optimum macrocell configuration.
OR/XOR/
CASCADE Logic
The ATF1508AS's logic structure is designed to efficiently support all types of logic. Within a
single macrocell, all the product terms can be routed to the OR gate, creating a 5-input
AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be
expanded to as many as 40 product terms with a little small additional delay.
The macrocell's XOR gate allows efficient implementation of compare and arithmetic func-
tions. One input to the XOR comes from the OR sum term. The other XOR input can be a
product term or a fixed high- or low-level. For combinatorial outputs, the fixed level input
allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimiza-
tion of product terms. The XOR gate is also used to emulate T- and JK-type flip-flops.
5
ATF1508AS(L)
0784OPLD09/02
Flip-flop
The ATF1508AS's flip-flop has very flexible data and control functions. The data input can
come from either the XOR gate, from a separate product term or directly from the I/O pin.
Selecting the separate product term allows creation of a buried registered feedback within a
combinatorial output macrocell. (This feature is automatically implemented by the fitter soft-
ware). In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flow-
through latch. In this mode, data passes through when the clock is high and is latched when
the clock is low.
The clock itself can be either the Global CLK Signal (GCK) or an individual product term. The
flip-flop changes state on the clock's rising edge. When the GCK signal is used as the clock,
one of the macrocell product terms can be selected as a clock enable. When the clock enable
function is active and the enable signal (product term) is low, all clock edges are ignored. The
flip-flop's asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product
term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchro-
nous preset (AP) can be a product term or always off.
Extra Feedback
The ATF15xxSE Family macrocell output can be selected as registered or combinatorial. The
extra buried feedback signal can be either combinatorial or a registered signal regardless of
whether the output is combinatorial or registered. (This enhancement function is automatically
implemented by the fitter software.) Feedback of a buried combinatorial output allows the cre-
ation of a second latch within a macrocell.
I/O Control
The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be indi-
vidually configured as an input, output or for bi-directional operation. The output enable for
each macrocell can be selected from the true or compliment of the two output enable pins, a
subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done
by the fitter software when the I/O is configured as an input, all macrocell resources are still
available, including the buried feedback, expander and cascade logic.
Global Bus/Switch
Matrix
The global bus contains all input and I/O pin signals as well as the buried feedback signal from
all 128 macrocells. The switch matrix in each logic block receives as its inputs all signals from
the global bus. Under software control, up to 40 of these signals can be selected as inputs to
the logic block.
Foldback Bus
Each macrocell also generates a foldback product term. This signal goes to the regional bus
and is available to 16 macrocells. The foldback is an inverse polarity of one of the macrocell's
product terms. The 16 foldback terms in each region allows generation of high fan-in sum
terms (up to 21 product terms) with a little additional delay.
3.3V or 5.0V I/O
Operation
The ATF1508AS device has two sets of V
CC
pins viz, V
CCINT
and V
CCIO
. V
CCINT
pins must
always be connected to a 5.0V power supply. V
CCINT
pins are for input buffers and are "com-
patible" with both 3.3V and 5.0V inputs. V
CCIO
pins are for I/O output drives and can be
connected for 3.3/5.0V power supply.
Open-collector
Output Option
This option enables the device output to provide control signals such as an interrupt that can
be asserted by any of the several devices.
PDF 
ZIP