Top view
ATF16V8C
High
Performance
E
2
PLD
ATF16V8C
Pin Configurations
Pin Name
Function
CLK
Clock
I
Logic Inputs
I/O
Bidirectional Buffers
OE
Output Enable
VCC
+5V Supply
PD
Power Down
Features
Industry Standard Architecture
Emulates Many 20-Pin PALs
Low Cost Easy-to-Use Software Tools
High Speed Electrically Erasable Programmable Logic Devices
5 ns Maximum Pin-to-Pin Delay
Low Power - 100
A Pin-Controlled Power Down Mode Option
CMOS and TTL Compatible Inputs and Outputs
I/O Pin Keeper Circuits
Advanced Flash Technology
Reprogrammable
100% Tested
High Reliability CMOS Process
20 Year Data Retention
100 Erase/Write Cycles
2,000V ESD Protection
200 mA Latchup Immunity
Commercial and Industrial Temperature Ranges
Dual-in-Line and Surface Mount Packages in Standard Pinouts
Block Diagram
Note:
1. Includes optional PD control pin.
DIP/SOIC
PLCC
Rev. 0425D/V16FC-D04/98
TSSOP Top View
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
I/CLK
I1
I2
PD/I3
I4
I5
I6
I7
I8
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I9/OE
Temperature Under Bias................... -40C to +85C
Storage Temperature...................... -65C to +150C
Voltage on Any Pin with
Respect to Ground......................... -2.0V to +7.0V
(1)
Voltage on Input Pins
with Respect to Ground
During Programming.................... -2.0V to +14.0V
(1)
Programming Voltage with
Respect to Ground....................... -2.0V to +14.0V
(1)
*NOTICE: Stresses beyond those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Absolute Maximum Ratings*
Note:
1. Minimum voltage is -0.6V dc, which may undershoot to -
2.0V for pulses of less than 20 ns. Maximum output pin
voltage is Vcc + 0.75V dc, which may overshoot to 7.0V
for pulses of less than 20 ns.
DC and AC Operating Conditions
Commercial
Industrial
Operating Temperature (Case)
0C - 70C
-40C - 85C
V
CC
Power Supply
5V
5%
5V
10%
The ATF16V8C is a high performance EECMOS Pro-
grammable Logic Device that utilizes Atmel's proven elec-
trically erasable Flash memory technology. Speeds down
to 5 ns and a 100
A pin-controlled power down mode op-
tion are offered. All speed ranges are specified over the
full 5V
10% range for industrial temperature ranges; 5V
5% for commercial range 5-volt devices.
The ATF16V8C incorporates a superset of the generic ar-
chitectures, which allows direct replacement of the 16R8
family and most 20-pin combinatorial PLDs. Eight outputs
are each allocated eight product terms. Three different
modes of operation, configured automatically with soft-
ware, allow highly complex logic functions to be realized.
The ATF16V8C can significantly reduce total system
power, thereby enhancing system reliability and reducing
power supply costs. When pin 4 is configured as the
power down control pin , supply current drops to less than
100
A whenever the pin is high. If the power down fea-
ture isn't required for a particular application, pin 4 may be
used as a logic input. Also, the pin keeper circuits elimi-
nate the need for internal pull-up resistors along with their
attendant power consumption.
Description
2
ATF16V8C
DC Characteristics
Symbol Parameter
Condition
Min
Typ
Max
Units
I
IL
Input or I/O Low
Leakage Current
0
V
IN
V
IL
(MAX)
-10
A
I
IH
Input or I/O High
Leakage Current
3.5
V
IN
V
CC
10
A
I
CC1
(1)
Power Supply Current,
Standby
15 MHz, V
CC
= MAX,
V
IN
= 0, V
CC,
Outputs
Open
Com.
115
mA
Ind.
130
mA
I
PD
Power Supply Current,
Power Down Mode
V
CC
= MAX,
V
IN
= 0, V
CC
Com.
10
100
A
Ind.
10
105
A
I
OS
Output Short Circuit
Current
V
OUT
= 0.5V;
V
CC
= 5V; TA = 25C
-150
mA
V
IL
Input Low Voltage
MIN < V
CC
< MAX
-0.5
0.8
V
V
IH
Input High Voltage
2.0
V
CC
+ 1
V
V
OL
Output Low Voltage
V
CC
= MIN; All Outputs
I
OL
= 24 mA
Com., Ind.
0.5
V
V
OH
Output High Voltage
V
CC
= MIN
I
OL
= -4.0 mA
2.4
V
I
OL
Output Low Current
V
CC
= MIN
Com.
24
mA
Ind.
12
mA
I
OH
Output High Current
V
CC
= MIN
Com., Ind.
-4
mA
Note: 1. All
I
CC
parameters measured with outputs open.
AC Waveforms
(1)
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
ATF16V8C
3
AC Characteristics
Symbol Parameter
-5
-7
Min
Max
Min
Max
Units
t
PD
Input or Feedback to Non-Registered
Output
1
5
3
7.5
ns
t
CF
Clock to Feedback
3
3
ns
t
CO
Clock to Output
1
4
2
5
ns
t
S
Input or Feedback Setup Time
3
5
ns
t
H
Input Hold Time
0
0
ns
t
P
Clock Period
6
8
ns
t
W
Clock Width
3
4
ns
F
MAX
External Feedback 1/(t
S
+ t
CO
)
142
100
MHz
Internal Feedback 1/(t
S
+ t
CF
)
166
125
MHz
No Feedback 1/(t
P
)
166
125
MHz
t
EA
Input to Output Enable --
Product Term
2
6
3
9
ns
t
ER
Input to Output Disable --
Product Term
2
5
2
9
ns
t
PZX
OE pin to Output Enable
2
5
2
6
ns
t
PXZ
OE pin to Output Disable
1.5
5
1.5
6
ns
Power Down AC Characteristics
(1, 2, 3)
Symbol Parameter
-5
-7
Min
Max
Min
Max
Units
t
IVDH
Valid Input Before PD High
5
7.5
ns
t
GVDH
Valid OE Before PD High
0
0
ns
t
CVDH
Valid Clock Before PD High
0
0
ns
t
DHIX
Input Don't Care After PD High
5
7.5
ns
t
DHGX
OE Don't Care After PD High
5
7.5
ns
t
DHCX
Clock Don't Care After PD High
5
7.5
ns
t
DLIV
PD Low to Valid Input
5
7.5
ns
t
DLGV
PD Low to Valid OE
15
20
ns
t
DLCV
PD Low to Valid Clock
15
20
ns
t
DLOV
PD Low to Valid Output
20
25
ns
Notes: 1. Output data is latched and held.
2. HI-Z outputs remain HI-Z.
3. Clock and input transitions are ignored.
4
ATF16V8C
Power Up Reset
The ATF16V8C's registers are designed to reset during
power up. At a point delayed slightly from V
CC
crossing
V
RST
, all registers will be reset to the low state. As a result,
the registered output state will always be high on power-
up.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the un-
certainty of how V
CC
actually rises in the system, the fol-
lowing conditions are required:
1) The V
CC
rise must be monotonic, from below .7 volts,
2) After reset occurs, all input and feedback setup times
must be met before driving the clock term high, and
3) The signals from which the clock is derived must re-
main stable during t
PR
.
Parameter Description
Typ
Max
Units
t
PR
Power-Up
Reset Time
600
1,000
ns
V
RST
Power-Up
Reset
Voltage
3.8
4.5
V
Commercial
Output Test Loads:
Input Test Waveforms and
Measurement Levels:
t
R
, t
F
< 1.5ns (10% to 90%)
Pin Capacitance
(f = 1 MHz, T = 25C)
(1)
Typ
Max
Units
Conditions
C
IN
5
8
pF
V
IN
= 0V
C
OUT
6
8
pF
V
OUT
= 0V
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
ATF16V8C
5
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